In SoC development, the verification cycle is a crucial phase that ensures products meet their specifications and function correctly. However, the complexity of modern SoC projects, with their constant data flow, multiple validation teams working in parallel, and tight schedules, presents significant challenges. This article explores these challenges and introduces Verisium Manager as a solution that embodies the 'One Tool Fits All' concept. This means that Verisium Manager is designed to handle all aspects of the verification process for SoC development, from planning to coverage analysis to regression testing, thereby addressing the complex needs of SoC verification.

The Hurdles in Traditional Validation Cycles

 A typical validation process involves planning, coverage analysis, and regression testing. This complexity is compounded by using separate tools for each activity, leading to multiple control environments, APIs, and databases, not to mention the array of tool owners. Such fragmentation results in constant data transfer and translation between systems, from the planning tool to the coverage analysis tool and then to the regression testing tool. This continuous movement of data causes delays, system instability, poor user experiences, and, ultimately, a dip in the quality of the validation process.

The use of multiple platforms leads to inefficiency and reduced productivity. What's needed is a unified system that can streamline the workflow, simplify the verification process, and enhance its effectiveness.

Envisioning the Ideal Solution: Verisium Manager

 The cornerstone of an efficient validation cycle is integration and simplicity. The ideal solution is a singular platform that consolidates planning, coverage analysis, and regression management into one smooth, unified process. Verisium Manager emerges as this much-needed solution, encompassing all the functionalities necessary to streamline the validation process. Its comprehensive nature instills confidence in its ability to handle all aspects of the verification cycle. It can be fully customized to address and enforce any validation methodology and can facilitate smooth integration into any customer environment.

Features that stand out in Verisium Manager include: 

• Unified Workflow: It acts as a single cockpit from which all activities are orchestrated, ensuring the validation teams' work is uninterrupted and seamlessly integrated.
• Customization and Integration: Verisium Manager supports customizing test-plan structures and mapping results per project, ensuring a perfect fit for various project requirements. Its ability to smoothly integrate into the project's environment and compute platforms is unparalleled.
• Support for Continuous Updates and Migration: The tool accommodates constant updates to project data and supports the migration of legacy data, ensuring that no historical data is lost in the transition to a new system.

Addressing Project-Specific Needs

 Verisium Manager recognizes diversity in different projects and offers project-specific solutions, including:

 Enforcing Project Test-Plan Structures and Attributes: It supports and enforces each project's unique test-plan structure and mapping guidelines.

• Unified Data Views and Measurements: Verisium Manager promotes a unified view of data across all teams and enforces unified measurements, ensuring consistency and clarity in the validation process.
• Enabling Project-Specific Actions and Integrations: The tool is designed to support project-specific actions directly from its graphical user interface and allows for smooth integration with in-house databases, dashboards, and the project execution stack.

Verisium Manager is the epitome of efficiency in software/hardware validation. Its differentiating features, such as support for customization, unified data view, and comprehensive coverage and regression requirements, make it an indispensable tool for any validation team looking to elevate their workflow.

Hearing is one of the most essential senses for engaging with the world. It enables us to converse, appreciate music, and remain alert to our surroundings. Hearing loss is a prevalent issue affecting millions of individuals globally and disconnecting them from a world where sound is vital to others and the environment. The World Health Organization (WHO) reports that over 5% of the global population requires hearing rehabilitation, a striking statistic highlighting this issue's pervasive nature. Technology has transformed audiology, evolving from simple ear trumpets to sophisticated modern hearing aids. This advancement began with the invention of the transistor, paving the way for devices that are fully wearable inside or behind the ear. Although hearing aids have been available for many years, historically, access to these critical devices has been insufficient, resulting in numerous individuals lacking the necessary support. However, recent advances in hearing aid technology promise improved acoustic experiences, employing modern techniques like binaural processing and neural networks. These innovations demand sophisticated architecture to balance high memory needs with low power consumption in a user-friendly design. Cadence is at the forefront of this technological evolution, offering tools and IP solutions that enhance the accessibility, efficiency, and impact of hearing aids, paving the way for a more inclusive future. This blog explores how Cadence's advanced DSPs are transforming hearing aid design and making them more accessible, efficient, and impactful. Hearing Aids: A Testament to Human Ingenuity The transition from analo g to digital technology in the late 20th century further transformed hearing aids, offering superior sound quality, customization, and the ability to connect to various electronic devices, thus enhancing the user experience markedly. Today's hearing aids are highly effective, versatile, and nearly invisible, a significant advancement from early attempts to address hearing loss. They also feature advanced noise cancellation and connectivity options, allowing users to integrate seamlessly into the digital world. This progression not only highlights the industry's commitment to improving user experience and accessibility but also offers a glimpse into a future where hearing loss is no longer a barrier. Challenges Despite advancements and sophistication, there are several challenges related to hearing aid design and adoption. Users demand smaller, more discreet devices that don't sacrifice performance. While the shift towards sleeker designs is aesthetically pleasing, it introduces substantial complexities in product design. Designers face the challenges of integrating essential components, such as batteries and peripherals, into increasingly compact spaces. Power consumption remains a critical concern, as these devices must remain operational throughout the day. Leveraging neural networks to enhance the signal-to-noise ratio (SNR) for better quality demands additional memory capacity. Consequently, there is a pressing need for flexible, low-power architectures that incorporate all necessary memory and peripherals without compromising the device’s compact size. Adopting AI for adjusting hearing aid volume to fit an individual's specific auditory requirements is a significant challenge and demands more memory and effort. Besides this, reliability and cost are significant challenges for manufacturers. Cadence's Role in Transforming Hearing Aids In hearing aid development, the capacity to evaluate the energy efficiency of SoCs across different frequencies in real time is crucial. These applications demand cohesive, energy-efficient solutions that can uphold high performance. The Cadence Tensilica HiFi and Fusion F1 DSP family emphasize minimal power usage while providing robust performance, ideally suited for a wide range of audio and voice applications. The Cadence Tensilica HiFi DSP family, a high-performance audio technology with AI acceleration and advanced DSP capability, offers feature-rich audio, speech, and imaging for wearables, automotive, home entertainment, digital assistants, and ASR. The Tensilica HiFi DSP family accelerates innovation with its comprehensive instruction set and supports fixed- and floating-point data types. Simplifying software development, it offers C/C++ programming, an auto-vectorizing compiler, and a rich DSP software library through the Cadence Tensilica Xplorer development environment. With the flexibility to customize and enhance performance through additional instructions and better I/O bandwidth, the Tensilica HiFi and Fusion DSP families offer a robust, low-energy audio solution compatible across an expansive software ecosystem for various applications and devices. Conclusion Technological advancements are driving hearing aid evolution; the future of hearing aids lies in further miniaturization and functionality enhancement. Cadence's ongoing innovations aim to improve signal processing and noise reduction, even in challenging environments. The integration of neural networks promises more apparent sound transmission and greater adaptability. Cadence is working on improving how these devices process signals and reduce noise and has initiated a collaborative venture with distinguished entities like GlobalFoundries (GF), Hoerzentrum Oldenburg gGmbH, and Leibniz University Hannover. This collaboration has borne fruit in the form of the industry's first binaural hearing aid system-on-chip (SoC) prototype, the Smart Hearing Aid Processor ( SmartHeAP ). Learn More Cadence, GlobalFoundries, Hoerzentrum Oldenburg and Leibniz University Hannover Collaborate to Advance Hearing Aid Technology Cadence Extends Battery Life and Improves User Experience for Next-Generation Hearables, Wearables and Always-On Devices Advancing the Future of Hearing Aids with Cadence Bluetooth LE Audio, Hearing Aids, and Mindtree

The demand for higher compute performance, energy efficiency, and faster time-to-market drove the conversations at this year's Open Compute Project (OCP) Global Summit in San Jose, California. It was the scene of showcasing groundbreaking innovations, expert-led sessions, and networking opportunities to drive the future of data center technology. For those who didn't get to attend or stop by our booth, here's a recap of Cadence's comprehensive solutions that enable next-generation compute technology, AI data center design, analysis, and optimization. Optimized Data Center Design and Operations As the data center community increasingly faces demands for enhanced efficiency, thermal management, sustainability, and performance optimization, data center operators, IT managers, and executives are looking for solutions to these challenges. At the Cadence booth, attendees explored the Cadence Reality Digital Twin Platform and Celsius EC Solver. These technologies are pivotal in achieving high-performance standards for AI data centers, providing advanced digital twin modeling capabilities that redefine next-generation data center design and operation. The Celsius EC Solver demonstration showed how it solves challenging thermal and electronics cooling management problems with precision and speed. CadenceCONNECT: Take the Heat Out of Your AI Data Center Cadence hosted a networking reception on October 16 titled "Take the Heat Out of Your AI Data Center." In today's AI era, managing the heat generated by high-density computing environments is more critical than ever. This reception offered insights into current and emerging data center technologies, digital twin cooling strategies that deliver energy-saving operations, and a chance to engage with industry leaders, Cadence experts, and peers to explore the latest cooling, AI, and GPU acceleration advancements. Here's a recap: Researcher, author, and entrepreneur Dr. Jon Koomey highlighted the inefficiency of data centers in his talk "The Rise of Zombie Data Centers," noting that 20-30% of their capacity is stranded and unused. He advocated for organizational changes and technological solutions like digital twins to reduce wasted energy and improve computational effectiveness as AI deployments increase. In "A New Millennium in Multiphysics System Analysis," Cadence Corporate VP Ben Gu explained the company's significant strides in multiphysics system analysis, evolving from chip simulation to a broader application of computational software for simulating various physical systems, including entire data centers. He noted that the latest Cadence venture, a digital twin platform for data center optimization, opened the opportunity to use simulation technology to optimize the efficiency of data centers. Senior Software Engineering Group Director Albert Zeng highlighted the Cadence Reality DC suite's ability to transform data center operations through simulation, emphasizing its multi-phase engine for optimal thermal performance and the integration of AI capabilities for enhanced design and management. A panel discussion titled "Turning AI Factory Blueprints into Reality at the Speed of Light" featured industry experts from NVIDIA, Norman Wright Precision Environmental and Power, NV5, Switch Data Centers, and Cadence, who explored the evolving requirements and multidimensional challenges of AI factories, emphasizing the need for collaboration across the supply chain to achieve high-performing and sustainable data centers. Watch the highlights. Transforming Designs from Chips to Data Centers The OCP Global Summit 2024 has reaffirmed its status as a pivotal event for data center professionals seeking to stay at the forefront of technological advancements. Cadence's contributions, from groundbreaking digital twin technologies to innovative cooling strategies, have shed light on the path forward for efficient, sustainable data centers. For data center professionals, IT managers, and engineers, the insights gained at this summit are invaluable in navigating the challenges and opportunities presented by the burgeoning AI era. Partnering with Arm Arm Total Design Cadence is a member of the Arm Total Design program. At an invitation-only special Arm event, Cadence's VP of Research and Development, Lokesh Korlipara, delivered a presentation focusing on data center challenges and design solutions with Arm Neoverse Compute Subsystem (CSS). The session highlighted: Efficient integration of Arm Neoverse CSS into system on chips (SoCs) with pre-integrated connectivity IP Performance analysis and verification of the Neoverse CSS integration into the SoC through Cadence's System VIP verification suite and automated testbench creation, enhancing both quality and productivity Jumpstarting designs through Cadence's collaboration with Arm for 3D-IC system planning, chiplets, and interposers Design Services readiness and global scale to support and/or deliver the most demanding Arm Neoverse CSS-based SoC design projects Cadence Supports Arm CSS in Arm Booth During the event, Cadence conducted a demo in the Arm booth that showcased the Cadence System VIP verification suite. The demo highlighted automated testbench creation and performance analysis for integrating the Arm CSS into SoCs while enhancing verification quality and productivity. Summary Cadence offers data center solutions for designing everything from the compute and networking chips to the board, racks, data centers, and campuses. Stay connected with Cadence and other industry leaders to continue exploring the innovations set to redefine the future of data centers. Learn More Cadence Joins Arm Total Design Cadence Arm-Based Solutions Cadence Reality Digital Twin Platform

Each November, we are reminded of the bravery and dedication of those who have served our country. At Cadence, we thank our Veteran employees for their patriotism by reaffirming our commitment to honoring their sacrifices and recognizing their contributions to our business success. Our diverse and inclusive culture is strengthened by the unique perspective of our Veteran employees, and we are proud to support the Veterans Inclusion Group as a space for community members and their allies to connect. In celebration of Veterans Day, we were excited to catch up with Johnathan Edmonds, Veterans Inclusion Group Lead and Design Engineering Director, for a heartfelt chat on his journey through military service to leadership within Cadence. Throughout the conversation, he shared the importance of creating space for Veterans, the skills they offer, and his aspirations for what the Veterans Inclusion Group will achieve in the years ahead. Oh yeah, and he flies planes, too! Join us as we dive into what makes this holiday special for so many across the nation and how we can respectfully commemorate it together. Johnathan, you’re a retired Air Force Reservist, pilot, and now a Design Engineering Director. Can you tell us about your journey from the military to your current role at Cadence? I started my military and electronics journey in the Navy. I enlisted at 18 and served for six years as an aviation electronics technician. During this time, I was able to learn about and repair electronics on planes. This set me up for success, and when I was honorably discharged, I attended Virginia Tech to study computer engineering. Once I graduated, I continued my career as an engineer, but I still wanted to be a military pilot. From my past experience, I knew the reserves were an option where I could learn to fly and still have a civilian career. Not only was I lucky enough to get selected to go to pilot training, but after I returned from flight school, my luck grew, and I was hired at Cadence. Cadence has supported me throughout my military career, which has been a great benefit, as many companies don’t support reservists. The best thing about serving and being employed at Cadence is how I could blend my skill sets to further the Air Force’s mission and achieve great things in engineering. As the first lead of Cadence’s Veterans Inclusion Group, you played an integral part in growing our culture and building community at the company since launching the group four years ago. What inspired you to take on the role of Inclusion Group Lead? I was inspired by three things: camaraderie, service, and outreach. I wanted to see if we could achieve a similar sense of community through the Veterans Inclusion Group as we had during our service life. I also wanted to see how we could better serve our Veterans here at Cadence. I wanted to explore any benefits that could be expanded, roles that could be developed by Vets, and, lastly, I wanted to serve a broader community. COVID-19 put a damper on some of the community support, but we are getting back on track with Veteran employment programs and volunteer efforts like Carry the Load and Gold Star Families. Why is it important to have this space dedicated to Veteran employees? There are many reasons! Networking, for one, creates a stronger, more unified Cadence culture. Two, Vets face a variety of issues not generally understood by those who have not served, such as PTSD, where to get help for disabilities, how to get an old medical record, etc. As I mentioned, I’m also passionate about connecting Veterans with employment and job opportunities. It is so nice to work for a company that actively recruits Vets. We have our own “language,” if you will, so it’s nice to have a space to talk in the language that we are familiar with. What have been some of your favorite moments leading this group over the past few years? Are there any “wins” that you would like to recognize? We have a lot of wins. Events held during COVID-19 and getting past COVID-19, donating to worthwhile causes, and hosting guest speakers are all fantastic milestones and accomplishments. That said, the biggest win is the hiring of new Veteran employees. Mark Murphy, Corporate VP of Sales Operations, and I have both welcomed Vets to our team during this time, and it is such a joy to watch what someone can do when given the opportunity to succeed in the right environment. As you are set to transition out of the lead role next year, what do you hope to see the Veterans Inclusion Group accomplish next? My hope is that the Veterans Inclusion Group partners with other companies, expanding our reach externally and exploring new opportunities to engage Veterans outside of Cadence. Johnathan (left) speaks on an inclusion group panel, along with David Sallard (center), lead of Cadence's Black Inclusion Group and Sr. Principal Application Engineer; Christina Jamerson (on screen), lead of Cadence's Abilities Inclusion Group and Demand Generation Director; and Dianne Rambke (right), lead of Cadence's Latinx Inclusion Group and Marketing Communications Director. What are the important ways that people can signal inclusion and respectfully honor Veterans at work? What are the most meaningful or impactful actions employees everywhere can take to support Veteran coworkers? I think there is one answer to both questions. I recommend that people engage with their companies’ employee resource groups (ERGs) and have conversations with them. Opening up the lines of communication will lead to new paths in their journeys. What are you looking forward to in 2025, both personally and professionally? In 2025, professionally, I am looking forward to taking mixed-signal systems and verification to another level by including emulation, automatic model generation, and seeing which boundaries we can push in our SerDes and Chiplets products. Personally, I am looking forward to making my SXS street legal so I can drive places without getting a ticket, seeing my children participate in sports, church, and school, and taking my wife on vacation to Europe or somewhere else we can unplug. Learn more about Cadence’s Inclusion Groups, diverse culture, and commitment to belonging.

Hey, is it suitable to post here? I wanted a small yet robust amp for practicing while I travel. I wanted something that would fit in my pocket yet still be loud enough to hear.

Presented here is a amplifier based upon the LM386 Audio Amplifier.

There is a standard circuit in the data sheet that is an excellent place to start.

Materials needed:
1 - HM359 project box
1 - 668-1237 speaker
1 - BS6I battery conn
1 - CP1-3515 stereo jack
1 - SC1316 stereo jack
2 - 450-1742 knob
1 - 679-1856 switch
1- 3mm LED
1 - 10 ohm 1/4W resistor
1 - 10uF ceramic cap
1 - .05 uF ceramic cap
1 - 420 uF electrolytic cap
1 - 8 ohm resistor
2 - 51AADB24 10K pot
1 - HM1252 circuit board
1 - LM386N-4 amplifier

Wire and Solder
Step 1: Prep the enclosure

Careful planning is required the first time you free build a circuit. The circuit board has solder pads but not traces. You will have to use thin wire to make the connections for the circuit to work.

Begin by laying out the components on the circuit board that will need to pass through the enclosure. This enclosure has a removable top panel which will be used for the volume, gain and 1/4 inch stereo jack.

Space is limited to check for fit before drilling.

All drilling of the plastic should be done with a step drill bit. This will make the cleanest holes without breaking the plastic.

Lay out the pots a few spaces back but still in line with the desired position. mark the center of each pot shaft then drill with a step drill tot he tightest fitting hole size. Make a center mark between the pot holes then drill for the stereo jack

On the inside of the top cover position and mark where the speaker will go.

Make a template on grid paper the same size as the speaker.

Tape the template to the inside of the cover as shown then use a step bit to drill holes on the center of every square in the grid. This will form the speaker grille. clean up the holes.

Step 2: place the major components

Solder the pots to the circuit board as shown. then place the stereo jack(note in order to get the final fit I had to trim and modify the stereo jack housing a little)

Next, position and solder the switch on the circuit board and mark a space on the top cover that will need to be cut for the switch opening. Use a small file to cut the opening.

Use a sharp knife to bevel the edges of the switch hole to allow for easier operation.

Drill a hole in the side of the upper case for the headphone jack and fasten it in place. ( I had to recess the hole a bit for the retaining nut to grab)

Step 3: Build the circuit

The speaker is held in place by using 2 small brackets that come with the serial cable connector hood. ( I had a bunch around that would never be used)

Refer the the circuit shown from the datasheet and the datasheet for the LM386. The basic circuit only has the volume control while the datasheet shows how to add a gain control across pins 1 and 8 of the amplifier.

The speaker is wired in series with the headphone jack. The headphone jack has internal switches that shut the speaker off when the phones are plugged in.

I chose to use a chip socket for the amplifier which make prototyping easier since you do not have to worry about solder heating as much.

Carefully lay the circuit out on the board and begin wiring components together. I added a second pot and cap in series between pins 1 and 8 of the amp to be able to manually set the gain in addition to volume.

Check you connections with a multimeter before adding the amplifier.

I chose to add a LED indicator for power. This was done by using one side of switch contacts from the battery. The LED is in series with a 220 ohm resistor.

Assemble the case and insert the battery.

Step 4: Final notes

If the speaker is noisy while the headphones work normally, try reversing the speaker connections. If it does not correct the issue, connect a 8 ohm resistor across the speaker contacts.

You may have to place an insulating layer between the speaker and the place where the stereo jack comes through to prevent contact. This will be noted by a loud buzz.

You may have to add some foam in the battery compartment to stop the battery from banging around.

For reference, I've also read an article about amplifiers: http://www.apogeeweb.net/article/60.html

Thanks for reading!
​

Cadence_SPB_17.4-2019 + Matlab R2019a

请参考本文档中的步骤进行操作

1，打开BJT_AMP.opj

2，设置Matlab路径

3，打开BJT_AMP_SLPS.slx

4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作

5，添加模块

6，相同

7，打开pspsim.slx

8，相同

9，打开C： Cadence Cadence_SPB_17.4-2019 tools bin

orCEFSimpleUI.exe和orCEFSimple.exe

10，相同

我想问一下如何解决，非常感谢！

use the DBO function DboLib_RepalceCache to do the job of "Replace cache" 

in order to easy the job ,  type the code below . the code is a wrapper of the function metioned above

set lStatus [DboState]
set lSession $::DboSession_s_pDboSession
DboSession -this $lSession
set lDesignsIter [$lSession NewDesignsIter $lStatus]
set lDesign [$lDesignsIter NextDesign $lStatus]
set lNullObj NULL

set oldLibName [DboTclHelper_sMakeCString "E:\PROJECT_WORKLIB.OLB"]
set newLibName [DboTclHelper_sMakeCString "E:\MCU_PARTS_LIB.OLB"]

#DboLib_ReplaceCache wrapper
proc ReplaceCacheByName {partName} {
    global oldLibName
    global newLibName
    global lDesign
    set lPartStr [DboTclHelper_sMakeCString $partName]
    #set lNewStr [DboTclHelper_sMakeCString $newName]
    $lDesign ReplaceCache $lPartStr $oldLibName $lPartStr $newLibName 0 1
}

then use the tcl command like below to do the real job :

ReplaceCacheByName "CL10B104KB8NNNC_C12"

This is the 15th installment of The Rationalist, my column for the Times of India.

It’s election season, and promises are raining down on voters like rose petals on naïve newlyweds. Earlier this week, the Congress party announced a minimum income guarantee for the poor. This Friday, the Modi government released a budget full of sops. As the days go by, the promises will get bolder, and you might feel important that so much attention is being given to you. Well, the joke is on you.

Every election, HL Mencken once said, is “an advance auction sale of stolen goods.” A bunch of competing mafias fight to rule over you for the next five years. You decide who wins, on the basis of who can bribe you better with your own money. This is an absurd situation, which I tried to express in a limerick I wrote for this page a couple of years ago:

POLITICS: A neta who loves currency notes/ Told me what his line of work denotes./ ‘It is kind of funny./ We steal people’s money/And use some of it to buy their votes.’

We’re the dupes here, and we pay far more to keep this circus going than this circus costs. It would be okay if the parties, once they came to power, provided good governance. But voters have given up on that, and now only want patronage and handouts. That leads to one of the biggest problems in Indian politics: We are stuck in an equilibrium where all good politics is bad economics, and vice versa.

For example, the minimum guarantee for the poor is good politics, because the optics are great. It’s basically Garibi Hatao: that slogan made Indira Gandhi a political juggernaut in the 1970s, at the same time that she unleashed a series of economic policies that kept millions of people in garibi for decades longer than they should have been.

This time, the Congress has released no details, and keeping it vague makes sense because I find it hard to see how it can make economic sense. Depending on how they define ‘poor’, how much income they offer and what the cost is, the plan will either be ineffective or unworkable.

The Modi government’s interim budget announced a handout for poor farmers that seemed rather pointless. Given our agricultural distress, offering a poor farmer 500 bucks a month seems almost like mockery.

Such condescending handouts solve nothing. The poor want jobs and opportunities. Those come with growth, which requires structural reforms. Structural reforms don’t sound sexy as election promises. Handouts do.

A classic example is farm loan waivers. We have reached a stage in our politics where every party has to promise them to assuage farmers, who are a strong vote bank everywhere. You can’t blame farmers for wanting them – they are a necessary anaesthetic. But no government has yet made a serious attempt at tackling the root causes of our agricultural crisis.

Why is it that Good Politics in India is always Bad Economics? Let me put forth some possible reasons. One, voters tend to think in zero-sum ways, as if the pie is fixed, and the only way to bring people out of poverty is to redistribute. The truth is that trade is a positive-sum game, and nations can only be lifted out of poverty when the whole pie grows. But this is unintuitive.

Two, Indian politics revolves around identity and patronage. The spoils of power are limited – that is indeed a zero-sum game – so you’re likely to vote for whoever can look after the interests of your in-group rather than care about the economy as a whole.

Three, voters tend to stay uninformed for good reasons, because of what Public Choice economists call Rational Ignorance. A single vote is unlikely to make a difference in an election, so why put in the effort to understand the nuances of economics and governance? Just ask, what is in it for me, and go with whatever seems to be the best answer.

Four, Politicians have a short-term horizon, geared towards winning the next election. A good policy that may take years to play out is unattractive. A policy that will win them votes in the short term is preferable.

Sadly, no Indian party has shown a willingness to aim for the long term. The Congress has produced new Gandhis, but not new ideas. And while the BJP did make some solid promises in 2014, they did not walk that talk, and have proved to be, as Arun Shourie once called them, UPA + Cow. Even the Congress is adopting the cow, in fact, so maybe the BJP will add Temple to that mix?

Benjamin Franklin once said, “Democracy is two wolves and a lamb voting on what to have for lunch.” This election season, my friends, the people of India are on the menu. You have been deveined and deboned, marinated with rhetoric, seasoned with narrative – now enter the oven and vote.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 23rd installment of The Rationalist, my column for the Times of India.

I had a strange dream last night. I dreamt that the government had passed a law that made using laptops illegal. I would have to write this column by hand. I would also have to leave my home in Mumbai to deliver it in person to my editor in Delhi. I woke up trembling and angry – and realised how Indian farmers feel every single day of their lives.

My column today is a tale of two satyagrahas. Both involve farmers, technology and the freedom of choice. One of them began this month – but first, let us go back to the turn of the millennium.

As the 1990s came to an end, cotton farmers across India were in distress. Pests known as bollworms were ravaging crops across the country. Farmers had to use increasing amounts of pesticide to keep them at bay. The costs of the pesticide and the amount of labour involved made it unviable – and often, the crops would fail anyway.

Then, technology came to the rescue. The farmers heard of Bt Cotton, a genetically modified type of cotton that kept these pests away, and was being used around the world. But they were illegal in India, even though no bad effects had ever been recorded. Well, who cares about ‘illegal’ when it is a matter of life and death?

Farmers in Gujarat got hold of Bt Cotton seeds from the black market and planted them. You’ll never guess what happened next. As 2002 began, all cotton crops in Gujarat failed – except the 10,000 hectares that had Bt Cotton. The government did not care about the failed crops. They cared about the ‘illegal’ ones. They ordered all the Bt Cotton crops to be destroyed.

It was time for a satyagraha – and not just in Gujarat. The late Sharad Joshi, leader of the Shetkari Sanghatana in Maharashtra, took around 10,000 farmers to Gujarat to stand with their fellows there. They sat in the fields of Bt Cotton and basically said, ‘Over our dead bodies.’ ¬Joshi’s point was simple: all other citizens of India have access to the latest technology from all over. They are all empowered with choice. Why should farmers be held back?

The satyagraha was successful. The ban on Bt Cotton was lifted.

There are three things I would like to point out here. One, the lifting of the ban transformed cotton farming in India. Over 90% of Indian farmers now use Bt Cotton. India has become the world’s largest producer of cotton, moving ahead of China. According to agriculture expert Ashok Gulati, India has gained US$ 67 billion in the years since from higher exports and import savings because of Bt Cotton. Most importantly, cotton farmers’ incomes have doubled.

Two, GMO crops have become standard across the world. Around 190 million hectares of GMO crops have been planted worldwide, and GMO foods are accepted in 67 countries. The humanitarian benefits have been massive: Golden Rice, a variety of rice packed with minerals and vitamins, has prevented blindness in countless new-born kids since it was introduced in the Philippines.

Three, despite the fear-mongering of some NGOs, whose existence depends on alarmism, the science behind GMO is settled. No harmful side effects have been noted in all these years, and millions of lives impacted positively. A couple of years ago, over 100 Nobel Laureates signed a petition asserting that GMO foods were safe, and blasting anti-science NGOs that stood in the way of progress. There is scientific consensus on this.

The science may be settled, but the politics is not. The government still bans some types of GMO seeds, such as Bt Brinjal, which was developed by an Indian company called Mahyco, and used successfully in Bangladesh. More crucially, a variety called HT Bt Cotton, which fights weeds, is also banned. Weeding takes up to 15% of a farmer’s time, and often makes farming unviable. Farmers across the world use this variant – 60% of global cotton crops are HT Bt. Indian farmers are so desperate for it that they choose to break the law and buy expensive seeds from the black market – but the government is cracking down. A farmer in Haryana had his crop destroyed by the government in May.

On June 10 this year, a farmer named Lalit Bahale in the Akola District of Maharashtra kicked off a satyagraha by planting banned seeds of HT Bt Cotton and Bt Brinjal. He was soon joined by thousands of farmers. Far from our urban eyes, a heroic fight has begun. Our farmers, already victimised and oppressed by a predatory government in countless ways, are fighting for their right to take charge of their lives.

As this brave struggle unfolds, I am left with a troubling question: All those satyagrahas of the past by our great freedom fighters, what were they for, if all they got us was independence and not freedom?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Read on to know about the Operating Point Parameters Summary window that gives you a one-stop view of the categorized and tabulated details on all operating point parameters in your design. This window improves your review cycle with its many benefits.(read more)

During a mixed-signal simulation, the analog engine usually dominates the simulation time and resources. If you need to run only the analog engine in several windows, or if you would like to to run multiple tests of the same circuit with different stimuli or test pattern, then you need to run the simulation multiple times. View this blog to know more about the the two advanced technologies that Spectre AMS Designer provides to help you improve the efficiency of your mixed-signal designs and to increase the simulation speed.(read more)

Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera. (read more)

At a bustling Cadence event, we met Adrian, an intern at a startup who immerses himself in Cadence tools for his research and work.

Adrian was enthusiastic about the innovative technologies at his disposal but faced a significant challenge: internet access was limited to a single machine for new joiners, forcing interns to wait in line for their turn to use online resources.

Adrian's excitement soared when he discovered a game-changing solution: Doc Assistant. The cloud-based help viewer, Doc Assistant, ships with all Cadence tools, enabling Adrian to access help resources offline from any machine equipped with the software. This meant Adrian could continue his research and work seamlessly, irrespective of internet availability!

Meeting Cadence users and customers at such events has given us the opportunity to showcase how they can benefit from the diverse features that Doc Assistant offers.

With that note, welcome back to our Doc Assistant A-Z blog series! In Part 1, we explored key features and benefits that our innovative viewer brings to the table. Today, in Part 2, we'll dive deeper into the advanced functionalities and customization options that make Doc Assistant indispensable for its users.

Whether you're looking to streamline your workflow or enhance your user experience, this blog will provide the insights you need to fully leverage the capabilities of our documentation viewer. Let’s get started!

What Makes Doc Assistant Stand Out?

Here are a few (more) cool features of Doc Assistant!

That's not all. We have more coming your way. Until next time, take care and stay tuned for our next edition!

Want to Know More?

For any questions or general feedback, write to docassistant.support@cadence.com.

Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Happy reading!

-Priya Sriram, on behalf of the Doc Assistant Team

Have you ever wanted to write a DRC rule deck to check for space or width constraints on polygons? Or have you wondered how the multiple lines of an LVS rule deck extract and conduct a comparison between the schematic and layout? Maybe you've been curious about the role of rule deck writers in creating high-quality designs ready for tape-out.

If any of these questions interest you, there is good news: the latest version (v23.1) of the Physical Verification Rules Writer (PVLRW) course is designed to teach you rule deck writing. This free 16-hour online course includes audio and labs designed to make your learning experience comfortable and flexible. Whether you are new to the concept or an experienced CAD/PDK engineer, the course is structured to enhance your rule deck writing skills.

The PVLRW course covers six core modules: Layer Processing, DRC Rules, Layout Extraction, ERC and LVS Rules, Schematic Netlisting, and Coloring Rules. There are also three optional appendix sections. Each module explains relevant rules with syntax, concepts, graphics, examples, and case studies.

This course is based on tool versions PEGASUS231 and Virtuoso Studio IC231.

Pegasus Input and Output

Pegasus is a cloud-ready physical verification signoff solution that enables engineers to support faster delivery of advanced-node integrated circuits (ICs) to market.

Pegasus requires input data in the form of layout geometry, schematic netlists, and rules that direct the tool operation. The rules fall into two categories: those that describe the fabrication process and those that control the job-specific operation.

Pegasus provides log and report files, netlists, databases, and error databases as output.

Overview of Pegasus Rule File

The rule decks written in Physical Verification Language (PVL) work for the Cadence PV signoff tools Pegasus and PVS (Physical Verification System).   

The PVL rules are placed in a file that gets selected in a run from the GUI or the command line, as the user directs. PVL rules may be on separate lines within the file and can also be contained in named rule blocks.

Each line of code starts with a PVL rule that uses prefix type notation. It consists of a keyword followed by options, input layer or variable names, and output layer or variable names.

A rule block has the format of the keyword rule, followed by a rule name you wish to give it, followed by an opening curly brace. You enter the rules you wish to perform, followed by a closing curly brace on the last separate line.

  Sample Rule deck with individual lines of code and rule blocks.

DRC Rules

The first step in a typical Pegasus flow is a Design Rule Check (DRC), which verifies that layout geometries conform to the minimum width, spacing, and other fabrication process rules required by an IC foundry. Each foundry specifies its own process-dependent rules that must be met by the layout design.

There are three types of DRC rules: layer definition rules, layer derivation rules, and DRC design check rules. Layer definition rules identify the layers contained in the input layout database, and layer derivation rules derive additional layers from the original input layers, allowing the tool to test the design against specific foundry requirements using the design check rules.

A sample DRC Rule deck

A layout view displaying the DRC violations

LVS Rules

The Pegasus Layout Versus Schematic (LVS) tool compares the layout netlist with the schematic netlist to check for discrepancies.

There are two essential LVS rule sets: LVS extraction rules and comparison rules. LVS extraction rules help extract drawn devices and connectivity information from the input layout geometry data and outputs into a layout netlist. The LVS extraction rule set also includes the layer definition, derivation, extraction, connectivity, and net listing rules.

LVS comparison rules are associated with comparing the extracted layout netlist to a schematic netlist.

A sample LVS Rule deck. 

TCL, Macros, and Conditional commands

Tcl is supported and used in various Pegasus functionalities, such as Pegasus rule files and Pegasus configurator. Macros are functional templates that are defined once and can be used multiple times in a rule file. Conditional Commands are used to process or skip specific commands in the rule file.

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• On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
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• If you need help with registration, contact support@cadence.com.

To stay up to date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails.

If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training.

For any questions, general feedback, or future blog topic suggestions, please leave a comment.

Related Resources

About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis. Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Welcome back to the Doc Assistant A-Z blog series!

Since the launch of Doc Assistant, we've been gathering feedback and input from our customers regarding their experiences with our latest documentation viewer. My interaction with Ralf was particularly useful and interesting.

Ralf is a design engineer who works on complex schematics and intricate layouts. For each release, he is challenged with the task of verifying the tool and feature changes across multiple releases. He shared with me that he has been using Doc Assistant’s capabilities to help him achieve this.

Ralf explained that he utilizes Doc Assistant to open and compare documents from different releases side-by-side, seamlessly tracking updates across multiple releases and verifying those updates in his Cadence tools. Additionally, in Doc Assistant’s online mode, he compares documents across previous tool versions, ensuring a thorough review of any changes. Finally, he was happy to share with me that Doc Assistant features have helped him significantly reduce the time he spends on identifying such changes.

You, of course, can also achieve such productivity gains using several Doc Assistant features designed to help simplify such tasks!

In previous editions of this blog series, we looked at some key features and benefits of Doc Assistant. If you've missed these editions, I would highly recommend that you read them:

• Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 1
• Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 2
  

In this third installment, we're diving into some more of Doc Assistant's key capabilities.

To learn more about how to use the above features, check out the Doc Assistant User Guide.

These are just a few of the productivity gain features in Doc Assistant. We’ll cover more in the next blog in the series.

Want to Know More?

If you have any feedback on Doc Assistant or would like to request more information or a demo, please contact docassistant.support@cadence.com.

Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Happy reading!

- Priya Sriram, on behalf of the Doc Assistant Team

Hi 

I am looking into chamfering the edge of PCB for Board edge connectors. I have performed fillet command earlier but new to chamfering.

Below is the description :

As seen above, the PCB edge are chamfered in thickness as well as at the corners.

Using OrCAD PCB hotfix S023.

Hi,

So I was trying to update the title block of a schematic that I have. The title block that was on there was out of date . I clicked on place --> title block and was able to find the title block that I need. I also have a .OLB file that contains that title block. Then I created a Netlist with the old BRD file as the input file (To keep it as is but modify changes) but when I do that I still do not see / cannot place the title block that I need. Under Place --> format symbols in Allegro , I do see a title block that is coming from the database (But it's the old one). I don't know what to do at this point and would appreciate any tips. I did make sure that the path to where the library is , is defined in the user preferences. 
I also tried copying the title block under the library folder in capture before creating my Netlist and that did not work either.

Thank you all.

How do we purge/remove the duplicated vias in the same location of the PCB editor? These vias are not the one stacked and they are just blind vias running in internal layers 12-14. I find there is an additional copy of the blind via at the same location. Not sure what caused this issue.

I'd like to be able to edit a footprint for a part in my design without needing to find the footprint filepath and directly open that file in PCB Editor. I see that I can view footprints from Capture, and that doing so shows me the footprint path, but I can't find any way to launch the editor. Is there any way to go directly from a part in a Capture schematic or a placed part in a PCB Editor board design to editing that part's footprint?

Hello..

I'm updating part in part editor in orcad capture, and I wonder how to align pin numbers using menu or tcl/tk command.

Please, let me know. Thank you.

Hello. I am using Cadence 17.4 tools. When I open a package symbol (.dra) or board file (.brd) in Allegro that was created in an older version of the tool I get a message like this one (as expected):

"The design created using release 17.2 will be updated for compatibility with the current software..."

If I create a symbol or board file from scratch in the 17.4 tool then open it later, I get the same message. (always referring to version 17.2 which is the previous version I was using here).

So far this has not caused me any problems, but I would like to understand why it is doing this in case I have something setup incorrectly.

I only have version 17.4 installed. I am not exporting to a downrev version when I save (i.e. not using File->Export->Downrev design…) and in User Preferences->Drawing I don’t have anything selected for database_compatibility_mode. What else might I check?

FYI here is the tool version information that I see after selecting Help->About Symbol:

OrCAD PCB Designer Standard 17.4-2019 S012 [10/26/2020] Windows SPB 64-bit Edition

Thanks -Jason

I have a design which says there are 6 unconnected nets. But 'Display All Nets, shows only 4 unconnected. When I try to look at the non-connection, is appears connected and nothing shows??

What is happening?

Hi,

I found that under the Dark Theme of PCB Environment Editor 17.4,

the window background is not all dark, resulting in unclear text display。

As shown in the figure below：

Hi

In the environment I'm currently working, axes are shown for schematic, symbol, and layout views.For schematics and symbols, I'd prefer a dim gray, such that the axes are just visible but not dominant. For the layout, I'd prefer a brighter color. Is there a way to realize this? So far when I change the color of the 'axis' layer in the display resource editor, the axes in all three views get changed together:

Thanks very much for your input!

Hi,

I have a LEF file with simple definitions of pad design which uses M8, M9, and AP layers. However, I failed to import the design with CIW > Import > LEF... as I encountered "ERROR: (OALEFDEF-90019): Ignoring the line 30 in the layer map file ... as it contains a syntax error. Each entry in the layer map file must have two values, LEFLayerName and OALayerNumber separated by a blank space." All lines in the file report the same OALEFDEF-90019 error.

The tech.layermap file looks like this:


# techLayer       techPurpose     stream# dataType

ref drawing 0 0
DNW drawing 1 0
PW drawing 2 0

How can I place stacked vias with the size exact same cut width without metals around?
As the red part only in the image below?

Hello,

I have been running this `uvm_reg_hw_reset_seq` sequence for the AHB protocol. My UVM Adapter looks like:

Issue: When I use basic reg.write, my write access are working well, as that is managed by the driver i.e. once adapter gives the packet to the driver, the driver supplies the address and the control signals to the DUT on the first clock cycle and then the write data on the next clock cycle. But when I am performing the read operation, somehow the UVM adapter is reading the data at the same clock cycle where read address + Controls are supplied and this is triggering read failure messages from the `uvm_reg_hw_reset_seq` sequence. What should I modify in the driver/sequencer/adapter so that the UVM adapter can read the data on the next cycle instead of the same clock cycle.

Just FYI: The waveforms of the read operation are correct, it is just the Adapter and the `uvm_reg_hw_reset_seq`. The AHB Driver + AHB Monitor is fully proven and verified to be working correctly.

I would like to send an update about a vmanager regression status x days after the regression has been run. In the current environment, the vmanager regression is creating a new filepath for logs automatically based on regression name/date, so I can't use a cron job to gather logs, as the log location is not known. 

I tried to use the pre session script to launch a detached shell script that would run after a delay, but when the pre_script runs, it waits until everything is completed before finishing and moving on to starting the regression.

Here is the test pre_script I am using:

#!/bin/sh

echo "pre_script start"

delay_script "FIRST" 1
nohup delay_script "SECOND" 30 & disown
delay_script "THIRD" 1

echo "pre_script end"
exit 0

Here is the test delay_script I am using:

#!/bin/sh

echo "Starting $1"

sleep $2

echo "Ending $1"

Here is the script output when run from terminal. After the "pre_script end", I get control back.

Here is the script output when run from vmanager. There is no "nohup", and the pre_session phase doesn't complete until all the delay scripts complete.

My question is, is there a better way to achieve my goal here? (The goal being to run a script from the vmanager log directory automatically x days after the regression). I think I could use the pre_script to send directory information for an auxiliary cron job to pick up, but I would prefer to not have to have extra cronjobs needed for this.

When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:

# A fatal error has been detected by the Java Runtime Environment:
#
#  SIGSEGV (0xb) at pc=0x00007efc52861b74, pid=14182, tid=18380
#
# JRE version: OpenJDK Runtime Environment Temurin-17.0.3+7 (17.0.3+7) (build 17.0.3+7)
# Java VM: OpenJDK 64-Bit Server VM Temurin-17.0.3+7 (17.0.3+7, mixed mode, sharing, tiered, compressed oops, compressed class ptrs, g1 gc, linux-amd64)
# Problematic frame:
# C  [libucis.so+0x238b74]

......

For more details please refer to the attached log file "hs_err_pid21143.log".

Two approaches were tried to solve this problem but neither has worked.
Method.1:

Setting larger heap size of Java process by "-memlimit" options.For example "vmanager -memlimit 8G".

Method.2:

Enlarging stack memory size limit of the Coverage engine by setting "IMC_NATIVE_STACKSIZE" environment variable to a larger value. For example "setenv IMC_NATIVE_STACKSIZE 1024000"

According to "hs_err_pid*.log" it is almost certain that the memory overflow triggered Java's CrashOnOutOfMemoryError and caused Verisium Manager to crash. There are some arguments about memory management of Java like "Xms, Xmx, ThreadStackSize, Xss5048k etc" and maybe this problem can be fixed by setting these arguments during analysis. However, how exactly does Verisium Manager specify these arguments during analysis? I tried to set them by the form of setting environment variables before analysis but it didn't work in analysis and their values didn't change.

Is there something wrong with my operation or is there a better solution?

Thank you very much.

I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code covered grade, block covered grade, statement covered grade, expression covered grade, toggle covered grade.

As I dont know the difference I started to read the IMC user guide and came to know there are 3 things we come across while doing a code coverage local, covered, average

From my understanding

local - child instances metrics doesnt reach the parent level. For example, we have an instance Q and its sub instances like Q.a, Q.b. Block Local grade of Q can be 100% even when its instances Q.a and Q.b a block local grades isnt at 100%.

In the attached image there is formula 

The key difference between average and covered is the weights.

Average : Mathematically taking the above scenario where Q.a, and Q.b has 10 blocks each. Q.a has covered 8 blocks and q.b has covered 2 blocks. Now if we take the normal average it should be total covered/ totatl number = 8+2/10+10 yielding 50%. But when we add weights saying Q.a is 70% and Q.b is 30% the new number would be (8*0.7+2*0.3) / (10*0.7+10*0.3) resulting 62%. Because of the weights we see 12% bump.

Covered: there is no role of weights.

Among these 3 metrics i've changed my default view to this in the image to get more realistic picture when i do analyze metrics. Do you guys agree with the approach?

I'm currently work in coverage analysis. In my design certain register bits remain unused, which could potentially lower toggle coverage. Specifically, I'd like to know how to disable coverage for specific unused register bits within a 32-bit register. For instance, I want to deactivate coverage for bit 17 and bit 20 in a 32-bit register to optimize toggle coverage. Could you please provide guidance on how to accomplish this?

Hello,

I have a question about toggle coverage.

In my case, there are many unused registers or wires that are affecting the toggle coverage score negatively.

Is it possible to automatically exclude registers or wires that are not used from toggle coverage?

My RTL code is as follows, Is it possible to automatically disable tb.top1.b and tb.top1.c without using an exclude file?

module top1;

  reg a;

  reg b;

  reg [31:0] c;

  initial

  begin

  #1 a=1'b0;

  #1 a=1'b1;

  #1 a=1'b0;

  end

endmodule

module tb;

  top1 top1();

endmodule

We are trying to run compilation, elab and sim with command xrun -r -u alu, where alu is one of the units to execute. we are getting the following errors.

1) xmsim: *E,DLMKDF: Unable to add default DEFINE std       /home/xxxx/Cad/xcelium/tools/inca/files/STD.
    xmsim: *E,DLMKDF: Unable to add default DEFINE synopsys  /home/xxxx/Cad/xcelium/tools/inca/files/SYNOPSYS

2) xmsim: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.

What is the purpose of hdl.var

3) xmsim: *F,NOSNAP: Snapshot 'alu' does not exist in the libraries.

I cannot see in log files, which libraries is it referring to??

Any one request you to help on how to debug these.

Hello All,

starting with version 8.1 the contents of the ce_tools directory will no longer
be shipped with Specman. The directory contains some unsupported AE/R&D
ware and has not been updated for several releases (i.e. most of those old
packages don't work with the latest release).
 
Attached is the contents of this directory. Please read the README before
using any of the packages.


Regards,
-hannes

Hello All,

Following is the einstein's puzzle solved by cadence Incisive92  (solved in less than 3 seconds -> FAST!!!!!!)

Thanks,

Vinay Honnavara

Verification engineer at Keyu Tech

vinayh@keyutech.com

 // Author: Vinay Honnavara

// Einstein formulated this problem : he said that only 2% in the world can solve this problem
// There are 5 different parameters each with 5 different attributes
// The following is the problem

// -> In a street there are five houses, painted five different colors (RED, GREEN, BLUE, YELLOW, WHITE)

// -> In each house lives a person of different nationality (GERMAN, NORWEGIAN, SWEDEN, DANISH, BRITAIN)

// -> These five homeowners each drink a different kind of beverage (TEA, WATER, MILK, COFFEE, BEER),

// -> smoke different brand of cigar (DUNHILL, PRINCE, BLUE MASTER, BLENDS, PALL MALL)

// -> and keep a different pet (BIRD, CATS, DOGS, FISH, HORSES)


///////////////////////////////////////////////////////////////////////////////////////
// *************** Einstein's riddle is: Who owns the fish? ***************************
///////////////////////////////////////////////////////////////////////////////////////

/*
Necessary clues:

1. The British man lives in a red house.
2. The Swedish man keeps dogs as pets.
3. The Danish man drinks tea.
4. The Green house is next to, and on the left of the White house.
5. The owner of the Green house drinks coffee.
6. The person who smokes Pall Mall rears birds.
7. The owner of the Yellow house smokes Dunhill.
8. The man living in the center house drinks milk.
9. The Norwegian lives in the first house.
10. The man who smokes Blends lives next to the one who keeps cats.
11. The man who keeps horses lives next to the man who smokes Dunhill.
12. The man who smokes Blue Master drinks beer.
13. The German smokes Prince.
14. The Norwegian lives next to the blue house.
15. The Blends smoker lives next to the one who drinks water.
*/




typedef enum bit [2:0]  {red, green, blue, yellow, white} house_color_type;
typedef enum bit [2:0]  {german, norwegian, brit, dane, swede} nationality_type;
typedef enum bit [2:0]  {coffee, milk, water, beer, tea} beverage_type;
typedef enum bit [2:0]  {dunhill, prince, blue_master, blends, pall_mall} cigar_type;
typedef enum bit [2:0]  {birds, cats, fish, dogs, horses} pet_type;




class Einstein_problem;

    rand house_color_type house_color[5];
    rand nationality_type nationality[5];
    rand beverage_type beverage[5];
    rand cigar_type cigar[5];
    rand pet_type pet[5];
        rand int arr[5];
    
    constraint einstein_riddle_solver {
    
        
    
        foreach (house_color[i])
            foreach (house_color[j])
               if (i != j)
                house_color[i] != house_color[j];
        foreach (nationality[i])
            foreach (nationality[j])
               if (i != j)
                nationality[i] != nationality[j];
        foreach (beverage[i])
            foreach (beverage[j])
               if (i != j)
                beverage[i] != beverage[j];
        foreach (cigar[i])
            foreach (cigar[j])
               if (i != j)
                cigar[i] != cigar[j];
        foreach (pet[i])
            foreach (pet[j])
               if (i != j)
                pet[i] != pet[j];
    
    
        //1) The British man lives in a red house.
        foreach(nationality[i])
                (nationality[i] == brit) -> (house_color[i] == red);
                
        
        //2) The Swedish man keeps dogs as pets.
        foreach(nationality[i])
                (nationality[i] == swede) -> (pet[i] == dogs);
                
                
        //3) The Danish man drinks tea.        
        foreach(nationality[i])
                (nationality[i] == dane) -> (beverage[i] == tea);
        
        
        //4) The Green house is next to, and on the left of the White house.
        foreach(house_color[i])        
                 if (i<4)
                    (house_color[i] == green) -> (house_color[i+1] == white);
        
        
        //5) The owner of the Green house drinks coffee.
        foreach(house_color[i])
                (house_color[i] == green) -> (beverage[i] == coffee);
                
        
        //6) The person who smokes Pall Mall rears birds.
        foreach(cigar[i])
                (cigar[i] == pall_mall) -> (pet[i] == birds);
        
        
        //7) The owner of the Yellow house smokes Dunhill.
        foreach(house_color[i])
                (house_color[i] == yellow) -> (cigar[i] == dunhill);
        
        
        //8) The man living in the center house drinks milk.
        foreach(house_color[i])
                if (i==2) // i==2 implies the center house (0,1,2,3,4) 2 is the center
                    beverage[i] == milk;
        
        
        
        //9) The Norwegian lives in the first house.
        foreach(nationality[i])        
                if (i==0) // i==0 is the first house
                    nationality[i] == norwegian;
        
        
        
        //10) The man who smokes Blends lives next to the one who keeps cats.
        foreach(cigar[i])        
                if (i==0) // if the man who smokes blends lives in the first house then the person with cats will be in the second
                    (cigar[i] == blends) -> (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i>0 && i<4) // if the man is not at the ends he can be on either side
                    (cigar[i] == blends) -> (pet[i-1] == cats) || (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i==4) // if the man is at the last
                    (cigar[i] == blends) -> (pet[i-1] == cats);
        
        foreach(cigar[i])        
                if (i==4)
                    (pet[i] == cats) -> (cigar[i-1] == blends);
        
        
        //11) The man who keeps horses lives next to the man who smokes Dunhill.
        foreach(pet[i])
                if (i==0) // similar to the last case
                    (pet[i] == horses) -> (cigar[i+1] == dunhill);
        
        foreach(pet[i])        
                if (i>0 & i<4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill) || (cigar[i+1] == dunhill);
                    
        foreach(pet[i])        
                if (i==4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill);
                    


        //12) The man who smokes Blue Master drinks beer.
        foreach(cigar[i])
                (cigar[i] == blue_master) -> (beverage[i] == beer);
        
        
        //13) The German smokes Prince.
        foreach(nationality[i])        
                (nationality[i] == german) -> (cigar[i] == prince);
        

        //14) The Norwegian lives next to the blue house.
        foreach(nationality[i])
                if (i==0)
                    (nationality[i] == norwegian) -> (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i>0 & i<4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue) || (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i==4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue);
        

        //15) The Blends smoker lives next to the one who drinks water.            
        foreach(cigar[i])            
                if (i==0)
                    (cigar[i] == blends) -> (beverage[i+1] == water);
        
        foreach(cigar[i])        
                if (i>0 & i<4)
                    (cigar[i] == blends) -> (beverage[i-1] == water) || (beverage[i+1] == water);
                    
        foreach(cigar[i])        
                if (i==4)
                    (cigar[i] == blends) -> (beverage[i-1] == water);
        
    } // end of the constraint block
    


    // display all the attributes
    task display ;
        foreach (house_color[i])
            begin
                $display("HOUSE : %s",house_color[i].name());
            end
        foreach (nationality[i])
            begin
                $display("NATIONALITY : %s",nationality[i].name());
            end
        foreach (beverage[i])
            begin
                $display("BEVERAGE : %s",beverage[i].name());
            end
        foreach (cigar[i])
            begin
                $display("CIGAR: %s",cigar[i].name());
            end
        foreach (pet[i])
            begin
                $display("PET : %s",pet[i].name());
            end
        foreach (pet[i])
            if (pet[i] == fish)
                $display("THE ANSWER TO THE RIDDLE : The %s has %s ", nationality[i].name(), pet[i].name());
    
    endtask // end display
    
    
endclass




program main ;

    initial
        begin
            Einstein_problem ep;
            ep = new();
            if(!ep.randomize())
                $display("ERROR");
            ep.display();
        end
endprogram // end of main

        

Hi all, I've trained a device model with the approach of an artificial neural network, and it shows well fit. 

May I know how to transfer the trained model to Verilog-A, so that, we can use this model to do circuit simulation?

And I've searched for some lectures that provide the Verilog-A code in the appendix, but I'm freshman in the field of Verilog-A, 

could anyone tell me each statement? such as

real hlayer-w[0:(NI*NNHL)-1   

Using the EMX solver, X-FAB design engineers can efficiently develop next-generation RF technology for the latest communication standards (including sub-6GHz 5G, mmWave, UWB, etc.), which are enabling technologies for communications and electric vehicle (EV) wireless applications. (read more)

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Cadence Clarity 3D Solver supports encrypted component models! Using this functionality, vendors can supply their 3D components, such as connectors, to end customers without revealing the physical IP of these designs. The first connector vendor to take advantage of this functionality is Japan Aviation Electronics (JAE),(read more)

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Do you know if it is possible to define localized back etching (LBE) in EMX? It should be associated to a layer which defines the holes done in the substrate. I've not found any reference for this in the .proc syntax. 

--> Answer found. This is not possible because EMX considers the same dielectric in all x-y plane

Hi, I would be grateful if you can help me with this error which I get after trying to run an EMX simulation on a PCELL.

I've found very limited information in this forum. Thanks

I get multiple results at the same frequency in a 3-tone simulation.

I try to determine the IP3 of a mixer. I have 3 large signal tones: 0.75 GHz, 1.25 GHz and 1.26 GHz.

At the IM3 frequency of 490 MHz I observe 4 results, see also the screenshot of the table output. The frequencies are exactly the same (even when I subtract 490 MHz by using xval() ).

Which of the values do I have to use to determine the correct IP3?

Is there an option to merge these results?

Hello everyone,

For my cross-coupled oscillator design, I have a problem with stability analysis. Based on my achieved results which are attached, where is my design problem?

Best,

https://ibb.co/bgKFP4N

https://ibb.co/3FGRLmV

https://ibb.co/pwSZDSF

Che(read more)

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL.(read more)

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about the new enhancements in ICADVM20.1 ISR25 for Virtuoso RF Solution. At the end of the blog, I told you about the Fully Assisted Roundtrip flow, which includes importing SiP files that are compatible with the Virtuoso RF Solution assisted import flow into the Virtuoso platform. Let's examine how the Fully Assisted Roundtrip flow works in this blog.(read more)

This blog helps in demonstrating the use of Pin to trunk routing style which helps in enhancing the layout experience.(read more)

Hi

the signal SPI_SCLK belongs to TWO Spacing CLASSES: CLS_SP_SPI and CLS_SP_SPI_CLOCK

I then assign TWO different SPACING RULES to each class : CLS_SP_SPI  > 2H and CLS_SP_SPI_CLOCK > 3.5H

Which SPACING RULE will inherit the signal SPI_SCLK ??

Is it possible to manually define the PRIORITY on Design Rules ??