1 Cayman Islands Dollar = 5.0444 Polish Zloty

1 Swiss Franc = 4.3304 Polish Zloty

Lawrence, KS – The Haskell Softball team hosted Graceland University for a double-header on Monday afternoon.

1 CFA Franc BCEAO = 0.007 Polish Zloty

1 Vietnamese Dong = 0.0002 Polish Zloty

1 Macedonian Denar = 0.074 Polish Zloty

1 Zambian Kwacha = 0.0008 Polish Zloty

1 South Korean Won = 0.0034 Polish Zloty

1 Jordanian Dinar = 5.9263 Polish Zloty

1 Lebanese Pound = 0.0028 Polish Zloty

1 Bahraini Dinar = 11.1184 Polish Zloty

1 Chilean Peso = 0.0051 Polish Zloty

Haskell loses in head to head battle in fourth set on September 24, 2019. 

Haskell falls short to advance in pool play and secure automatic bid to represent A.I.I. Conference in nationals. 

1 Maldivian Rufiyaa = 0.2712 Polish Zloty

1 Malaysian Ringgit = 0.9702 Polish Zloty

1 Nicaraguan Cordoba Oro = 0.1222 Polish Zloty

Players are working out creatively, but can't replace the intensity of team training.

1 Netherlands Antillean Guilder = 2.3422 Polish Zloty

1 Estonian Kroon = 0.2948 Polish Zloty

1 Danish Krone = 0.6111 Polish Zloty

1 Fiji Dollar = 1.8663 Polish Zloty

1 New Zealand Dollar = 2.5809 Polish Zloty

1 Croatian Kuna = 0.606 Polish Zloty

1 Peruvian Nuevo Sol = 1.237 Polish Zloty

Lawrence, Kansas – The Haskell men's golf team finished 9th out of 11 teams in the Baker Tournament held at Eagle Bend Golf Course in Lawrence, Kansas on Monday and Tuesday. The Indians finished with a round scores of 330, 332, and 325 with a total team score 987.

LAWRENCEVILLE, Ga. – The Association of Independent Institutions (A.I.I.) announced on Monday that Grant Shorty (SO/Albuquerque, NM) of Haskell Indian Nations University (Kan.) has been named the A.I.I.'s Men's Golfer of the Week for the duration of April 10-16.

1 Dominican Peso = 0.0764 Polish Zloty

1 Papua New Guinean Kina = 1.2257 Polish Zloty

1 Brunei Dollar = 2.9752 Polish Zloty

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor.  

So, how do you measure IP quality and why it is so complicated?

The answer depends on who is asking. Most of the time, the definition of IP quality depends on your vantage point.  If you are an R&D manager, IP quality means something. If you are a global supply manager, IP quality means something else. If you are an SoC start-up, your measure of quality is quite different from that of an established fabless company. If you are designing IP in-house, then your considerations are very different than being a commercial IP vendor. If you are designing an automotive SoC, then we are in a totally different category. How about as an IP vendor? How do you articulate IP quality metrics to your customers?

This varies greatly by the type of IP, as well. When it comes to interface (hard) IP and controllers, if you are an R&D manager, your goal is to design IP that meets the IP specifications and PPA (power, performance, and area) targets. You need to validate your design via silicon test chips. This applies to all hard PHYs, which must be mapped to a particular foundry process. For controllers that are in RTL form—we called these soft IP—you have to synthesize them into a particular target library in a particular foundry process in order to realize them in a physical form suitable for SoC integration. Of course, your design will need to go through a series of design validation steps via simulation, design verification and passing the necessary DRC checks, etc. In addition, you want to see the test silicon in various process corners to ensure the IP is robust and will perform well under normal process variations in the production wafers.

For someone in IP procurement, the measure of quality will be based on the maturity of the IP. This involves the number of designs that have been taped out using this IP and the history of bug reports and subsequent fixes. You will be looking for quality of the documentation and the technical deliverables. You will also benchmark the supplier’s standard operating procedures for bug reporting and technical support, as well as meeting delivery performance in prior programs. This is in addition to the technical teams doing their technical diligence.

An in-house team that is likely to design IP for a particular SoC project will be using an established design flow and will have legacy knowledge of last generation’s IP. They may be required to design the IP with some reusability in mind for future programs. However, such reusability requirements will not need to be as stringent and as broad as those of commercial IP vendors because there are likely to be established metrics and procedures in place to follow as part of the design team’s standard operating procedures. Many times, new development based on a prior design that has been proven in use will be started, given this stable starting point. All of these criteria help the team achieve a quality outcome more easily.

Then, if designing for an automotive SoC, additional heavy lifting is required.  Aside from ensuring that the IP meets the specifications of the protocol standards and passes the compliance testing, you also must pay attention to meeting functional safety requirements. This means adherence to ISO 26262 requirements and subsequently achieving ASIL certification. Oftentimes, even for IP, you must perform some AEC-Q100-related tests that are relevant to IP, such as ESD, LU, and HTOL.

To read more, please visit: https://semiengineering.com/why-ip-quality-is-so-difficult-to-determine/

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD.  With the increasing companies are working on PCIe 4.0 related product development, Cadence, as the key and leading PCIe IP solution vendor in the market, has strived for continuous enhancement of its PCIe 4.0 to be the best in the class IP solution. From our initial PCIe 4.0 solution in 4 years ago (revealed in 2015), we have made many advancements and improvements adding features such as Multi-link with any lane assignment, U.2/U.3 connector, and Automotive support. The variety of applications that PCIe4 finds a home in require extensive robustness and reliability testing over and above the compliance tests mandated by the standard body, i.e., PCI-SIG.

PCIe 4.0 TX Eye-Diagram, Loop-back Test (Long-reach) and RX JTOL Margin Test

Cadence IP team has also implemented additional "stress tests" in conjunction to its already comprehensive IP characterization plan, covering electrical, functional, ESD, Latch-up, HTOL, and yield sorting. Take the Receiver Jitter Tolerance Test (JTOL) for instance. JTOL is a key index to test the quality of the receiver of a system. This test use data generator/analyzer to send data to a SerDes receiver which is then looped back through the transmitter back to the instrument. The data received is compared to the data generated and the errors are counted. The data generator introduce jitter into the transmit data pattern to see how well the receiver functions under non-ideal conditions. While PCI-SIG compliance can be obtained on a single lane implementation, real world scenarios require wider implementations under atypical operating conditions. Cadence’s PCIe 4.0 IP was tested against to additional stressed conditions, such as different combination of multi-lanes operations, “temperature drift” conditions, e.g., bring up the chip at room temperature and check the JTOL at high temperature. 

PCIe 4.0 Sub-system Stress Test Setup

Besides complying with electrical parameters and protocol requirements, real world systems have idiosyncrasies of their own. Cadence IP team also built a versatile “System test” setup in house to perform a system level stress test of its PCIe 4.0 sub-system. The Cadence PCIe 4.0 sub-system is connected to a large number of server and desktop motherboards. This set up is tested with 1000s of cycles of repeated stress under varying operating conditions. Stress tests include speed change from 2.5G all the way to 16G and down, link enable/disable, cold boot, warm boot, entering and exiting low power states, and BER test sweeping presets across different channels. Performing this level of stress test verifies that our IP will operate to spec robustly and reliably when presented with the occasional corner cases in the real world.

More Information

For the demonstration of Cadence PCIe4 PHY Receiver Test and Sub-system Stress Test, see the video:

• PCIe 4.0 Sub-system Stress Test
• PCIe 4.0 PHY Receiver JTOL Test

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

X is a song written by Y and famously covered by Z. Time Magazine’s Josh Tyrangiel described it thus:

Y murmured the original like a dirge, but except for a single overwrought breath before the music kicks in, Z treated the 7-min. song like a tiny capsule of humanity, using his voice to careen between glory and sadness, beauty and pain, mostly just by repeating the word X. It’s not only Z’s best song — it’s one of the great songs, and because it covers so much emotional ground and is not (yet) a painfully obvious choice, it has become the go-to track whenever a TV show wants to create instant mood. ‘X can be joyous or bittersweet, depending on what part of it you use,’ says Sony ATV’s Kathy Coleman. ‘It’s one of those rare songs that the more it gets used, the more people want to use it.’

Name X, Y and Z.

Workoutable © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 16th installment of The Rationalist, my column for the Times of India.

Steven Pinker, in his book Enlightenment Now, relates an old Russian joke about two peasants named Boris and Igor. They are both poor. Boris has a goat. Igor does not. One day, Igor is granted a wish by a visiting fairy. What will he wish for?

“I wish,” he says, “that Boris’s goat should die.”

The joke ends there, revealing as much about human nature as about economics. Consider the three things that happen if the fairy grants the wish. One, Boris becomes poorer. Two, Igor stays poor. Three, inequality reduces. Is any of them a good outcome?

I feel exasperated when I hear intellectuals and columnists talking about economic inequality. It is my contention that India’s problem is poverty – and that poverty and inequality are two very different things that often do not coincide.

To illustrate this, I sometimes ask this question: In which of the following countries would you rather be poor: USA or Bangladesh? The obvious answer is USA, where the poor are much better off than the poor of Bangladesh. And yet, while Bangladesh has greater poverty, the USA has higher inequality.

Indeed, take a look at the countries of the world measured by the Gini Index, which is that standard metric used to measure inequality, and you will find that USA, Hong Kong, Singapore and the United Kingdom all have greater inequality than Bangladesh, Liberia, Pakistan and Sierra Leone, which are much poorer. And yet, while the poor of Bangladesh would love to migrate to unequal USA, I don’t hear of too many people wishing to go in the opposite direction.

Indeed, people vote with their feet when it comes to choosing between poverty and inequality. All of human history is a story of migration from rural areas to cities – which have greater inequality.

If poverty and inequality are so different, why do people conflate the two? A key reason is that we tend to think of the world in zero-sum ways. For someone to win, someone else must lose. If the rich get richer, the poor must be getting poorer, and the presence of poverty must be proof of inequality.

But that’s not how the world works. The pie is not fixed. Economic growth is a positive-sum game and leads to an expansion of the pie, and everybody benefits. In absolute terms, the rich get richer, and so do the poor, often enough to come out of poverty. And so, in any growing economy, as poverty reduces, inequality tends to increase. (This is counter-intuitive, I know, so used are we to zero-sum thinking.) This is exactly what has happened in India since we liberalised parts of our economy in 1991.

Most people who complain about inequality in India are using the wrong word, and are really worried about poverty. Put a millionaire in a room with a billionaire, and no one will complain about the inequality in that room. But put a starving beggar in there, and the situation is morally objectionable. It is the poverty that makes it a problem, not the inequality.

You might think that this is just semantics, but words matter. Poverty and inequality are different phenomena with opposite solutions. You can solve for inequality by making everyone equally poor. Or you could solve for it by redistributing from the rich to the poor, as if the pie was fixed. The problem with this, as any economist will tell you, is that there is a trade-off between redistribution and growth. All redistribution comes at the cost of growing the pie – and only growth can solve the problem of poverty in a country like ours.

It has been estimated that in India, for every one percent rise in GDP, two million people come out of poverty. That is a stunning statistic. When millions of Indians don’t have enough money to eat properly or sleep with a roof over their heads, it is our moral imperative to help them rise out of poverty. The policies that will make this possible – allowing free markets, incentivising investment and job creation, removing state oppression – are likely to lead to greater inequality. So what? It is more urgent to make sure that every Indian has enough to fulfil his basic needs – what the philosopher Harry Frankfurt, in his fine book On Inequality, called the Doctrine of Sufficiency.

The elite in their airconditioned drawing rooms, and those who live in rich countries, can follow the fashions of the West and talk compassionately about inequality. India does not have that luxury.

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 23rd installment of The Rationalist, my column for the Times of India.

I had a strange dream last night. I dreamt that the government had passed a law that made using laptops illegal. I would have to write this column by hand. I would also have to leave my home in Mumbai to deliver it in person to my editor in Delhi. I woke up trembling and angry – and realised how Indian farmers feel every single day of their lives.

My column today is a tale of two satyagrahas. Both involve farmers, technology and the freedom of choice. One of them began this month – but first, let us go back to the turn of the millennium.

As the 1990s came to an end, cotton farmers across India were in distress. Pests known as bollworms were ravaging crops across the country. Farmers had to use increasing amounts of pesticide to keep them at bay. The costs of the pesticide and the amount of labour involved made it unviable – and often, the crops would fail anyway.

Then, technology came to the rescue. The farmers heard of Bt Cotton, a genetically modified type of cotton that kept these pests away, and was being used around the world. But they were illegal in India, even though no bad effects had ever been recorded. Well, who cares about ‘illegal’ when it is a matter of life and death?

Farmers in Gujarat got hold of Bt Cotton seeds from the black market and planted them. You’ll never guess what happened next. As 2002 began, all cotton crops in Gujarat failed – except the 10,000 hectares that had Bt Cotton. The government did not care about the failed crops. They cared about the ‘illegal’ ones. They ordered all the Bt Cotton crops to be destroyed.

It was time for a satyagraha – and not just in Gujarat. The late Sharad Joshi, leader of the Shetkari Sanghatana in Maharashtra, took around 10,000 farmers to Gujarat to stand with their fellows there. They sat in the fields of Bt Cotton and basically said, ‘Over our dead bodies.’ ¬Joshi’s point was simple: all other citizens of India have access to the latest technology from all over. They are all empowered with choice. Why should farmers be held back?

The satyagraha was successful. The ban on Bt Cotton was lifted.

There are three things I would like to point out here. One, the lifting of the ban transformed cotton farming in India. Over 90% of Indian farmers now use Bt Cotton. India has become the world’s largest producer of cotton, moving ahead of China. According to agriculture expert Ashok Gulati, India has gained US$ 67 billion in the years since from higher exports and import savings because of Bt Cotton. Most importantly, cotton farmers’ incomes have doubled.

Two, GMO crops have become standard across the world. Around 190 million hectares of GMO crops have been planted worldwide, and GMO foods are accepted in 67 countries. The humanitarian benefits have been massive: Golden Rice, a variety of rice packed with minerals and vitamins, has prevented blindness in countless new-born kids since it was introduced in the Philippines.

Three, despite the fear-mongering of some NGOs, whose existence depends on alarmism, the science behind GMO is settled. No harmful side effects have been noted in all these years, and millions of lives impacted positively. A couple of years ago, over 100 Nobel Laureates signed a petition asserting that GMO foods were safe, and blasting anti-science NGOs that stood in the way of progress. There is scientific consensus on this.

The science may be settled, but the politics is not. The government still bans some types of GMO seeds, such as Bt Brinjal, which was developed by an Indian company called Mahyco, and used successfully in Bangladesh. More crucially, a variety called HT Bt Cotton, which fights weeds, is also banned. Weeding takes up to 15% of a farmer’s time, and often makes farming unviable. Farmers across the world use this variant – 60% of global cotton crops are HT Bt. Indian farmers are so desperate for it that they choose to break the law and buy expensive seeds from the black market – but the government is cracking down. A farmer in Haryana had his crop destroyed by the government in May.

On June 10 this year, a farmer named Lalit Bahale in the Akola District of Maharashtra kicked off a satyagraha by planting banned seeds of HT Bt Cotton and Bt Brinjal. He was soon joined by thousands of farmers. Far from our urban eyes, a heroic fight has begun. Our farmers, already victimised and oppressed by a predatory government in countless ways, are fighting for their right to take charge of their lives.

As this brave struggle unfolds, I am left with a troubling question: All those satyagrahas of the past by our great freedom fighters, what were they for, if all they got us was independence and not freedom?

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

Hi,

  I wanted to open a discussion on the stylus flowtool.  My purpose is to see if there are users out there who are having success with the tool.  To have some discussions around issues that I am running into and to get a user point of view on the problems I am trying to solve.

  Let's start the conversation with : Is there anyone out there trying to use flowtool?  Do you have a centralized flow, or each user has their own?

Thanks, and I look forward to the conversations...

--Craig Crump

How can I make innovus start with common UI instead of legacy? When I launch Innovus with command "innovus", I get the legacy UI. I have Innovus version 17.11 installed. 

Thanks in advance.

Hello Everyone,

I was finishing the layout via Innovus and ran verifyConnectivity followed by checkRoute.

verifyConnectivity was okay and it showed no errors and no warnings, whereas checkRoute showed there are 3 unrouted nets.

When i ran the checkRoute command again immediately, it showed no unrouted/unconnected nets.

Which of these commands should we trust or is this really unrouted nets issue?

Looking forward for a response, thanks in advance.

Regards,

Vijay

For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

When I place a pcell and do not change the W parameter (default is used) the value is not saved in the OA cell property.

When I change the default value of the super master now, the old pcell will get the new default value automatically because there is nothing saved inside the OA cell for this parameter.

Do you have any Idea, that how we can save the default values in the OA cell properties so that this value doesn't get updated if the default values are updated in the new PDKs

Hi there,

I'm running a transient simulation, and I want to get all instances with model implementation hisim_hv because after that I want to process the data and to adjust some parameters for this kind of devices before dumping the values.

What is the easiest/fastest way to get those instances in skill/ocean?

What I did until now: 

- save the final OP of the simulation and then in skill

openResults()
selectResults('tranOp)
report(?type "hisim_hv" ?param "vgs")

Output seems to be promising, and looks like I can redirect it to a file and after that I have to parse the file.

Is there other simple way? I mean to not save data to file and to parse it.

Eventually having an instance name, is it possible to get the model implementation (hsim_hv, bsim4, etc..)? 

Best Regards,

Marcel

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Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)

Hi, I want to add values to components in my SiP design such as 1nF or 15nH. There is already in existence a COMP_VALUE property reserved for this as shown during BOM generation. This property is not visible under the Edit/Properties dialog for component or symbol find filters. We have already created user properties called COMP_MFG and COMP_MFG_PN that it editable at a component level. When we try to add COMP_VALUE it is reported as a reserved name in Cadence but this name is not listed in the properties dialog. Is there a way to turn on the visibility and editablility of this or other hidden reserved Cadence property names? How can I assign a string value to the COMP_VALUE property?

Thanks

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain...

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