A shift register unit comprises: a first transistor, a pulling-up close unit, a pulling-up start unit, a first pulling-up unit, a second pulling-up unit, a trigger unit, and an output unit. A shift register circuit, an array substrate and a display device are also provided. The shift register unit, the shift register circuit, the array substrate and the display device can reduce drift of a gate threshold voltage of a gate line driving transistor and improve operation stability of devices.

A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.

An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i−1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i−2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

A bilateral cargo strap system is provided as a means of securing a variety of different cargo within a storage area. The bilateral cargo strap system utilizes a combination of elastic straps with perpendicularly positioned stabilizing rods to improve retention of a variety of cargo within a storage area. The elastic straps extend over the retained cargo and are used as the means of engaging mounting features within the storage area. The stabilizing rods effectively distribute the tension force of the elastic straps over the retained cargo securing it in place within the storage space. The bilateral cargo strap system is versatile and may be used to secure a wide variety of cargo including, but not limited to, kayaks, coolers, bicycles, lumber, and construction equipment.

An extendable, intermodal transport platform is disclosed. The invention comprises a standard ISO-length loading platform supported by main beams and crossmembers. The platform has ISO lifting and stacking fitments at its four corners. The platform has extendable supplemental platforms at each end, the extendable supplemental platforms fitting beneath the deck bed of the platform, or extendable to position stacking fitments at over-the-road trailer positions for North American fleet. Inner stacking fitments may laterally expand and retract so as to slide underneath the deck bed between the main beams. In some embodiments the platform includes posts that extend upward to position ISO lifting fitments at standard heights, such as under hydraulic power.

A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.

An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

The invention concerns an oscillator generating a wave composed of a frequency of on the order of terahertz from a beat of two optical waves generated by a dual-frequency optical source. The oscillator includes a modulator the transfer function of which is non-linear for generating harmonics with a frequency of less than one terahertz for each of the optical waves generated by the dual-frequency optical source, an optical detector able to detect at least one harmonic for each of the optical waves generated by the dual-frequency optical source and transforming the harmonics detected into an electrical signal, a phase comparator for comparing the electrical signal with a reference electrical signal, and a module for controlling at least one element of the dual-frequency optical source with a signal obtained from the signal resulting from the comparison.

An atomic oscillator includes: a gas cell which includes two window portions having a light transmissive property and in which metal atoms are sealed; a light emitting portion that emits excitation light to excite the metal atoms in the gas cell; a light detecting portion that detects the excitation light transmitted through the gas cell; a heater that generates heat; and a connection member that thermally connects the heater and each window portion of the gas cell to each other.

The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

This invention relates to a novel rotary control valve with new joint methods and flow control mechanisms, inline-reparability and fully metal seals more particularly to a triple offset butterfly valve or ball valve with those features used for on-off and flow controlling under multiple extreme conditions or in severe services; such as the integrated gasification combined cycle under high temperature and pressure, Fluid Catalytic Cracking under high temperature over 1200 F with hard diamond like catalytic particles, shale fracking process under extreme high pressure and high velocity fluid with solid particles and corrosive additives and other critical applications for products life lasting 5 to 30 years like deepsea flow control systems and nuclear power plants and for the applications of millions cycles like jet or rocket turbine engine fuel delivery systems with high velocity fuel fluid mixed with highly oxidative gas under temperature 1365 F.

A butterfly valve (100) is provided. The butterfly valve (100) includes a valve body (103) including a valve bore (109) passing through the valve body (103), with the valve bore (109) including an upstream valve bore portion (109U) and a downstream valve bore portion (109D), a shaft bore (112), a valve shaft (121) located in the shaft bore (112) and extending substantially across the valve bore (109), and a valve flap (107) affixed to the valve shaft (121) and configured to be rotated by the valve shaft (121). The valve flap (107) is configured to rotate between a closed orientation blocking the valve bore (109) and an open orientation. The valve flap (107) is affixed on an upstream valve bore portion side of the valve shaft (121), wherein incoming fluid presses the valve flap (107) against the valve shaft (121).

A butterfly valve including a valve body having a passage, a valve shaft assembly, a valve plate, and a tube that is friction fit inside the passage is provided. The valve shaft assembly includes a first shaft portion and a second shaft portion. The first and second shaft portions are in opposing spaced relation with the valve plate disposed therebetween. The valve plate has a flange such that when the butterfly valve is in the closed position a seal is formed with the tube, which is disposed within the fluid flow passage. The valve plate has lip extending from a portion of the valve plate that is radially outward from the circumference of the tube. The lip acts to reduce flow induced torque experienced while the valve plate is actuated from the closed to the open position.

Water valves and methods of regulating fluid flow for low ambient pressure water sources that reduce the amount of filtration needed for valve mechanisms operating in the water source.

A drain plug assembly that has particular application for sealing a drain hole in a high voltage battery compartment on a vehicle. The plug assembly includes a plug that inserted into the drain hole. The plug assembly further includes a return spring coupled to the plug and causing the plug to be biased into the drain hole. The plug assembly also includes at least one shape memory alloy device coupled to the plug and a support structure. The SMA device receives an electrical current that causes the device to contract and move the plug out of the drain hole against the bias of the return spring.

A method for operating a processing system, in which product units of different formats are processed. The processing system contains a plurality of processing devices that are arranged one after the other in a processing line. In the event of a format changeover, certain component arrangements arranged in the processing system must be adapted to the new product format. In the event of an upcoming format change, a gap in the conveyed goods is generated while the conveying operation is maintained, wherein the gap in the conveyed goods runs through the processing system along the processing devices. As soon as the gap in the conveyed goods runs through a component arrangement to be adapted to the new format, the format is changed over at the component arrangement while the gap in the conveyed goods runs through the component arrangement.

A supply device (10) for a machine for transversely cutting two strips (11 and 12) of a flexible material, in particular a strip of paper, moving continuously, to produce separate stacks of documents cut transversely according to predetermined formats. The device comprises lower and upper driving mechanisms (13, 14) associated with the two strips (11, 12) of flexible material respectively, which each include a mechanically rotated first roller (13a, 14a) and a freely rotatable second bearing roller (13b and 14b). The driving mechanism is mounted on a frame (15) supported by a movable platform (16) which is rigidly connected to a linear actuator (17) arranged to be moved transversely with respect to the direction of movement of the strips (11 and 12). Optical reading cells (11a, 11b, 12a, 12b) define the operating modes of the driving servomotors (13b and 14b) and of the linear actuator (17).

A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

A counter substrate for liquid crystal display includes a transparent substrate, a black matrix, and stripe transparent electrodes. The black matrix divides a plane surface of the transparent substrate into pixel or sub-pixel unit to form a light-shielded area and openings above the plane surface. The stripe transparent electrodes are formed into the pixel unit or the sub-pixel unit above the plane surface. The black matrix includes a frame pattern including two sides facing each other in parallel in the pixel or the sub-pixel unit, and a linear central pattern which is parallel to the two sides of the frame pattern and is formed at a midsection of the pixel or the sub-pixel unit. The transparent electrodes are each parallel to the two sides of the frame pattern and the central pattern and are located symmetrically to the central pattern.

Embodiments of the disclosed technology relate to a color filter substrate and a method of manufacturing the same. The color filter substrate comprises a base substrate having a black matrix pattern thereon, the black matrix pattern having a plurality of openings; and a plurality of color filter layers in different colors, disposed on the base substrate and located at the openings of the black matrix pattern, the color filter layers being glass layers in different colors.

According to one embodiment, a first gene encodes a reporter protein. The first gene is disposed at the downstream of the gene promoter. A second gene is disposed at the downstream of the gene promoter and encodes a replication origin-binding protein. An internal ribosome entry site is disposed between the first gene and the second gene. The transcription termination signal sequence encodes a signal for terminating the transcription of the first gene and the second gene. A replication origin sequence is recognized by the replication origin-binding protein.

Methods and compositions for targeted delivery of biotherapeutics are provided. The compositions comprise bile-sensitive St. thermophilus bacteria modified to release a biotherapeutic agent following bile exposure. Biotherapeutic agents released by the St. thermophilus bacteria disclosed herein include AQ and AQR rich peptides. Methods of the invention comprise administering to a subject a St. thermophilus bacterium modified to release a biotherapeutic agent following bile exposure. Administration of the St. thermophilus bacterium promotes a desired therapeutic response. The bacterium may be modified to express and release AQ or AQR rich peptides which subsequently inhibit cellular apoptosis or reduce mucosal damage. Thus, methods of the invention find use in treating or preventing a variety of gastrointestinal disorders including C. difficile infection and antibiotic-associated diarrhea.

The invention is directed to a single-step method for rapidly and efficiently preparing protein-polymer conjugates, including an insulin-polymer conjugate. According to the method of the present invention, a protein and hydrophilic polymer are contacted in the presence of at least one organic solvent and at least one metal chelator, under conditions that promote the formation of a conjugate of the protein and polymer. Thus, the invention is directed to the site-specific modification of selected proteins, such as insulin, with poly(ethylene glycol) at residue PheB1. The invention also provides a pharmaceutical formulation for encapsulating the conjugate in a biodegradable polymer.

Isolated polynucleotides and polypeptides and recombinant DNA constructs particularly useful for altering agronomic characteristics of plants under nitrogen limiting conditions, compositions (such as plants or seeds) comprising these recombinant DNA constructs, and methods utilizing these recombinant DNA constructs. The recombinant DNA construct comprises a polynucleotide operably linked to a promoter functional in a plant, wherein said polynucleotide encodes an LNT1 polypeptide.

The present invention relates to a novel method for analyzing nucleic acid sequences based on real-time detection of DNA polymerase-catalyzed incorporation of each of the four nucleotide bases, supplied individually and serially in a microfluidic system, to a reaction cell containing a template system comprising a DNA fragment of unknown sequence and an oligonucleotide primer. Incorporation of a nucleotide base into the template system can be detected by any of a variety of methods including but not limited to fluorescence and chemiluminescence detection. Alternatively, microcalorimetic detection of the heat generated by the incorporation of a nucleotide into the extending template system using thermopile, thermistor and refractive index measurements can be used to detect extension reactions.

Provided herein are methods for making water-soluble nanoparticles comprising a core/shell nanocrystal that is coated with a surface layer comprising enough hydrophilic ligands to render the nanoparticle water soluble or water dispersable. Methods for crosslinking molecules on the surface of a nanoparticle, which methods can be used on the above water-soluble nanoparticles also are provided. Nanoparticle compositions resulting from these methods are also provided.

Disclosed are process for contacting a protein containing material with one or more wet-mill streams. The protein content of the protein containing material is increased.

A stylish ready-to-assemble chaise lounge and sofa which may be easily and quickly assembled by a consumer, is provided. The invention is a kit from which either a stylish chaise lounge or a sofa may be easily assembled by a consumer using a single Allen wrench. The kits, both chaise and sofa, comprise a seat base, a long side seatback and a short side seatback, feet, fasteners and cushions. With regard to the chaise, the long and short side chaise seatbacks have rectangular lower portions with upper portions featuring a flowing curved “waterfall” seating surface which improves the comfort of a user leaning back against the seatback.

An integrated tuner circuit has an arbitrary IF (intermediate frequency) output. The tuner includes an integrated circuit with a fixed-frequency control loop and a matched external variable capacitance Ct, to achieve tracking of a tuned LC band-pass filter with an arbitrary oscillator.

A tunable narrow band radio frequency (RF) filter (200) includes an RF input (225), an RF output (227), a capacitive network (201-209) for coupling the RF input (225) with the RF output (227) and an inductive network (219-223) for resonating the filter at a predetermined center frequency. A number of semiconductor devices such as varactor diodes (215, 217, 229, 233) are used for tuning respective capacitors in the capacitive network (201-209). A single voltage source (Vc) is used for tuning each one of the respective varactor diodes for moving the resonant frequency of the filter over a substantially wide frequency range.

In a signal communication device, a frequency-selective filter has at least one component that is biased by a control signal to establish a center frequency of the frequency-selective filter. A closed-loop bias generator is provided to generate the control signal and to adjust the control signal based, at least in part, on a comparison of the control signal and a reference signal.

A system includes a filter and a tuner formed on an integrated circuit. The filter receives an input signal comprising a first number of channels and communicates an intermediate output signal comprising a second number of channels less than the first number of channels. The tuner is coupled to the filter and receives the intermediate output signal and communicates an output signal comprising a third number of channels less than the second number of channels.

Disclosed are one-port and two-port voltage-tunable micro-electromechanical capacitors, switches, and filter devices. High aspect-ratio metal micromachining is used to implement very high quality factor (Q) tunable and fixed capacitors, fixed inductors, and low insertion loss tunable and fixed bandpass LC filters. The tunable capacitors can move in the plane of the substrate by the application of DC voltages and achieve greater than 100% of tuning. A combination of low-loss substrate and highest conductivity metal is used to achieve record high Q and low insertion loss at radio frequencies. The disclosed tunable capacitor structure can also be used as a micromechanical switch.

A band-pass filter device includes: a plurality of band-pass filter elements on a principal plane of a substrate; wherein the band-pass filter elements correspond to a plurality of respective channels divided by frequency regions, and each have a plurality of piezoelectric resonators. Each of the piezoelectric resonators includes a piezoelectric film whose periphery is supported by the substrate, a first electrode formed on a lower surface of the piezoelectric film, a second electrode formed on an upper surface of the piezoelectric film and formed in a state of overlapping at least a part of the first electrode with the piezoelectric film interposed between the second electrode and the first electrode, a lower space formed between the substrate and the piezoelectric film, and an upper space formed over the piezoelectric film.

Methods and apparatus for computing the carrier frequency of a transmitter using frequency modulated digital data to compensate for frequency shifting of the transmitter and the receiver local oscillators and for bandwidth adjustment of the receiver's filter. In particular, methods and apparatus are disclosed for binary systems transmitting “1” and “0” data using decoded or undecoded received signals.