The present invention relates to an item produced via thermoforming and comprising: i) a biodegradable polyester comprising:a) succinic acid;b) optionally one or more C6-C20 dicarboxylic acids; e) 1,3-propanediol or 1,4-butanediol; f) a chain extender or branching agent;ii) polylactic acid;iii) at least one mineral filler; The invention further relates to processes for producing the abovementioned items.

Disclosed is an epoxy resin composition used for encapsulation of a semiconductor containing an epoxy resin (A), a curing agent (B), an inorganic filler (C) and a mold releasing agent, in which the mold releasing agent contains a compound (D) having a copolymer of an α-olefin having 28 to 60 carbon atoms and a maleic anhydride esterified with a long chain aliphatic alcohol having 10 to 25 carbon atoms.

A method, system and computer program product for intelligently responding to hardware failures so as to optimize system performance. An administrative server monitors the utilization of the hardware as well as the software components running on the hardware to assess a context of the software components running on the hardware. Upon detecting a hardware failure, the administrative server analyzes the hardware failure to determine the type of hardware failure and analyzes the properties of the workload running on the failed hardware. The administrative server then responds to the detected hardware failure based on various factors, including the type of the hardware failure, the properties of the workload running on the failed hardware and the context of the software running on the failed hardware. In this manner, by taking into consideration such factors in responding to the detected hardware failure, a more intelligent response is provided that optimizes system performance.

Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.

The invention in particular has as an object detecting incompatibility between equipment items of a on-board system. A logic interface associated with one equipment item comprises at least one input while a logic interface associated with another equipment item comprises at least one output. The input and the output are connected. After a minimal data definition level associated with the input and a data definition level associated with the output have been obtained (505), the said minimal data definition level associated with the input is compared (515) with the said data definition level associated with the output. Following this comparison, if the said minimal data definition level associated with the input is lower than the said data definition level associated with the output, an alarm indicating an incompatibility of these two equipment items is generated (545).

Aspects of the present invention provide a tool for analyzing and remediating an update-related failure. In an embodiment, a failure state of a computer system that has been arrived at as a result of an update is captured. A semantic diff that includes the difference between the failure state and at least one of an original state or a completion state is then computed. This semantic diff is transformed into a feature vector format. Then the transformed semantic diff is analyzed to determine a remediation for the update. Failure and/or resolution signatures can be constructed using the semantic diff and contextual data, and these signatures can be used in comparison and analysis of failures and resolutions.

An approach for introspection of a software component and generation of a conditional memory dump, a computing device executing an introspection program with respect to the software component is provided. An introspection system comprises one or more conditions for generating the conditional memory dump based on operations of the software component. In one aspect, a computing device detects, through an introspection program, whether the one or more conditions are satisfied by the software component based on information in an introspection analyzer of the introspection program. In addition, the computing device indicates, through the introspection program, if the one or more conditions are satisfied by the software component. In another aspect, responsive to the indication, the computing device generates the conditional memory dump through the introspection program.

A method to prevent failure on a server computer due to internally and/or externally induced shock and/or vibration. The method includes acquiring, by at least one sensor, analog acceleration data of components in a server computer. The data is then converted to digital format and stored within a motor drive assembly processor memory unit. The processor analyzes the stored data for existence of machine degradation. In response to detecting the existence of machine degradation, the motor drive assembly processor initiates remediation procedures. The remediation procedures include controlling rotating speed of moving devices or performing a complete system shut down.

Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.

A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.

An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point.

Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

A method and user equipment for simultaneous transmission of a first set of information bits and a second set of information bits by a user equipment, either separately encoded utilizing transmit power or rate matching to increase successful decoding of a set of information bits, or jointly encoding using a priori knowledge or bit positioning to increase successful decoding. Also, the use of joint coding where a first set of information bits is encoded first and then encoded with a second set of information bits, and modulation symbol mapping are provided.

Within a radio communication network infrastructure transmitting data organized into a sequence of symbols to a receiving device over a plurality of radio links, data to be transmitted is encoded according to an error correction coding scheme in order to produce a set of systematic symbols and a set of corresponding redundancy symbols; the systematic symbols and a first subset of the corresponding redundancy symbols are transmitted, over a first radio link among said plurality of radio links, in broadcast mode, and a second subset of the corresponding redundancy symbols, distinct from the first one, is transmitted over a second radio link among said plurality of radio links.

According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

A method of operating a memory controller to control a memory device includes reading a read vector from the memory device and correcting one or more errors in the read vector, where a power consumed at the correcting is varied according to the number of errors in the read vector.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Methods and systems for in-place updating original content stored in a non-volatile storage device and for yielding updated content. Some of the described embodiments illustrate the possibilities for reduction in storage operations, storage blocks, and/or update package size. Some of the described embodiments include the writing of error recovery result(s) such as XOR result(s) which enable the recovery of data in case of an interruption of the update process. In some of the described embodiments, there is re-usage of a protection buffer containing content which is required in the update process.

A packet transmission/reception apparatus and method is provided. The packet transmission method of the present invention includes acquiring a source payload including partial source symbols from a source block, generating a source packet including the source payload and an identifier (ID) of the source payload, generating a repair packet including a repair payload corresponding to the source payload and an ID of the repair payload, generating a Forward Error Correction (FEC) packet block including the source and repair packets, and transmitting the FEC packet block. The source payload ID includes a source payload sequence number incrementing by 1 per source packet. The packet transmission/reception method of the present invention is advantageous in improving error correction capability and network resource utilization efficiency.

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.

The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r1; determining a second demodulated symbol r2; determining a first parity symbol p1; determining a second parity symbol p2; determining a super-parity symbol q1; and detecting a parity error in the sequence of DQPSK symbols by comparing a combination of the first parity symbol p1 and the second parity symbol p2 against the super-parity symbol q1, wherein a parity between two DQPSK symbols describes a phase difference between the two DQPSK symbols.

An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments. Further, the system includes a controller configured to provide the two or more first data segments of the data word to the first encoder for encoding and to provide the one or more second data segments of the data word to the second encoder for encoding.

A wireless communication system including a sender apparatus having a plurality of transmitting antennas that performs MIMO transmission of a plurality of data blocks; and a receiver apparatus that receives the plurality of data blocks. The sender apparatus transmits a process number via a control channel different from a data channel to the receiver apparatus, and wherein when the MIMO diversity transmission is performed, the receiver apparatus performs HARQ processing in the received data blocks based on not a process number which prevents the data blocks from competing but the received process number from the sender apparatus.

Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

Containment systems and methods safely and permanently encapsulate a sharp portion of a sharp medical instrument (e.g. a hypodermic needle). The containment system includes a cap or other container formed of a durable and flexible material having a rim defining an open end configured to receive a sharp portion therein, an interior surface, wherein at least a portion of the interior surface comprises a puncturing element, and a bladder contained within the cap proximate the puncturing element, the bladder containing a first component of a liquid hardenable solution. Opposing sides of the cap can be deformed under external pressure to cause the puncturing element to puncture the bladder so as to release the first component of the liquid hardenable solution from the bladder such that the first component contacts the sharp portion and the sharp portion is substantially permanently retained inside the cap by the liquid hardenable solution.

Containment systems and methods safely and permanently encapsulate a sharp portion of a sharp medical instrument (e.g. a hypodermic needle). The containment system includes a cap or other container formed of a durable and flexible material and having a rim defining an open end configured to receive the sharp portion therein and an adhesive disposed on an interior surface of the container. The method of use includes inserting the sharp medical instrument into the container, and compressing the sides of the container to permanently encapsulate the sharp portion of the medical instrument within the adhesive. The adhesive may be an adhesive tape and may be protected before use by a covering, which may be removed at the time of use by pulling a pull tab extending from an opening in the container.

A method of disposing nuclear waste in underground rock formations is presented. The method includes the steps of selecting a land area having a rock formation positioned there-below of a depth able to prevent radioactive material placed therein from reaching the surface and drilling a vertical wellbore from the surface, to a depth ranging between 5,000 feet and 25,000 feet, into the underground rock formation or repository. A plurality of horizontal laterals or horizontal wellbores, ranging in length from 500 feet to 40,000 feet, are drilled from the vertical wellbore into the underground rock formation or repository. Nuclear waste to be stored within these laterals is encapsulated in a special waste canister and these nuclear waste canisters are positioned within the horizontal laterals wherein they are sealed to prevent loss and leakage. Means are also provided by which these canisters are adapted to allow retrievability of the canisters from the wellbore at a later date and to return the waste to the surface for use after retrieval.

Certain exemplary embodiments can provide a system, machine, device, manufacture, circuit, composition, and/or user interface adapted for and/or resulting from, and/or a method and/or machine-readable medium comprising machine-implementable instructions for, activities that can comprise and/or relate to, in a treatment zone, reacting an oxygen-comprising gas, one or more selected ferric/ferrous chelates, one or more selected nitrates and/or nitrites, and/or anaerobic wastewater.

The present invention intends to provide a method for removing radioactive cesium, or radioactive iodine and radioactive cesium that is simple and low-cost, further does not require an energy source such as electricity, moreover can take in and stably immobilize the removed radioactive substances within a solid, and can reduce the volume of radioactive waste as necessary, and to provide a hydrophilic resin composition using for the method for removing radioactive cesium, or radioactive iodine and radioactive cesium, and the object of the present invention is achieved by using a hydrophilic resin composition containing: at least one hydrophilic resin selected from the group consisting of a hydrophilic polyurethane resin, a hydrophilic polyurea resin, and a hydrophilic polyurethane-polyurea resin each having at least a hydrophilic segment; and a zeolite dispersed therein in a ratio of at least 1 to 200 mass parts relative to 100 mass parts of the hydrophilic resin.

General medication disposal systems are provided. Aspects of the systems include devices having a sealable container dimensioned to accommodate a pharmaceutical composition; and an amount of an inactivating substance, e.g., granulated or pelletized activated carbon, present inside of the sealable container. Aspects of the invention further include methods of making and using the systems, as well as kits comprising the devices of the system.

An apparatus for recovering valuable elements is provided herein. In some embodiments, the apparatus having a conveyor; a container configured to be moved on the conveyor, wherein the container has an open surface; a paper package which contains a mixture containing valuable elements, the paper package being configured to be disposed in the container and to be combusted; a cover that covers the open surface of the container, the cover having an opening for discharging valuable elements vaporized from the mixture; a microwave oven through which the container having the cover and the paper package passes, wherein the microwave oven having a microwave generator and a discharging opening for discharging the valuable elements vaporized from the mixture; and a condenser coupled to the discharge opening, wherein the condenser recovers the valuable elements vaporized from the mixture.

A method and apparatus for the stabilization and safe removal of buried waste that is tested and classified as being transuranic or not transuranic waste and disposed accordingly. The buried waste (usually in vertical pipe units) is enclosed in a casing and ground and mixed with the surrounding soil. This process allows for chemical reactions to occur that stabilizes the mixture. The entire process is contained within the casing to avoid contamination. In situ or external testing is done for radio isotopes to classify the waste. If it is classified as transuranic the waste is removed in a controlled way into a retrieval enclosure and disposed off in drums. If the waste is not transuranic then grout is introduced into the mixture, allowed to set and the resulting monolith is removed and buried in trenches.

Apparatus and a method for decomposing a body of a deceased person, as an alternative to traditional cremation. The apparatus includes a primary vessel where the body is treated with a highly basic solvent to render the body into skeletal remains and liquid remains. A clamp is applied to the skull during processing for solvent access to the skull. A secondary vessel is used to receive the liquid remains from the primary vessel and further treat them. During this further treatment, the skeletal remains left in the primary vessel after the liquefied portion has been transferred to the secondary vessel, can be treated to be decolorized and deodorized, and then returned to the decedent's next of kin as ash-like material.

A treatment system and a method for removal of at least one halogenated compound, such as PCBs, found in contaminated systems are provided. The treatment system includes a polymer blanket for receiving at least one non-polar solvent. The halogenated compound permeates into or through a wall of the polymer blanket where it is solubilized with at least one non-polar solvent received by said polymer blanket forming a halogenated solvent mixture. This treatment system and method provides for the in situ removal of halogenated compounds from the contaminated system. In one embodiment, the halogenated solvent mixture is subjected to subsequent processes which destroy and/or degrade the halogenated compound.

The present invention relates to a subsurface refuse collection system comprising an underground bunker (4), a refuse container (3), a deposit bin (1) and a cover (2) with automatic opening and closing which can be powered electrically using a solar system. The container (3) is collected by means of an automated crane (18) with automatic hitching to facilitate collection. The system is equipped with multiple devices to measure volume and weight of the refuse deposited in the deposit bin (1), for the purpose of system monitoring or improvements to the management of truck routes. It also includes a safety device to prevent accidental fails into the underground bunker during collection.

The cost relating to a reduction in volume and storage of a waste resin including a radioactive nuclide is reduced. In an aspect of the invention, a volume reduction processing system 1000 is provided. The volume reduction processing system 1000 includes a radioactivity meter 102 that measures the radioactivity of a processing target resin, a volume reduction processing device 110 that carries out a heating process, and an oxidation process using oxygen plasma P on the processing target resin, and a process stopping point computation unit 180 that determines a process stopping point for carrying out a volume reduction process on the processing target resin with the volume reduction processing device as far as a volume reduction target value. The volume reduction processing device 110 stops at least one process of the heating process and oxidation process on the process stopping point being reached.

Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

An acoustic apparatus including circuitry to correct for acoustic cross-coupling of acoustic drivers mounted in a common acoustic enclosure. A plurality of acoustic drivers are mounted in the acoustic enclosure so that motion of each of the acoustic drivers causes motion in each of the other acoustic drivers. A canceller cancels the motion of each of the acoustic drivers caused by motion of each of the other acoustic drivers. A cancellation adjuster cancels the motion of each of the acoustic drivers that may result from the operation of the canceller.

A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.

A recursive type-IV discrete cosine transform system includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, a second permutation device. The first permutation device performs two-dimensional order permutation operation on N digital signals for generating N two-dimensional first temporal signals. The recursive type-III discrete cosine/sine transform device repeats a type-III discrete cosine/sine transform for generating second temporal signals. The cosine/sine factor generation device sequentially performs cosine/sine factor multiplication and corresponding addition operations for generating third temporal signals. The recursive type-II discrete cosine/sine transform device repeats a type-II discrete cosine/sine transform for generating fourth temporal signals. The second permutation device performs a one-dimensional order permutation operation for generating N one-dimensional output signals. The N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Apparatus and method for processing linear systems of equations and finding a n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision elements and b is an n1 vector corresponding to n predefined high-precision elements. A first iterative process generates n low-precision elements corresponding to an n×1 vector xl satisfying Alxl=bl where Al, bl are elements in low precision. The elements are converted to high-precision data elements to obtain a current solution vector x. A second iterative process generates n low-precision data elements corresponding to an n×1 correction vector dependent on the difference between the vector b and the vector product Ax. Then there is produced from the n low-precision data elements of the correction vector respective high-precision data elements of an n×1 update vector u. The data elements of the current solution vector x are updated such that x=x+u.

Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

Techniques for medium access control. Some techniques include receiving, at a first computing device, a solicitation for at least a first medium access request that specifies at least one time period for transmitting the first medium access request to the second computing device; encoding the first medium access request at least in part by using a compressive sensing encoding technique to obtain a first encoded medium access request; and transmitting the first encoded medium access request to the second computing device during the at least one time period specified in the received solicitation.

A function f(x) is calculated with a calculating apparatus that makes a correct calculation with a low probability. Provided that G and H are cyclic groups, f is a function that maps an element x of the group H into the group G, X1 and X2 are random variables whose values are elements of the group G, x1 is a realized value of the random variable X1, and x2 is a realized value of the random variable X2, an integer calculation part calculates integers a' and b' that satisfy a relation a'a+b'b=1 using two natural numbers a and b that are relatively prime. A first randomizable sampler is capable of calculating f(x)bx1 and designates the calculation result as u. A first exponentiation part calculates u'=ua. A second randomizable sampler is capable of calculating f(x)ax2 and designates the calculation result as v. A second exponentiation part calculates v'=vb. A determining part determines whether u'=v' or not. A final calculation part calculates ub'va' in a case where it is determined that u'=v'.

The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.