1. 9 Surprising Facts About Voyager 2’s Uranus Flyby  Moneycontrol
2. Potential For Life Found On Uranus' Moons, Scientists Reveal  NDTV
3. The anomalous state of Uranus’s magnetosphere during the Voyager 2 flyby  Nature.com
4. Voyager-2 visited Uranus in 1986. Something more happened when it arrived  India Today
5. Uranus and its moons may have ideal conditions for life—but Voyager 2 missed it due to one bad day  The Economic Times

1. Vicky Kaushal looks unrecognisable as Parashurama in Mahavatar first look. Check first poster, release date  Hindustan Times
2. Mahavatar First Poster: Vicky Kaushal Takes On The Role Of "The Eternal Warrior Of Dharma"- Parashurama  NDTV Movies
3. Vicky Kaushal drops powerful FIRST LOOK as Lord Parashurama for ‘Mahavatar’  TOI Etimes
4. entertainment News Live Today November 13, 2024: Vicky Kaushal looks unrecognisable as Parashurama in Mahavatar first look. Check first poster, release date  Hindustan Times
5. Vicky Kaushal to play Chiranjeevi Parashurama in Amar Kaushik’s Mahavatar  India Today

1. Garena Free Fire MAX redeem codes for November 13, 2024: Win bundles, new outfits, and more rewards...  Moneycontrol
2. Garena Free Fire MAX redeem codes for November 12, 2024: Win free gifts, rewards, and know how to redeem...  Moneycontrol
3. Garena Free Fire MAX redeem codes for November 13: Win free in-game rewards daily  The Times of India
4. Garena Free Fire MAX Redeem Codes Today, November 13: Win Free Gifts, Skins And Much More  Jagran English
5. Garena Free Fire MAX November 13 redeem codes: All about Booyah Top-Up event  HT Tech

1. Battered Reliance Shares To Make A Comeback? This Analyst Sees 29% Upside Ahead  Benzinga India
2. Reliance Industries shares may see 30% upside according to CLSA, who cites this key trigger  CNBCTV18
3. RIL shares are down 20% from record high, oversold on charts; here's what analysts say  Business Today
4. Six of India’s top 10 most valuable firms shed Rs 1.55 lakh crore in market value  Moneycontrol
5. Reliance Industries Share Price Today on 13-11-2024: Reliance Industries share price are down by -0.63%, Nifty down by -0.8%  Mint

1. Inflation in nearly half of major states outgrows India's Oct CPI; price pressure steepest in Chhattisgarh  Moneycontrol
2. Retail inflation surges to a 14-month high of 6.2% in October  The Times of India
3. If we exclude vegetable prices, CPI inflation remains in RBI's range: UBI research  The Economic Times
4. Rising food prices are likely to push back beginning of rate cutting cycle  The Indian Express
5. India confident of reaching USD 100 billion trade volume with Russia ahead of 2030 timeline: S Jaishankar  Telegraph India

1. 26 die as bus plunges into Indus in Diamer  DAWN.com
2. 14 Dead As Bus With Wedding Guests Falls Into River In Pak, Bride Survives  NDTV
3. A bus carrying wedding guests falls into a river in northern Pakistan, killing 18  The Times of India
4. Tragic Gilgit-Baltistan Bus Accident Claims 26 Lives During Wedding Journey  Oneindia
5. 14 Drown, 12 Missing In Pakistan After Bus Plunges Into River In PoK's Gilgit-Baltistan  News18

1. Chennai rain: IMD predicts heavy rainfall for Tamil Nadu. Are schools, colleges closed today?  Hindustan Times
2. Chennai rains today: Heavy downpour expected in many Tamil Nadu districts, IMD issues alert. Schools shut today?  Mint
3. Low pressure weakens, but heavy rain in Tamil Nadu may persist  The New Indian Express
4. Tamil Nadu weather: Schools shut in Chennai, IMD puts 17 districts in state on heavy rainfall alert  Business Today
5. Tamil Nadu rains: Schools, colleges closed in several districts amid heavy rain  The Hindu

1. Delhi: India's capital chokes as air pollution turns 'severe'  BBC.com
2. Several flights diverted due to low visibility conditions at Delhi airport  The Times of India
3. Delhi's toxic air: Why you should not take your cough lightly  India Today
4. Delhi air pollution: Visibility near-zero amid thick smog; CPCB says AQI 'very poor', IQAir shows 'hazardous' | Details  Hindustan Times
5. Delhi's IGI airport sees flight diversions as season's first dense fog hits national capital  Moneycontrol

1. BREAKING| 'Bulldozer Reminds Of Lawlessness' : Supreme Court Says Properties Can't Be Demolished Merely...  Live Law - Indian Legal News
2. "Officials To Pay From Salary": Top Court Guidelines On 'Bulldozer Justice'  NDTV
3. ‘Heavens won’t fall on authorities if they hold their hands for some period’: SC sets pan India guidelines against bulldozer action  The Financial Express
4. Executive Can't Become Judge, Pronounce Guilt Of Persons & Punish Them By Demolishing Their Properties :...  Live Law - Indian Legal News
5. ‘Officials will pay for demolitions from their salary’: 5 Key SC observations on ‘chilling’ side of ‘bulldozer justice’  Mint

Xiaomi has recently shown off a demo for their HyperConnect feature, allowing users to share files with Apple users.

The post Xiaomi plays nice with Apple with its new HyperConnect feature appeared first on Phandroid.

According to the latest rumors, the Samsung Galaxy Z Flip FE could be powered by the Exynos 2400 chipset which is surprising.

The post Samsung Galaxy Z Flip FE chipset of choice could surprise you appeared first on Phandroid.

The ASUS ROG Phone 9 has recently been spotted on Geekbench where it appears to be powered by the new Qualcomm chipset.

The post ASUS ROG Phone 9 spotted on Geekbench with Qualcomm’s latest chipset appeared first on Phandroid.

Atlas Biomed's website is no longer active and the phone number listed is dead as well.

In this clip, Steve Jobs pauses for 18 seconds to contemplate a question deeply before answering.

Zomato witnesses approximately 400,000 cancelled orders monthly which prompted it to launch the initiative.

A man recently took to Reddit, seeking help identifying an unknown Devanagari text he found at a flea market in Germany.

US-based comedian Austin Nasso is going viral online for his hilarious impersonation of US-President-elect Donald Trump during a fictional visit to India.

Microsoft announced it has acquired Semantic Machines, a conversational AI startup providing chatbots and AI chat apps founded in 2014 having $20.9 million in funding from investors. The acquisition will help Microsoft catch up with Amazon Alexa, though the latter is more focused on enabling consumer applications of conversational AI.

Microsoft will use Semantic Machine’s acquisition to establish a conversational AI center of excellence in Berkeley to help it innovate in natural language interfaces.

Microsoft has been stepping up its products in conversational AI. It launched the digital assistant Cortana in 2015, as well as social chatbots like XiaoIce. The latest acquisition can help Microsoft beef up its ‘enterprise AI’ offerings.

As the use of NLP (natural language processing) increases in IoT products and services, more startups are getting traction from investors and established players. In June last year, Josh.ai, avoice-controlled home automation software has raised $8M.

Followed by it was SparkCognition that raised $32.5M Series B for its NLP-based threat intelligence platform.

It appears Microsoft’s acquisition of Semantic Machines was motivated by the latter’s strong AI team. The team includes technology entrepreneur Daniel Roth who sold his previous startups Voice Signal Technologies and Shaser BioScience for $300M and $100M respectively. Other team members include Stanford AI Professor Percy Liang, developer of Google Assistant Core AI technology and former Apple chief speech scientist Larry Gillick.

Siemens Building Technologies division announced it will acquire Enlighted Inc., a smart IoT building technology provider. The transaction is expected to close in Q3’18.

Enlighted Inc.’s core element is an advanced lighting control application. It is based on a patented, software-defined smart sensor that collects and monitors real-time occupancy, light levels, temperatures and energy usage.

The sensor can gauge temperature, light level, motion, energy, and has Bluetooth connectivity.

The Enlighted system works by collecting temperature, light and motion data via its smart sensors. A gateway device carries the information to Energy Manager, a secure browser-based interface to create profiles and adjust settings of the entire Enlighted Advanced Lighting Control System. The Energy manager operates as an analytics device.

The whole system consists of multi-function sensors, distributed computing, a network, and software applications run by Enlighted Inc.

Enlighted Inc.’s main target market is commercial real estate. Key use cases of its intelligent Lighting Control System are energy efficiency, controlling heating, ventilation and air conditioning, and building utilization reports.

Use the Postscapes 'Connected Products Framework' to understand the smart home and buildings eco-system.

Smart Lock Company LockState raised $5.8M Series A in new investment to fund its aggressive sales and marketing and partner development plan. The company previously raised $740K seed round and $1M in a round led by angel investors. The lead investor in latest round was Iron Gate Capital. Other investors include Kozo Keikaku Engineering Inc, Nelnet and Service Provider Capital.

The company’s Wi-Fi-enabled RemoteLock is used by 1000s of Airbnb and other vacation rental hosts. It helps hosts remotely provide access to guests. Locking/unlocking codes can be generated via a host’s computer or smartphone.

RemoteLock’s prices start at $299 which is its algorithmic ResortLock. The most pricey lock by LockState is its ‘RemoteLock 7i Black WiFi Commercial Smart Lock’ which costs $479.

Another core product of LockState is its cloud-based remote access platform for internet-enabled locks. It implies users can remotely manage their (internet-enabled) locks via LockState’s cloud platform.

Unlike smartphones and watches, customers don’t look forward to upgrading their smart locks or buying one when new models are launched. Thus, smart lock companies offset this disadvantage by partnering with property management and short-term rental companies to get new customers.

LockState has partnered with vacation rental brands like Airbnb, HomeAway, and other listing partners to automate guest access.

Igloohome a Singapore-based smart lock company also raised an investment of $4M in April this year.

EV Ultimo launches platform to assist brands, buyers, stakeholders in the Electric Vehicles ecosystem

[SAPS] - A former company Director (57) is expected to appear in the Thabamoopo Magistrates Court in Lebowakgomo on 11 November 2024 for allegedly defrauding a pensioner an amount of R378 000.00 in the name of business.

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[SAPS] One hundred and seventy one (171) murder suspects, 261 attempted murder suspects and 250 suspected rapists were among 12 593 suspects who were arrested during various operations by police in KwaZulu-Natal in the month of October. During such operations police also managed to recover 345 firearms and 2 998 rounds of ammunition of various calibre of firearms. Among the recovered firearms were 23 rifles and 17 homemade illegal guns.

[The Conversation Africa] South Africa's finance minister, Enoch Godongwana, announced in his October mid-term budget policy statement that cabinet had approved funding for an early retirement programme to reduce the public sector wage bill. R11 billion (about US$627 million) will be allocated over the next two years to pay for the exit costs of 30,000 civil servants while retaining critical skills and promoting the entry of younger talent.

[SAnews.gov.za] With the United Nations Framework Convention on Climate Change (COP29) taking place this week, South Africa expects the COP29 Presidency to enhance efforts to finalise the New Collective Quantified Goal on Finance (NCQG), which is a matter of great importance for developing economies.

[COSATU] The Congress of South African Trade Unions (COSATU) is deeply concerned by the Minister for Communications and Digital Technologies, Mr. S. Malatsi's sudden withdrawal of the South African Broadcasting Corporation (SABC) SOC Ltd Bill from Parliament where it was being engaged upon by the National Assembly's Portfolio Committee: Communications and Digital Technologies.

[Namibian] Russian company Rosatom and South African AllWeld Nuclear and Industrial are joining forces to promote the sustainable development of nuclear energy in Africa.

[COSATU] The Congress of South African Trade Unions (COSATU) welcomes the slight drop in the expanded unemployment rate from 42.6% in the second quarter to 41.9% in the third quarter of this year.

[Parliament of South Africa] Parliament, Tuesday, 12 November 2024 - The National Assembly (NA) will hold a plenary session scheduled to start at 10:00. Among the items on the agenda from 10:00 to 13:00 is the statement by the Minister of Water and Sanitation on water security in the country and a debate on 16 Days of Activism for no violence against women and children. The debate will be held under the theme, "Marking 30 years of democratic rights for women and fostering national unity to end gender-based violence".

[DA] It is a national embarrassment that the inability of the City of Johannesburg to supply water to its residents, business and public sector offices, has now led to the shutdown of operations at the Constitutional Court, on Constitution Hill in Braamfontein.

PCI-SIG DevCon 2024 – 32^nd Anniversary

For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32^nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.

Why Are Standards Like PCIe So Important?

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.

HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.

Figure 1. Evolution of PCIe Data Rates (source PCI-SIG)

What’s New This Year at DevCon?

At DevCon ’24, the PCIe 7.0 standard will take center stage, and Cadence is showing off a full suite of IP subsystem solutions for PCIe 7.0 this year.

What Sets Cadence Apart?

At Cadence, we believe in building a full subsystem for our testchips with eight lanes of PHY along with a full 8-lane controller. Adding a controller to our testchip significantly increases the efficiency and granularity in characterization and stress testing and enables us to demonstrate interoperability with real-world systems. We are also able to test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice. This approach significantly reduces the risks in our customers’ SoC designs.

Figure 2: Piper - Cadence PHY IP for PCIe 7.0

Figure 3: Industry’s first IP subsystem for PCIe 7.0

Which Market Is This For?

At a time when accelerated computing has gone mainstream, PCIe links are going to take on a role of higher importance in systems. Direct GPU-to-GPU communication is crucial for scaling out complex computational tasks across multiple graphics processing units (GPUs) or accelerators within servers or computing pods. There is a growing recognition within the industry of a need for scalable, open architecture in high-performance computing. As AI and data-intensive applications evolve, the demand for such technologies will likely increase, positioning PCIe 7.0 as a critical component in the next generation of interface IP.

Here's a recent article describing a potential use case for PCIe 7.0.

Figure 4: Example use case for PCIe 7.0

Why Are Optical Links Important?

It takes multiple buildings of data centers to train AI/ML models today. These buildings are increasingly being distributed across geographies, requiring optical fiber networks that are great at handling the increased bandwidth over long distances. However, these optical modules soon hit a power wall where all the budgeted power is used to drive the signal from point A to point B, and there is not enough power left to run the actual CPUs and GPUs. Such scenarios create a need for non-retimed, linear topologies. Linear Pluggable Optics (LPO) links can significantly reduce module power consumption and latency when compared to traditional Digital Signal Processing (DSP) based retimed optical solutions, which is critical for accelerating AI performance. Swapping from DSP-based solutions to LPO results in significant cost savings that help drive down expenditure due to lower power and cooling requirements, but this requires a robust high-performance ASIC to drive the optics rather than retimers/DSP.

To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare.

Figure 5: Example of ASIC driving linear optics

Compliance Is Key

For PCIe 6.0, the official compliance program has not started yet; this is typical for the SIG where the official compliance follows a few years after the spec is ratified to give enough time for the ecosystem to have initial products ready, and for test and equipment vendors to get their hardware/software up and running. At this time, PCIe Gen6 implementations can only be officially certified up to PCIe 5.0 level (the highest official compliance test suite that the SIG supports). We have taken our PCIe 6.0 IP subsystem solution to the SIG for multiple process nodes, and they are all listed as compliant. You can run this query on the pcisig.com website under the Developers->Integrators list by making the following selections:

Due to space limitations, not all combinations could be tested at the May workshop (e.g., N3 root port) – this will be tested in the next workshop.

Also, the SIG just held an “FYI” compliance event this week to bring together the ecosystem for confidential testing (no results were reported, and data cannot be shared outside without violating the PCI-SIG NDA). We participated in the event with multiple systems and can report that our systems have done quite well. The test ecosystem is not mature yet, and a few more FYI workshops will be conducted before the official compliance for 6.0 is launched. We have collaborated with all the key test vendors for electrical and protocol testing throughout the year. As early as the middle of last year, we were able to provide test cards to all these vendors to demo PCIe 6.0 capabilities in their booths at various events. Many of them recorded these videos, and they can be found online.

• Cadence Subsystem IP for PCIe 6.0: Protocol and Electrical Testing
• Cadence Subsystem IP for CXL Protocol Test Demo
• Cadence Subsystem IP for CXL2.0/3.0 Protocol Test Demo
• Cadence Subsystem IP for PCIe 6.0: Protocol Stack Demo

More at the PCI-SIG Developers Conference

Check us out at the PCI-SIG Developer’s conference on June 12 and 13 to see the following demonstrations:

• Robust performance of Cadence IP for PCIe 7.0 transmitting and receiving 128GT/s signals over non-retimed optics
• Capabilities of Cadence IP for PCIe 7.0 measured using oscilloscope instrumentation detailing its stable electrical performance and margin
• The reliability of Cadence IP for PCIe 6.0 interface using Test Equipment to characterize the PHY receiver quality
• A PCI-SIG-compliant Cadence IP subsystem for PCIe 6.0 optimized for both power and performance

As a leader in PCI Express, Anish Mathew of Cadence will share his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Figure 6: Cadence UIO Implementation Summary

Summary

Cadence showcased PCIe 7.0-ready IP at PCI-SIG Developers Conference 2023 and continues to lead in PCIe IP development, offering complete solutions in advanced nodes for PCIe 7.0 that will be generally available early next year. With a full suite of solutions encompassing PHYs, Controllers, Software, and Verification IP, Cadence is proud to be a member of the PCI-SIG community and is heavily invested in PCIe. Cadence was the first IP provider to bring complete subsystem solutions for PCIe 3.0, 4.0, 5.0, and 6.0 with industry-leading PPA and we are proud to continue this trend with our latest IP subsystem solution for PCIe 7.0, which sets new benchmarks for power, performance, area, and time to market.

We live in a rapidly growing “digitalized world,” with an ever-increasing need for video/music streaming, gaming, AI/machine learning, etc. All of these propel demand on modern SoC design to quickly evolve the SoC by fitting more sophisti...(read more)

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environment. Locking is the most basic requirement for data sharing. A core takes the lock, accesses the shared data structure, and releases the lock. While one core has the lock, other cores are disallowed from accessing the same data structure. Typically, locking is implemented using an atomic read-modify-write bus transaction on a variable allocated in an uncached memory.

This blog shares the AXI4 locking mechanism when implementing an Xtensa LX-based multi-core system on a Xilinx FPGA platform. It uses a dual-core design mapped to a KC705 platform as an example.

Exclusive Access to Accomplish Locking

The Xtensa AXI4 manager provides atomic access using the AXI4 atomic access mechanism. While Xtensa's AXI manager interface generates an exclusive transaction, the subordinate's interface is also expected to support exclusive access, i.e., AXI monitoring. Xilinx BRAM controller's AXI subordinate interface does not support exclusive access, i.e., AXI monitoring: AXI Feature Adoption in Xilinx FPGAs.

Leveraging Xtensa AXI4 Subordinate Exclusive Access

The Xtensa LX AXI subordinate interface supports exclusive access. One approach is to utilize this support and allocate locks in one of the core's local data memories. Ensure that the number of external exclusive managers is configured, typically to the number of cores (Figure 1).

Figure 1

Note that the Xtensa NX AXI subordinate interface does not support exclusive access. For an Xtensa NX design, shared memory with AXI monitoring is required.

In Figure 2, the AXI_crossbar#2 (block in green) routes core#0's manager AXI access (blue connection) to both core's local memories. Core#1's manager AXI (yellow connection) can also access both core's local memories. Locks can be allocated in either core's local data memory.

In-Bound Access on Subordinate Interface

On inbound access, the Xtensa AXI subordinate interface expects a local memory address, i.e., an external entity needs to present the same address as the core would use to access local memory in its 4GB address space. AXI address remap IP (block in pink) translates the AXI system address to each core's local address. For example, assuming locks are allocated in core#0's local memory, core#1 generates an AXI exclusive to access a lock allocated in core#0's local memory (yellow connection). AXI_crossbar#2 forwards transaction to M03_AXI port (green connection). AXI_address_remap#1 translates the AXI system address to the local memory address before presenting it to core#0's AXI subordinate interface (pink connection).

It is possible to configure cores with disjoint local data memory addresses and avoid the need for an address remap IP block. But then it will be a heterogeneous multi-core design with a multi-image build. An address remap IP is required to keep things simple, i.e., a homogeneous multi-core with a single image build. A single image uses a single memory map. Therefore, both cores must have the same view of a lock, i.e., the lock's AXI bus address must be the same for both.

Figure 2

AXI ID Width

Note Xtensa AXI manager interface ID width=4 bits. Xtensa's AXI subordinate interface ID width=12 bits. So, you must configure AXI crossbar#2 and AXI address remap AXI ID width higher than 4. AXI IDs on a manager port are not globally defined; thus, an AXI crossbar with multiple manager ports will internally prefix the manager port index to the ID and provide this concatenated ID to the subordinate device. On return of the transaction to its manager port of origin, this ID prefix will be used to locate the manager port, and the prefix will be truncated. Therefore, the subordinate port ID is wider in bits than the manager port ID. Figure 3 shows the Xilinx crossbar IP AXI ID width configuration.

Figure 3

Software Tools Support

Cadence tools provide a way to place locks at a specific location. For more details, please refer to Cadence's Linker Support Packages (LSP) Reference Manual for Xtensa SDK. .xtos.lock(green) resides in core#0's local memory and holds user-defined and C library locks. The lock segment memory attribute is defined as shared inner (cyan) so that L32EX and S32EX instructions generate an exclusive transaction on an AXI bus. See Figure 4. The stack and per-core Xtos and C library contexts are allocated in local data memory (yellow).

…………..LSP memory map………….
BEGIN dram0
0x40000000: dataRam : dram0 : 0x8000 : writable ;
dram0_0 : C : 0x40000400 - 0x40007fff : STACK : .dram0.rodata .clib.percpu.data .rtos.percpu.data .dram0.data .clib.percpu.bss .rtos.percpu.bss .dram0.bss;
END dram0
…………………
BEGIN sysViewDataRam0
0xA0100000: system : sysViewDataRam0 : 0x8000 : writable, uncached, shared_inner;
lockRam_0 : C : 0xA0100000 - 0xA01003ff : .xtos.lock;
END sysViewDataRam0
…………..

Figure 4

Please visit the Cadence support site for more information on emulating Xtensa cores on FPGAs.

Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet designs and demonstrate high data rate performance in TSMC's 3nm technology(read more)

We are currently setting up the Tempus flow and have ran into some mismatched data regarding ECO and timing reports. I generated a timing report before running ECO and saw six total setup violations. When running opt_signoff -setup, the initial setup summary that was printed in the shell only showed one violation. I can see that violation from the initial setup summary in my pre-ECO timing report and it is not the worst path. Upon further investigation, I forced the tool to try to fix setup on one of the other five violations from the timing report using the opt_signoff_select_setup_endpoints attribute and the tool said that the endpoint had positive slack and would be ignored.

Has anyone experienced something like this before?

Hi, I'm using genus (Version 21.14-s082_1) to synthesis a VHDL-design with multiple power-domains. After reading the power intent file and calling 'apply_power_intent',  I get the following warning:

Warning : Potential problem while applying power intent of 1801 file. [1801-99]
: Cannot find any instance for scope '/:CHIP_TOP'. Rest of commands in this scope will be skipped (set_scope:../../upf/CHIP_TOP.upf:2).
: Check the power intent. If the scenario is expected, this message can be ignored.

The fist two lines of CHIP_TOP.upf:

upf_version 3.1
set_scope :CHIP_TOP

I simulated the same  UPF and VHDL files with Xeclium and was able to verify all the IEEE1801/UPF aspects I need without any problems. I don't know, why genus is having a problem with the 'scope'.
In genus, after getting the warning, running 'set_db power_domain:CHIP_TOP/BLOCK_A/PD_CORE_D .library_domain PD0V5' returns the following error:

Error : <Start> word is not recognized. [TUI-182] [set_db]
: 'power_domain:CHIP_TOP/BLOCK/PD_CORE_D' is not a recognized object/attribute. Type 'help root:' to get a list of all supported objects and attributes.
: Check if the given <Start> word is a valid object_type, object or attribute.

Running 'commit_power_intent' gives me:

Started inserting low power cells...
====================================
Info : Command 'commit_power_intent' cannot proceed as there are no power domains present. [CPI-507]
: Design with no power domains is 'design:CHIP_TOP'.
Completed inserting low power cells (runtime 0.00).
====================================================

I'm suspecting that the problem lies in 'set_scope' and VHDL. I never had such problems with Verilog. I tried every way to reference the hierarchy in the code and now I'm at my wit's end and I need your help o/
How to set the scope with 'set_scope' in UPD 3.1 to the toplevel in VHDL, so that genus accepts it? Or is the problem caused by something else?

Best,

Iqbal

Hi everyone. 

I'm very a new cadence user. I'm not good at using it and quite lost in finding a way to get the results. With the topic, I would like to ask you for some suggestions to improve my cadence skills.

I have some digital decision logic. Some are combinational logic, some are sequential logic that I would like to import or generate random input combination to the inputs of my decision logic to get the maximum, minimum, and average delay power dissipation and area when feeding the different input combination.

My logic has 8-bit, 16-bit, and 32-bit input. The imported data tends to be decimal numbers.

I would like to ask you:

- which tool(s) are the most appropriate to import and feed the different combination to my decision logic?

- which tool is the most appropriate to synthesis with different number of input? - I have used Genus Synthesis Solution so far. However with my skill right now I can only let Genus synthesize my Verilog code one setup at a time. I'm not sure if I there is anyway I can feed a lot of input at a time and get those results (min, max, average of delay, power dissipation and area)

- which language or scripts I should pick up to use and achieve these results?

-where can I find information to solve my problem? which information shall I look for?

Thank you so much for your time!!

Best Regards

I am trying to install IC231 on RHEL 8 using installscape, however configuring keeps failing.

I tried to run the configuration file manually as suggested in one of the previous posts and it gives me following errors:

sh batch_configure.sh
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ncvhdl23.03-d103lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ncvhdl23.03-d103lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ncvhdl64b23.03-d103lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ncvhdl64b23.03-d103lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: oaRedist22.61-p003lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'oaRedist22.61-p003lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: amsEnv64b23.10-p043lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'amsEnv64b23.10-p043lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ihdl64b23.10-p043lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ihdl64b23.10-p043lnx86_101124125631.stat': No such file or directory

I am not very well versed with Linux at the moment but trying. Could any one suggest something or point to what is missing?

Hi! 

I am attempting to create a very simple test pcell that contains a single Nmos 4 terminal device (Gate, Source, Drain, Backgate). However, unlike other devices I have used in the past, the backgate terminal of the device I wish to include within the pcell is an inherited connection, and the other 3 are physical terminals. Note that for the pcell master, I do not want any inherited connections, just physical pins. Hence I need to drive this inherited connection with a pin within my pcell. I started implementing the symbol and schematic first, ensuring I could obtain the correct connectivity, extract netlist, etc. I thought I had it hooked up correctly, but alas I am failing to export the CDL. Let me explain my current approach.

Schematic:

Create the 4 physical pins using a combination of dbCreateInst (for the pin isnt), dbMakeNet, dbCreateTerm and dbCreatePin.

Create the device instance using dbCreateInstByMasterName and setting the desired cdf parameters + callbacks.

For the physical terminals of the device, I'm using dbCreateConnByName to make the connection to the appropriate net that was created above.

For the inherited connection, I am creating a netSet property like so: dbCreateProp(newinst deviceTermName "netSet" netName)

Symbol:

Create the 4 physical pins using a combination of dbCreateRect, dbMakeNet, dbCreateTerm, dbCreatePin.

And then create whatever symbol design I wish using the likes of dbCreateRect, dbCreateLine, etc. 

Everything works fine when using a device without an inherited connection, so I'm guessing I'm missing something along this line... Also, if I copy the contents of the pcell schematic to a regular schematic view, do a check and save, the view extracts just fine. So I wonder if the check and save it fixing the connectivity that I may not have. 

Thanks for any possibly engagement or suggestions 🙂

Keelan

Is there a skill command for "Assign Layout Instance terminals", this form appears when i click on define device correspondence and Bind the devices.

Also,

Problem Statement : i have a schematic with a couple of transistor symbols and and i alos have a corresponding layout view with respective layout transistors but they all are inside a pCell(created by me) i.e layout transistor called inside a custom Pcell. Now i have multiple symbols in schematic view and a single instance(pCell) in layout view. 
Is there a way how i can bind these schematic symbols with layout symbols inside the pCell(custom)? Even if i have to use cph commands i'm fine with it. need help here.

The idea here is to establish XL connectivity between the schematic symbols and corresponding layout transistors(inside the pCell).

Thanks,

Shankar

Hello Community,

Is there any simple way how i can get the coordinates of all the shapes in a layout view?

Currently i'm flattening the layout, getting all the lpps from CV and using setof to get all the shapes of a layer and looping through them to get the coordinates.

Is there a way to do it without having to flatten the layout view and shapes merged or any other elegant way to do it if we flatten it?

Also, dbWriteSkill doesn't give output how i desired

Thanks,

Shankar

Hi All,

I'm using a code (abConvertPolygonToPath.ils) that I found in other posts to convert a rect object to a path object inside a pcell code, but when I try to run a DRC, the layout export fails due to a warning message, here is the log message

*WARNING* (DB-270001): Pcell evaluation for 18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout has the following error(s):

*WARNING* (DB-270002): ("eval" 0 t nil ("*Error* eval: undefined function" abConvertPolygonToPath))

ERROR (XOASIS-231): Pcell evaluation failed for '18A_asaavedr/lay_mesh_BM0_BM4_3p6_3p6/layout' because the Pcell SKILL code contains either a syntax error or an unsupported XOasis function. Check the standard output or the Virtuoso log file for more information. Cadence recommends correcting the Pcell SKILL code to resolve the issue. However, to ignore these errors and continue the translation, you may use the 'ignorePcellEvalFail' option.

INFO (XOASIS-282): Translation Failed. '1' error(s) and '3' warning(s) found.

And when compile the code I get the following message:

*WARNING* defgeneric function already defined - abConvertPolygonToPath

I will aprreciate any help in how to waive this error, or fix it.

Thank you

Hello,

I was looking to destructively and efficiently modify a list that was passed in as an argument to a procedure, by prepending an item to the list.

I noticed that cons lets you do this efficiently, but the operation is non-destructive. Hence this wouldn't work if you are trying to modify a function's list parameter in place.

Here is an example of trying to add "0" to the front of a list:

Cadence AWR Design Environment Software Featured in Multiple Training Course Options: Live and Virtual Starting in October(read more)

AWR V22.1 software introduces the Pointer-Hybrid optimization method which uses a combination of optimization methods, switching back and forth between methods to efficiently find the lowest optimization error function cost. The optimization algorithm automatically determines when to switch to a different optimization method, making this a superior method over manual selection of algorithms. This method is particularly robust in regards to finding the global minima without getting stuck in a local minima well.(read more)