With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and 1c nodes along with the DRAM device speeds going up to 8533 for Lpddr5/8800 for DDR5, Data integrity is becoming a really important issue that the OEMs and other users have to consider as part of the system that relies on the correctness of data being stored in the DRAMs for system to work as designed.

It’s a complicated problem that requires multiple ways to deal with it.

Traditionally one of the main approaches to deal with data errors is to rely on the ECC. ECC requires additional memory storage in which the ECC codes will calculated and stored at the time of memory write to DRAM. These codes will be read back along with the memory data during to the reads and checked against the data to make sure that there are no errors. Typical ECC schemes use Hamming code that provide for single bit error correction and double bit error detection per burst. Also, while several of previous generation of DRAM required Host to keep aside system memory for ECC storage latest DRAMs like Lpddr5 and DDR5 support on die ECC as part of the normal DRAM function that can be enabled using mode registers. DDR5 further requires Host to run through an ECC Error Check and Scrub (ECS) cycle on an average every tECSint time (Average Periodic ECS Interval) to prevent data errors.

Not meeting the DRAM Refresh requirement is a major reason that can lead to loss of data. This could be challenging as the PVT variation can cause the refresh requirement to change over time. Putting the DRAM in Self Refresh mode can help off-loading Refresh tracking responsibilities to DRAM but may prevent Host to do other scheduling optimizations and should be carefully considered.

Some of the other things that can affect the DRAM data are

1. Row hammer where same or adjacent rows are activated again and again leading to loss or changing of data contents in the rows that has not being addressed. Latest DRAMs like Lpddr5/Ddr5 support Refresh Management (including DRFM and ARFM) that allows the Host to compensate for these problems by issuing dedicated RFM commands helping DRAMs deals with potential Data loss issues arising out of Row hammer attacks.
2. Device temperature is another important factor that the Host needs to be aware of and if the application requires DRAM to operate at elevated temperature. The user needs to check with DRAM Vendor on the temperature range that DRAM can still operate. Data integrity at thresholds greater than certain temperature is not assured regardless of refresh rate unless DRAM is manufactured to withstand that.
3. Loss of power to DRAM will cause DRAM to lose all its contents. If this is a real concern for the system designer, they should consider using NVDIMM-N devices which has an onchip controller and a power source which is just enough to allow the DRAM contents to be copied into a backup non-volatile memory before power is lost. When the power is stored back, the stored memory contents in the non-volatile memory will be written back to the DRAM and system can continue to operate as it was before the power loss event occurred.

For transmissions and manufacturing errors DRAMs support additional features like CRC, DFE, Pre-Emphasis and PPR which will be covered in the next blog.

Cadence MMAV VIPs for DDR5/DDR5 DIMM and LPDDR5 are compressive VIP solutions and supports all of the above-listed Data integrity features including support for ECC error injection and SBE correction/DBE detection to assist with the verification challenges dealing with data integrity issues.

More information on Cadence DDR5/LPDDR5 VIP is available at Cadence VIP Memory Models Website.

Shyam 

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every circumstance is difficult to achieve with conventional verification. Learn more how Jasper C2RTL App helps to perform equivalence checking with 100x performance improvement(read more)

Power network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early planning and analysis of 3D-IC power networks, 3D-IC chip-centric power integrity signoff, and hierarchical methods that significantly improve capacity and performance of power integrity (PI) signoff while maintaining a very high level of accuracy at signoff. This blog summarizes the typical design challenges faced by today’s 3D-IC designers, as discussed in our recent webinar, “Addressing 3D-IC Power Integrity Design Challenges.” Please click here to view the full webinar.

Major Trends in Advanced Chip Design

From chips to chiplets, stacked die, 3D-ICs, and more, three major trends are impacting advanced semiconductor packaging design. The first is heterogenous integration, which we define as a disaggregated approach to designing systems on chip (SoCs) from multiple chiplets. This approach is similar to system-in-package (SiP) design, except that instead of integrating multiple bare die – including 3D stacking – on a single substrate, multiple IPs are integrated in the form of chiplets on a single substrate.

The second major trend is around new silicon manufacturing techniques that leverage silicon vias (TSVs) and high-density fanout RDL. These advancements mean that silicon is becoming a more attractive material for packaging, especially when high bandwidth and form factor become key attributes in the end design. This brings new design and verification challenges to most packaging engineers who typically work with organic and ceramic substrate materials.

Finally, on the ecosystem side, all the large semiconductor foundries now offer their own versions of advanced packaging. This brings new ways of supporting design teams with technologies like reference flows and PDKs, concepts that have typically been lacking in the packaging community. Cadence has worked with many of the leading foundries and outsourced semiconductor assembly and test facilities (OSATs) to develop multi-chip(let) packaging reference flows and package assembly design kits. The downside is that, with the time restrictions designers are under today, there isn’t enough time to simulate the details of these flows and PDKs further.

For those who must make the best electro/thermal/physical decisions to achieve the best power/performance/area/cost (PPAC), factors can include accurate die size estimations, thermal feasibility, die-to-die interconnect planning, interposer planning (silicon/organic), front-to-front and front-to-back (F2F/F2B) planning, layer stack and electromigration/ IR drop (EMIR)/TSV planning, IO bandwidth feasibility, and system-level architecture selection.

3D-IC Power Network Design and Analysis

The key to success in 3D-IC design is early power integrity planning and analysis. Cadence’s Integrity 3D-IC platform is a high-capacity 3D-IC platform that enables 3D design planning, implementation, and system analysis in a single, unified cockpit. Cadence’s Voltus IC Power Integrity Solution is a comprehensive full chip electromigration, IR drop, and power analysis solution. With its fully distributed architecture and hierarchical analysis capabilities, Voltus provides very fast analysis and has the capacity to handle the largest designs in the industry. Typically, 3D-IC PDN design and analysis is performed in four phases, as shown in Figure 1.

Phase 1 - Perform early power delivery network (PDN) exploration with each fabric’s PDN cascaded in system PI with early circuit models.

Phase 2 – Plan 3D-IC PDNs in Cadence’s Integrity 3D-IC platform, including micro bumps, TSVs, and through dielectric vias (TDVs), power grid synthesis for dies, and early rail analysis and optimization.

Phase 3 – Perform full chip-centric signoff in Voltus with detailed die, interposer, and package models, including chip die models, while keeping some dies flat.

Phase 4 – Perform full system-level signoff with Cadence’s Sigrity SystemPI using detailed extracted package models from Sigrity XtractIM, board models from Sigrity PowerSI or Clarity 3D Solver, interposer models from XtractIM or Voltus, and chip power models from Voltus.

Figure 1. 3D-IC PDN design and analysis phases

3D-IC Chip-Centric Signoff

The integration of Integrity 3D-IC and Voltus enables chip-centric early analysis and signoff. Figure 2 and Figure 3 highlight the chip centric early PI optimization and signoff flows. In early analysis, the on-chip power networks are synthesized, and the micro bumps and TSVs can be placed and optimized. In the signoff stage, all the detailed design data is used for power analysis, and detailed models are extracted and used for package, interposer, and on-die power networks.

Figure 2. Early chip-centric PI analysis and optimization flow

Figure 3. Chip-centric 3D-IC PI signoff

Hierarchical 3D-IC PI Analysis

To improve the capacity and performance of 3D-IC PI analysis, Voltus enables hierarchical analysis using chiplet models. Chiplet models can be reduced chip models in spice format or more accurate xPGV models which are highly accurate proprietary models generated by Voltus. With xPGV models, the hierarchical PI analysis has almost the same accuracy as flat analysis but offers 10X or higher benefit in runtime and memory requirements.

Conclusion

This blog has highlighted the major design trends enabled by advanced 3D packaging and the design challenges arising from these advancements. The design of power delivery networks is one of these major challenges. We have discussed Cadence solutions to overcome this PI challenge. To learn more, view our recent webinar, "Addressing 3D-IC Power Integrity Design Challenges" and visit the Voltus web page.

By default, a dielectric must separate each pair of conductor layers in the cross-section of a design. In rare cases, this does not represent the real, manufactured substrate.

If your design requires you to have conductor layers that are not separated by a dielectric (such as, for half-etch designs), there is a variable that needs to be set in Allegro X APD. You must set this by enabling the variable icp_allow_adjacent_conductors. This entry, and its location in the User Preferences Editor, are shown in the following image.

The Objects on adjacent conductor layers do not electrically connect together, automatically. A via must be used to establish the inter-layer connections.

When enabling this option, it is recommended to exercise caution because excluding dielectric layers from your cross-section can lead to inaccurate calculations, including the calculations for signal integrity and via heights. It is important that your cross-section accurately reflect the finished product to ensure the most accurate results possible. Any dielectric layers present in the manufactured part need to be in the cross-section for accurate extraction, 3D viewing, and so on.

Let us know your comments on the various designs that would require adjacent conductor layers.

Power and Ground rings are exposed rings of metal surrounding a die that supply power/ground to the die and create a low-impedance path for the current flow. These rings ensure stable power distribution and reduce noise. Allegro X Package Designer Plus has a utility called Power/Ground Ring Generator which lets you define and place one or more shapes in the form of a ring around a die.

 To run the PWR/GND Generator Wizard, go to Route > Power/Ground Ring Generator or type "pring wizard" in the APD command window to invoke the Wizard.

This Wizard lets you define and place one or more shapes in the form of a ring around a die. The Power/Ground Ring Wizard creates up to 12 rings (shapes) at a time. If you require more rings, you can run the Power/Ground Ring Wizard as many times as needed. This command displays a wizard in which you can specify:

• The number of rings to be generated
• The creation of the first ring as a die flag (Die flag is the boundary of the die like the power ring.)
  • If you create a die flag and the first ring is the same net as the flag, you can enter a negative distance to overlap the ring and the die flag.
• Multiple options for placement of the rings with respect to:
  • Origination point
  • Distance from the edge of the die
  • Distance from the nearest die pin on each die side
• The reference designator of the die with which the rings will be used
• The distance between rings
• The width of each ring
• The corner types on each ring (arc, chamfer, and right-angle)
• An assigned net name for each ring
• A label for each ring

The rings are basic in nature. For other shape geometries or split rings, choose Shape > Polygon or Shape > Compose/Decompose Shape from the menu in the design window.

Depending on the options selected, the Power/Ground Ring Wizard UI changes, representing how the rings will be created. Verify the Wizard settings to ensure that the rings are created as intended.

1. When the Power/Ground Ring Wizard appears, set the number of rings to 2, accept the other defaults, and click Next. You can set Create first ring as die flag to create a basic die flag.

         2. Define Ring 1 and the net associated with it.

              a) Browse and choose Vss in the Net Names dialog box.

            b) Click OK.

            c) Specify the label as VSS.

            d) Click Next.

             The first ring should appear in your design. It is associated with the proper net; in this case, VSS.

2. For the second ring, choose the net as Vdd and specify the label as VDD.
3. Click Next.
4. Click Finish in the Result Verification screen to complete the process.

The completed rings appear as shown below.

Now, when you click on Power and Ground Die Pin and add wirebonds, you will see that the wirebonds are placed directly on the Power and Ground rings.

When things go wrong with your package design flow, it can sometimes be difficult to understand the cause of the issue. This can be something like a die component is wrongly identified as a BGA, a via stack has an alignment issue, or there are duplicate bondwires. These are just a few examples of issues; there can be many more. When interactive messages and log files do not help determine the problem, the Package Design Integrity Check tool becomes very handy. This feature lets you run integrity checks, which ensures that the database is configured correctly. 

To invoke the command from Allegro X Advanced Package Designer, use the Tools > Package Design Integrity menu. 

Or type package integrity at the Command  prompt. 

The Package Design Integrity Checks dialog box includes all categories and checks currently registered for the currently running product. You can enable all these categories and checks or only the one that you want to run. This utility can fix errors automatically (where possible). Errors and warnings are written to the “package_design_check.log” file.  

The utility can also be extended with your own custom rules based on your specific flows and needs. 

Verisium SimAI App harnesses the power of machine learning technology with the Cadence Xcelium Logic Simulator - the ultimate breakthrough in accelerating verification closure. It builds models from regressions run in the Xcelium simulator, enabling the generation of new regressions with specific targets. The Verisium SimAI app also features cousin bug hunting, a unique capability that uses information from difficult-to-hit failures to expose cousin bugs. With these advanced machine learning techniques, Verisium SimAI offers the potential for a significant boost in productivity, promising an exciting future for our users.

Figure 1: Regression compression and coverage maximization with Verisium SimAI 

What can I do with Verisium SimAI?

You can exercise different use cases with Verisium SimAI as per your requirements. For some users, the goal might be regression compression and improving coverage regain. Coverage maximization and hitting new bins could be another goal. Other users may be interested in exposing hard-to-hit failures, bug hunting for difficult to find issues. Verisium SimAI allows users to take on any of these challenges to achieve the desired results.

Let's go into some more details of these use cases and scenarios where using SimAI can have a big positive impact.

1. Using SimAI for Regression Compression and Coverage Regain

Unlock up to 10X compute savings with SimAI!

Verisium SimAI can be used to compress regressions and regain coverage. This flow involves setting up your regression environment for SimAI, running your random regressions with coverage and randomization data followed by training, and finally, synthesizing and running the SimAI-generated compressed regressions. The synthesized regression may prune tests that do not help meet the goal and add more runs for the most relevant tests, as well as add run-specific constraints. This flow can also be used to target specific areas like areas involving a high code churn or high complexity.

You can check out the details of this flow with illustrative examples in the following Rapid Adoption Kits (RAK) available on the Cadence Learning and Support Portal (Cadence customer credentials needed):

• Using SimAI with vManager (For Regression Compression and Coverage Regain) (RAK) 
• Using SimAI with a Generic Runner (For Regression Compression and Coverage Regain) (RAK)

2. Using SimAI for Coverage Maximization and Targeting coverage holes

Reduce your Functional Coverage Holes by up to 40% using SimAI!

Verisium SimAI can be used for iterative coverage maximization. This is most effective when regressions are largely saturated, and SimAI will explicitly try to hit uncovered bins, which may be hard-to-hit (but not impossible) coverage holes. This is achieved using iterative learning technology where with each iteration, SimAI does some exploration and determines how well it performed. This technique can also be used for bug hunting by using holes as targets of interest.

See more details on the Cadence Learning and Support Portal:

• Using SimAI for Coverage Maximization - vManager flow (RAK) 
• Using SimAI for Coverage Maximization - Generic Runner Flow (RAK)

3. Using SimAI for Bug Hunting

Discover and fix bugs faster using SimAI!

Verisium SimAI has a new bug hunting flow which can be used to target the goal of exposing hard-to-hit failure conditions. This is achieved using an iterative framework and by targeting failures or rare bins. The goal to target failures is best exercised when the overall failure rate is typically low (below 5%). Iterative learning can be used to improve the ability to target specific areas. Use the SimAI bug hunting use case to target rare events, low hit coverage bins, and low hit failure signatures.

See more details on the Cadence Learning and Support Portal:

• Using SimAI for Bug Hunting with vManager (RAK) 
• Using SimAI for Bug Hunting – Generic runner flow (RAK) 

Unlock compute savings, reduce your functional coverage holes, and discover and fix bugs faster with the power of machine learning technology now enabled by Verisium SimAI!

Please keep visiting  https://support.cadence.com/raks to download new RAKs as they become available.

Please note that you will need the Cadence customer credentials to log on to the Cadence Online  Support  https://support.cadence.com/, your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies.

Happy Learning!

The course "Jasper Formal Fundamentals v24.03" introduces formal analysis to those who want to use formal analysis for design or verification. 

To optimally benefit from this course, you must already have sufficient knowledge of the System Verilog assertions to be capable of writing properties for formal verification. Hence, this training provides a module on formal analysis to help cover this essential background. 

In this course, you will learn how to code efficient SVA Properties for formal analysis, understand formal complexity and how to overcome it, and learn the basics of formal coverage.

After completing this course, you will be able to:

• Define reusable, functionally correct SVA properties that are efficient for formal tools. These shall use abstract auxiliary code to simplify descriptions, make code maintenance easier, reduce debug time, and reduce tool-proof runtime.
• Set up, run, and analyze results from formal analysis.
• Identify designs upon which formal is likely to be successful while understanding formal complexity issues and how to identify and overcome them.
• Use a systematic property development process to approach a completely new verification problem.
• Understand the basics of formal coverage.

 The most recently updated release includes new modules on:

• "Basic complexity handling" which discusses the complexity in formal and how to identify and handle them.
• "Complexity reduction methods” which discusses the complexity reduction methods and which is suitable for which type of complexity problem.
• “Coverage in formal” which discusses the basics of coverage in formal verification and how coverage can be used in formal.   

Take this course to learn the basics of formal verification. 

What's Next? 

You can check out the complete training: Jasper Formal Fundamentals. There is a free online version of the training available 24/7 for all customers with a Cadence Learning and Support Portal account. If you are interested in an instructor-led version of the training, please contact Cadence Training. And don't forget to obtain your digital badge after completing the training!

You can also check Jasper University page for more materials on formal analysis and Jasper apps. 

Related Trainings 

Jasper Formal Expert Training Course | Cadence

Verilog Language and Application Training Course | Cadence

SystemVerilog for Design and Verification Training Course | Cadence

SystemVerilog Assertions Training Course | Cadence

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Jasper Formal Property Verification (FPV) App: Basic Usage Demo (Video)

Jasper Formal Methodology playlist

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Verisium Debug, the Cadence unified debug platform, offers a variety of debugging capabilities, including RTL debug, UVM testbench debug, UPF debug, and DMS debug. From IP to SoC level debug, the user can take the benefits of the rich debugging features to reduce the time for debug.

Not only the common and advanced debug features, Verisium Debug also provides Python-based interface API, which enables capabilities allowing users to customize functions with Verisium Debug Python API to access from design, waveform databases and add functions to Verisium Debug’s GUI for visualization purposes. With Verisium Debug’s Python API, users can turn repetitive works into automatic programs or reduce efforts to create in-house utilities with well-established infrastructure from Verisium Debug.

Here is an example of how the user uses Python API to create a customized function. Users can write a Python program to extract signals in a specific design scope and report the values of the extracted signals. From Fig 1., you can understand the procedure of the traversal steps.

1. Import Python library in Verisium Debug package.
2. Setup the database for traversal.
3. Search the scope with the hierarchy information in the design DB.
4. Query the signal list and the values of the signals.
5. Print out the results.

Fig 1. Procedure of Verisium Debug Python Program

The result from the Verisium Debug Python App can be used for post-process design checking or fed into other utilities in the design flow.

The concept is very straightforward. With Verisium Debug and the Python API environment enabled, you can easily query any information that is stored in the databases of Verisium Debug. The result can be outputted in text format, or you can also use the API to display the results back to Verisium Debug’s GUI.

The Verisium Debug Python API is an important capability and resource for Verisium Debug users. To make Verisium Debug Python API easier to access, from Verisium Debug 24.10 release, Verisium Debug introduced the new Verisium Debug Python App Store.

Fig 2. Verisium Debug App Store

The Python App Store includes ready-to-use Python App examples with the availabilities of original source code documents, which help the user to understand how to start writing an app that fits their use case.

Fig 3. Example apps in Verisium Debug App Store

The Verisium Debug Python App Store can also be used by a team as an app management system. App creators can share the developed apps across teams within their companies. The in-house created apps will become easy to manage, and engineers can easily access the apps from the central location, which makes it possible for users to see the updated available Verisium Debug Apps from the Verisium Debug App Store.

Check the following videos for more information about Verisium Debug Python API:

Customize Verisium Debug with Python API

Verisium Debug Customized Apps with Python API

In SoC development, the verification cycle is a crucial phase that ensures products meet their specifications and function correctly. However, the complexity of modern SoC projects, with their constant data flow, multiple validation teams working in parallel, and tight schedules, presents significant challenges. This article explores these challenges and introduces Verisium Manager as a solution that embodies the 'One Tool Fits All' concept. This means that Verisium Manager is designed to handle all aspects of the verification process for SoC development, from planning to coverage analysis to regression testing, thereby addressing the complex needs of SoC verification.

The Hurdles in Traditional Validation Cycles

 A typical validation process involves planning, coverage analysis, and regression testing. This complexity is compounded by using separate tools for each activity, leading to multiple control environments, APIs, and databases, not to mention the array of tool owners. Such fragmentation results in constant data transfer and translation between systems, from the planning tool to the coverage analysis tool and then to the regression testing tool. This continuous movement of data causes delays, system instability, poor user experiences, and, ultimately, a dip in the quality of the validation process.

The use of multiple platforms leads to inefficiency and reduced productivity. What's needed is a unified system that can streamline the workflow, simplify the verification process, and enhance its effectiveness.

Envisioning the Ideal Solution: Verisium Manager

 The cornerstone of an efficient validation cycle is integration and simplicity. The ideal solution is a singular platform that consolidates planning, coverage analysis, and regression management into one smooth, unified process. Verisium Manager emerges as this much-needed solution, encompassing all the functionalities necessary to streamline the validation process. Its comprehensive nature instills confidence in its ability to handle all aspects of the verification cycle. It can be fully customized to address and enforce any validation methodology and can facilitate smooth integration into any customer environment.

Features that stand out in Verisium Manager include: 

• Unified Workflow: It acts as a single cockpit from which all activities are orchestrated, ensuring the validation teams' work is uninterrupted and seamlessly integrated.
• Customization and Integration: Verisium Manager supports customizing test-plan structures and mapping results per project, ensuring a perfect fit for various project requirements. Its ability to smoothly integrate into the project's environment and compute platforms is unparalleled.
• Support for Continuous Updates and Migration: The tool accommodates constant updates to project data and supports the migration of legacy data, ensuring that no historical data is lost in the transition to a new system.

Addressing Project-Specific Needs

 Verisium Manager recognizes diversity in different projects and offers project-specific solutions, including:

 Enforcing Project Test-Plan Structures and Attributes: It supports and enforces each project's unique test-plan structure and mapping guidelines.

• Unified Data Views and Measurements: Verisium Manager promotes a unified view of data across all teams and enforces unified measurements, ensuring consistency and clarity in the validation process.
• Enabling Project-Specific Actions and Integrations: The tool is designed to support project-specific actions directly from its graphical user interface and allows for smooth integration with in-house databases, dashboards, and the project execution stack.

Verisium Manager is the epitome of efficiency in software/hardware validation. Its differentiating features, such as support for customization, unified data view, and comprehensive coverage and regression requirements, make it an indispensable tool for any validation team looking to elevate their workflow.

PHY Interface for the PCI Express (PCIe), SATA, USB, DisplayPort, and USB4 Architectures (PIPE) enables the development of the Physical Layer (PHY) and Media Access Layer (MAC) design separately, providing a standard communication interface between these two components in the system.

In recent years, the PIPE interface specification has incorporated many enhancements to support new features and advancements happening in the supported protocols. As the supported features increase, so does the count of signals on PIPE interface. To address the issue of increasing signal count, the message bus interface was introduced in PIPE 4.4 and utilized for PCIe lane margining at the receiver and elastic buffer depth control.

In PIPE 5.0, all the legacy PIPE signals without critical timing requirements were mapped into message bus registers so that their associated functionality could be accessed via the message bus interface instead of implementing dedicated signals. It was decided that any new feature added in the new version of PIPE specification will be available only via message bus accesses unless they have critical timing requirements that need dedicated signals.

Message Bus Interface

The message bus interface provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. It also enables future PIPE operations to be added without adding additional wires. The use of this interface requires the device to be in a power state with PCLK running.

Control and status bits used for PIPE operations are mapped into 8-bit registers that are hosted in 12-bit address spaces in the PHY and the MAC. The registers are accessed using read-and-write commands driven over the signals M2P_MessageBus[7:0] and P2M_MessageBus[7:0]. These signals are synchronous with the PCLK and are reset with Reset#.

Message Bus Interface Commands

The 4-bit commands are used for accessing the PIPE registers across the message bus. A transaction consists of a command and any associated address and data.

All the following are time multiplexed over the bus from MAC and PHY:

1. Commands (write_uncommitted, write_committed, read, read completion, write_ack)
2. 12-bit address used for all types and read and writes
3. 8-bit data, either read or written

There can be cases where multiple PIPE interface signals can change on the same PCLK. To address such cases, the concept of write_uncommitted and write_committed is introduced.

The uncommitted write should be saved into a write buffer, and its associated data values are updated into the relevant PIPE register at a future time when a write_committed is received, taking effect during the same PCLK cycle. Once a write_committed is sent, no new writes, whether committed or uncommitted, and any read command may be sent until a write_ack is received. Also, it is allowed to send NOP commands between write uncommitted and write committed. 

A simple timing demonstration of message bus:

Message Address Space

MAC and PHY each implement unique 12-bit address spaces. These address spaces will host registers associated with the PIPE operations. MAC accesses PHY registers using M2P_MessageBus[7:0], and PHY accesses the MAC registers using the M2P_MessageBus[7:0].

The MAC and PHY access specific bits in the registers to: initiate operations, Initiate handshakes, and Indicate status.

Each 12-bit address space is divided into four main regions: the receiver address region, the transmitter address region, the common address region, and the vendor-specific address region.

Each register field has an attribute description of either level or 1-cycle assertion. When a level field is written, the value written is maintained by the hardware until the next write to that field or until a reset occurs. When a 1-cycle field is written to assert the value high, the hardware maintains the assertion for only a single cycle and then automatically resets the value to zero on the next cycle.

Cadence has a mature Verification IP solution for the verification of various aspects and topologies of PIPE PHY design. For more details, you may refer to the Simulation VIP for PIPE PHY | Cadence page, or you may send an email to support@cadence.com.

The application of real-time data processing or responsiveness is crucial, such as in high-performance computing, data centers, or applications requiring low-latency data transfers. It enables efficient use of PCIe bandwidth and resources by intelligently managing memory write operations based on system dynamics and workload priorities. By effectively leveraging Deferrable Memory Write [DMWr], Devices can achieve optimized performance and responsiveness, aligning with the evolving demands of modern computing applications.

What Is Deferrable Memory Write?

Deferrable Memory Write (DMWr) ECN introduced this new memory transaction type, which was later officially incorporated in PCIe 5.0 to CXL2.0. This enhanced type of memory transaction is Deferrable Memory Write [DMWr], which flows as another type of existing Read/Write memory transaction; the major difference of this Deferrable Memory Write, where the Requester attempts to write to a given location in Memory Space using the non-posted DMWr TLP Type, it Postponing their completion of memory write transactions to improve overall system efficiency and performance, those memory write operation can be delay or deferred until other priority task complete.

The Deferrable Memory Write (DMWr) requires the Completer to return an acknowledgment to the Requester and provides a mechanism for the recipient to defer (temporarily refuse to service) the Request.

DMWr provides a mechanism for Endpoints and hosts to choose to carry out or defer incoming DMWr Requests. This mechanism can be used by Endpoints and Hosts to simplify the design of flow control, reduce latency, and improve throughput. The Deferrable Memory writes TLP format in Figure A.

(Fig A) Deferrable Memory writes TLP format.

Example Scenario

Here's how the DMWr works with a simplified example: Imagine a system with an endpoint device (Device A) and a host CPU (Device B). Device B wants to write data to Device A's memory, but due to varying reasons such as system bus congestion or prioritization of other transactions, Device A can defer the completion of the memory write request. Just follow these steps:

1. Initiation of Memory Write: Device B initiates a memory write transaction to Device A. This involves sending the memory write request along with the data payload over the PCIe physical layer link.
2. Acknowledgment and Deferral: Upon receiving the memory write request, Device A acknowledges the transaction but may decide to defer its completion. Device A sends an acknowledgment (ACK) back to Device B, indicating it has received the data and intends to complete the write operation but not immediately.
3. Deferred Completion: Device A defers the completion of the memory write operation to a later, more opportune time. This deferral allows Device A to prioritize other transactions or optimize the use of system resources, such as memory bandwidth or processor availability.
4. Completion and Response: At a later point, Device A completes the deferred memory write operation and sends a completion indication back to Device B. This completion typically includes any status updates or additional information related to the transaction.

Usage or Importance of DMWr

Deferrable Memory Write usage provides the improvement in the following aspects:

• Reduced Latency: By deferring less critical memory write operations, more critical transactions can be processed with lower latency, improving overall system responsiveness.
• Improved Efficiency: Optimizes the utilization of system resources such as memory bandwidth and CPU cycles, enhancing the efficiency of data transfers within the PCIe architecture.
• Enhanced Performance: Allows devices to manage and prioritize transactions dynamically, potentially increasing overall system throughput and reducing contention.

Challenges in the Implementation of DMWr Transactions

The implementation of deferrable memory writes (DMWr) introduces several advancements and challenges in terms of usage and verification:

1. Timing and Synchronization: DMWr allows transactions to be deferred, complicating timing requirements or completing them within acceptable timing windows to avoid protocol violations. Ensuring proper synchronization between devices becomes critical to prevent data loss or corruption.
2. Protocol Compliance: Verification must ensure compliance with ECN PCIe 6.0 and CXL specifications regarding when and how DMWr transactions can be initiated and completed.
3. Performance Optimization: While DMWr can improve overall system performance by reducing latency, verifying its impact on system performance and ensuring it meets expected benchmarks is crucial.
4. Error Handling: Handling errors related to deferred transactions adds complexity. Verifying error detection and recovery mechanisms under various scenarios (e.g., timeout during deferral) is essential.

Verification Challenges of DMWr Transactions

The challenges to verifying the DMWr transaction consist of all checks with respect to Function, Timing, Protocol compliance, improvement, Error scenario, and security usage on purpose, as well as Data integrity at the PCIe and CXL.

1. Functional Verification: Verifying the correct implementation of DMWr at both ends of the PCIe link (transmitter and receiver) to ensure proper functionality and adherence to specifications.
2. Timing Verification: Validating timing constraints associated with deferring writes and ensuring transactions are completed within specified windows without violating protocol rules.
3. Protocol Compliance Verification: Checking that DMWr transactions adhere to PCIe and CXL protocol rules, including ordering rules and any restrictions on deferral based on the transaction type.
4. Performance Verification: Assessing the impact of DMWr on overall system performance, including latency reduction and bandwidth utilization, through simulation and testing.
5. Error Scenario Verification: Creating and testing scenarios to verify error handling mechanisms related to DMWr, such as timeouts, retries, and recovery procedures.
6. Security Considerations: Assessing potential security vulnerabilities related to DMWr, such as data integrity risks during deferred transactions or exposure to timing-based attacks.

Major verification challenges and approaches are timing and synchronization verification in the context of implementing deferrable memory writes (DMWr), which is crucial due to the inherent complexities introduced by deferred transactions. Here are the key issues and approaches to address them:

Timing and Synchronization Issues

1. Transaction Completion Timing:
   • Issue: Ensuring deferred transactions are completed within the specified time window without violating protocol timing constraints.
   • Approach: Design an internal timer and checker to model worst-case scenarios where transactions are deferred and verify that they are complete within allowable latency limits. This involves simulating various traffic loads and conditions to assess timing under different scenarios.
2. Ordering and Dependencies:
   • Issue: Verifying that transactions deferred using DMWr maintain the correct ordering and dependencies relative to non-deferred transactions.
   • Approach: Implement test scenarios that include mixed traffic of DMWr and non-DMWr transactions. Verify through simulation or emulation that dependencies and ordering requirements are correctly maintained across the PCIe link.
3. Interrupt Handling and Response Times:
   • Issue: Verify the handling of interrupts and ensure timely responses from devices involved in DMWr transactions.
   • Approach: Implement test cases that simulate interrupt generation during DMWr transactions. Measure and verify the response times to interrupts to ensure they meet system latency requirements.

In conclusion, while deferrable memory writes in PCIe and CXL offer significant performance benefits, their implementation and verification present several challenges related to timing, protocol compliance, performance optimization, and error handling. Addressing these challenges requires rigorous testing and testbench of traffic, advanced verification methodologies, and a thorough understanding of PCIe specifications and also the motivation behind introducing this Deferrable Write is effectively used in the CXL further. Outcomes of Deferrable Memory Write verify that the performance benefits of DMWr (reduced latency, improved throughput) are achieved without compromising timing integrity or violating protocol specifications.

In summary, PCIe and CXL are complex protocols with many verification challenges. You must understand many new Spec changes and consider the robust verification plan for the new features and backward compatible tests impacted by new features. Cadence's PCIe 6.0 Verification IP is fully compliant with the latest PCIe Express 6.0 specifications and provides an effective and efficient way to verify the components interfacing with the PCIe 6.0 interface. Cadence VIP for PCIe 6.0 provides exhaustive verification of PCIe-based IP and SoCs, and we are working with Early Adopter customers to speed up every verification stage.

More Information

• For more info on how Cadence PCIe Verification IP and TripleCheck VIP enable users to confidently verify PCIe 6.0, see our VIP for PCI Express, VIP for Compute Express Link, and TripleCheck for PCI Express
• See the PCI-SIG website for more details on PCIe in general and the different PCI standards.

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2024.1 release is now available for download at Cadence Downloads . For the list of CCRs fixed in this release, see the README.txt file in the installation hierarchy. SIGRITY/SYSANLS 2024.1 Here is a list of some of the key updates in the SIGRITY/SYSANLS 2024.1 release: For more details about these and all the other new and enhanced features introduced in this release , refer to the following document: Sigrity Release Overview and Common Tools What's New . Supported Platforms and Operating Systems Platform and Architecture X86_64 (lnx86) Windows (64 bit) Development OS RHEL 8.4 Windows Server 2022 Supported OS RHEL 8.4 and above RHEL 9 SLES 15 (SP3 and above) Windows 10 Windows 11 Windows Server 2019 Windows Server 2022 Systems Analysis 2024.1 Clarity 3D Solver Clarity 3D Layout Structure Optimization Workflow : A new workflow, Clarity 3D Layout Structure Optimization Workflow, has been added to Clarity 3D Layout. This workflow integrates Allegro PCB Designer with Clarity 3D Layout for high-speed structure optimization. Component Geometry Model Editor : The new Clarity 3D Layout editor lets you set up ports, solder bumps/balls/extrusions, and two-terminal and multi-terminal circuits using a single GUI. Coaxial Open Port Option Added to Port Setup Wizard : The Coaxial Open Port option lets you create ports for each target net pin and reference net pin in Clarity 3D Layout. The nearby reference net pins are then used as a reference for each target net pin, reducing the number of ports needed. In addition, the ports of unused reference net pins are shorted to the ground. Parametric Import Option Added : Two new options, Parametric Import and Default Import , have been added to the Tools – Launch Clarity3DWorkbench menu. The Parametric Import option lets you import the design along with its parameters into Clarity 3D Workbench. The Default Import option lets you ignore the parameters when importing the design into Clarity 3D Workbench. Component Library Added to Generate 3D Components : Clarity 3D Workbench now includes a new component library that lets you use predefined 3D component templates or add existing 3D components to create 3D designs and simulation models. AI-Powered Content Search Capability : Clarity 3D Workbench and Clarity 3D Transient Solver now support an AI-powered capability for searching the content and displaying relevant information. Expression Parser to Handle Undefined Parameters : Clarity 3D Workbench and Clarity 3D Transient Solver support writing expressions or equations containing undefined parameters in the Property window to describe a simulation variable. The improved expression parser automatically detects any undefined parameter in an expression and prompts users to specify their values. This capability lets you define a model or a simulation variable as a function instead of specifying static values. For detailed information, refer to Clarity 3D Layout User Guide and Clarity 3D Workbench User Guide on the Cadence Support portal. Clarity 3D Transient Solver Mesh Processing Improved to Simulate Large Use Cases : Clarity 3D Transient Solver leverages a new meshing algorithm that enhances overall mesh processing, specifically for large designs and use cases. The new algorithm dramatically improves the mesh quality, minimum mesh size, number of mesh key points, total mesh number, and memory usage. Advanced Material Processing Engine : The material processing capability has been enhanced to handle thin outer metal, which previously resulted in open and short issues in some designs. In addition, the material processing engine offers improved mode extraction for particular use cases, including waveguide and coaxial designs. Characteristic Impedance Calculation Improved : The solver engine now uses a new analytical calculation method to calculate the characteristic impedance of coaxial designs with improved accuracy. For detailed information, refer to Clarity 3D Transient Solver User Guide on the Cadence Support portal. Celsius Studio Celsius Interchange Model Introduced : Celsius Studio now supports Celsius Interchange Model generation, which is a 3D model derived from detailed physical designs for multi-physics and multi-scale analysis. This Celsius Interchange Model file ( .cim ) serves as a design information carrier across Celsius Studio tools, enabling a variety of simulation and analysis tasks . Celsius 3DIC Thermal Workflow Improvements : The Thermal Simulation workflows in Celsius 3DIC have been significantly enhanced. Key improvements include: Advanced Power Setup with Transient Power Function and Multi Mode options Enhanced GUI for the Mesh Control and Simulation Control tabs Improved meshing capabilities Celsius Interchange Model ( .cim ) generation Material library support for block and connections Import of Heat Transfer Coefficients (HTCs) from a CFD file Bump creation through the Bump Array Wizard Layer Stackup CSV file generation Celsius 3DIC Warpage and Stress Workflow Enhancements : The Warpage and Stress workflow in Celsius 3DIC has undergone significant improvements, such as: Improved multi-stage warpage simulation flow for 3DIC packaging process Enhanced GUI for the Mesh Control , Simulation Control , and Stress Boundary Conditions tabs Support for large deformations and temperature profiles Bump creation through the Bump Array Wizard New constraint types Enhanced meshing capabilities Geometric Nonlinearity Support in Warpage and Stress Analysis : Large deformation analysis is now supported in warpage and stress studies. This study uses the Total Lagrangian approach to model geometric nonlinearities in simulation, which allows accurate prediction of final deformations. Thermal Network Extraction and Simulation : In the solid extraction flow in Celsius 3D Workbench, you can now import area-based power map files to create terminals. For designs with multiple blocks, this capability allows automatic terminal creation, eliminating the need to manually create and set up 2D sheets individually. Additionally, thermal throttling feature is now supported in Celsius Thermal Network. This makes it ideal for preliminary analyses or when a quick estimation is required. It runs significantly faster than 3D models, allowing for quicker iterations and more efficient decision-making. For detailed information, refer to the Celsius 3DIC User Guide , Celsius Layout User Guide and Celsius 3D Workbench User Guide on the Cadence Support portal. Sigrity 2024.1 Layout Workbench Improved Graphical User Interface : A new option, Use Improved User Interface , has been added in the Themes page of the Options dialog box in the Layout Workbench GUI. In the new GUI, the toolbar icons and menu options have been enhanced and rearranged. For detailed information, refer to Layout Workbench User Guide on the Cadence Support portal. Broadband SPICE Python Script Integration with Command Line for Simulation Tasks : Broadband SPICE lets you run Python scripts directly from the command line for performing simulation and analysis. The new -py and *.py options make it easier to integrate Python scripts with the command-line operations. This update streamlines the process of automating and customizing simulations from the command line, which makes your simulation tasks faster and easier. For detailed information, refer to Broadband SPICE User Guide on the Cadence Support portal. Celsius PowerDC Block Power Assignment (BPA) File Format Support : PowerDC now supports the BPA file format. Similar to the Pin Location (PLOC) file, the BPA file is a current assignment file that defines the total current of a power grid cell, which is then equally distributed across the power pins within the cell. This provides better control over the power distribution. Ability to Run Multiple IR Drop Cases Sequentially : You can now select multiple result sinks from the Current-Limited IR Drop flow and run IR Drop analysis for them sequentially. PowerDC automatically runs the simulations in sequence after you select multiple result sinks. This saves time by automating the process. Enhanced Support for Mixed Conversion Devices : PowerDC now supports mixing different conversion devices, such as switching regulators and linear regulators within a single DC-DC/LDO instance. This enhancement offers added flexibility by letting you configure each instance in your design according to your specific needs. For detailed information, refer to PowerDC User Guide on the Cadence Support portal. PowerSI Monte Carlo Method Added : A new option, Monte Carlo Method, has been added in the Optimality dialog box. This option lets you create multiple random samples to depict variations in the input parameters and assess the output. Channel Check Optimization Added : The S-Parameter Assessment workflow in PowerSI now supports Channel Check Optimization . It uses the AI-driven Multidisciplinary Analysis and Optimization (MDAO) technology that lets you optimize your design quickly and efficiently with no accuracy loss. For detailed information, refer to PowerSI User Guide on the Cadence Support portal. SPEEDEM Multi-threaded Matrix Solver Support Added : The Enable Multi-threaded Matrix Solver check box has been added that lets you accelerate the simulation speed for high-performance computing. This check box provides two options, Automatic and Always, to include the -lhpc4 or -lhpc5 parameter, respectively, in the SPEEDEM Simulator (SPDSIM) before running the simulation. For detailed information, refer to the SPEEDEM User Guide on the Cadence Support portal. XtractIM Options to Skip or Calculate Special DC-R Simulation Results : The Skip DC_R of Each Path and Only DC_R of Each Path options have been added to the Setup menu. Skip DC_R of Each Path : This option lets you skip the calculation of the DC-R result during the simulation. Other results, such as SPICE T-model , RL_C of Each Path , Coupling of Each Path , etc., are still calculated. Only DC_R of Each Path : This option lets you calculate the DC-R result only during the simulation. Other results, such as SPICE T-model , RL_C of Each Path , Coupling of Each Path , etc., are not calculated. Color Assignment for Pin Matching : The MCP Auto Connection window includes the Display Color Editor , which lets you assign a color for pin matching. It helps you easily identify the matching pins in the left and right sections of the MCP Auto Connection window . Ability to Save Simulations Individually : The Save each simulation individually check box has been added to the Tools - Options - Edit Options - Simulation (Basic) - General form. Select this check box and run the simulation to generate a simulation results folder containing files and logs with a timestamp for each simulation. Reuse of SPD File Settings : The XtractIM setup check box lets you import an existing package setup to reuse the configurations and settings from one .spd file to another. For detailed information, refer to XtractIM User Guide on the Cadence Support portal. Documentation Enhancements Cloud-Based Help System Upgraded The cloud-based help system, Doc Assistant, has been upgraded to version 24.10, which contains several new features and enhancements over the previous 2.03 version. Sigrity Release Team Please send your questions and feedback to sigrity_rmt@cadence.com .

Wild River Technology (WRT), the leading supplier of signal integrity measurement and optimization test fixtures for high-speed channels at data rates of up to 224G, has announced the availability of a new advanced channel modeling solution that helps achieve extreme signal integrity design to 70GHz. Read the press release. The CMP-70 program continues the industry-first simulation-to-measurement collaboration with Cadence that was initially established with the CMP-50. Significant resources were dedicated to the development of the CMP-70 by Cadence and WRT over almost three years. The CMP-70 will be on display at DesignCon 2025 , January 28-30, in Cadence booth 827 to benchmark the Cadence Clarity 3D Solver . “I am not a fan of hype-based programs that simply get attention,” remarked Alfred P. Neves, WRT’s co-founder and chief technical officer. “Both Cadence and Wild River brought substantial skills to the table in this project as we continued our industry-first simulation-to-measurement collaboration. The result is a proven, robust and accurate platform that brings extreme signal integrity to 70GHz designs. This application package has also been instrumental in demonstrating the robust 3D EM simulation capability of the Cadence Clarity solver.” “We’re delighted to continue the joint development and validation program with WRT that started with the CMP-50,” said Gary Lytle, product management director at Cadence. “The skilled and experienced signal integrity technologists that both companies bring to the program results in a superior signal integrity solution for our mutual customers.” CMP-70 Solution Features The solution is available both in a standard configuration and as a custom solution for customer-specific stackups and fabrication. The primary target application is to support a 3D EM solver analysis modeling versus the time- and frequency-domain measurement methodologies. The solution features include: The CMP-70 platform, assembled and 100% TDR NIST traceable tested, with custom stands Material Identification overview web-based meeting including anisotropic 3D material identification A cross-section PCB report and structures for using as-fabricated geometries Measured S-parameters, pre-tested for quality (passivity/causality and resampled for time domain simulations) A host of novel crosstalk structures suited for 112G HD level project analysis PCB layout design files (NDA required) An EDA starter library including loss models with industry-first accurate surface roughness models Comprehensive training available for 3D EM analysis – correspondence, material ID in X-Y and Z axis for a host of EDA tools Industry-First Hausdorff Technique The WRT application package also includes an industry-first modified Hausdorff (MHD) technique , included as MATLAB code. This algorithmic approach provides an accurate way to compare two sets of measurements in multi-dimensional space to determine how well they match. The technique is used to compare the results simulated by the Clarity solver with those measured on the CMP-70 platform. The methodology and initial results are shown in the figure below, where the figure of merit (FOM) is calculated from 10, 35, and finally to 50GHz. The MHD algorithm requires a MATLAB license, but WRT also accommodates customer data as another option, where WRT provides the comparison between measured and simulated data. Additional Resources If you are attending DesignCon 2025 , be sure to stop by Cadence booth 827 to see WRT’s CMP-70 advanced channel modeling solution in action with the Clarity 3D Solver. Check out our on-demand webinar, " Validating Clarity 3D Solver Accuracy Through Measurement Correlation ." Learn more about the CMP-70 solution and the Clarity 3D Solver . For more information about Cadence’s full suite of integrated multiphysics simulation solutions, download our Multiphysics System Analysis Solutions Portfolio .

Allegro X System Capture offers a complete ecosystem for library development. This post introduces the latest DE-HDL Library Development using System Capture course in which you learn how to create different library objects. As a librarian, you often work with numerous libraries. Your tasks include creating or modifying symbols for libraries. To use Allegro X System Capture to create a library, you can follow the steps in the following flowchart: Let’s go through each step in detail. Setting the CDS_SITE Variable Before you start library development for a new project, set the CDS_SITE system environment variable. This step is required to access libraries and other configuration files. Creating a Project in Allegro X System Capture The next step is to create a project in Allegro X System Capture. Adding a Library to the Project Symbol development consists of creating symbol graphics, electrical data, and properties used by different tools in the PCB design flow. To add a library to a project, first create a library in the Libraries pane of the Project e xplorer. Creating Library Symbols The library development process supports the creation of various types of symbols. Creating a Symbol with Multiple Views You can generate multiple views of the same symbol using the Duplicate command. For example, a discrete symbol, such as a resistor, can have multiple views, as shown in the following image: Creating a Split Symbol For advanced designs, you often need to create library symbols and break them into multiple sections to support the design process. When a symbol shows all the logical pins in the physical package, it is called a single-section or flat symbol. Many large ICs have several pins and the symbols need to fit on a single schematic page. One workaround is to use vector pin names on a symbol to reduce its size, although manufacturers prefer schematics that show each pin. You can divide these high-pin count devices into smaller pieces, where each piece is a separate version of the part. Such parts are referred to as split parts or multi-section symbols. For multi-section symbols, you can create two types of split parts—symmetrical and asymmetrical. Symmetrical Split Symbols A symmetrical split symbol has only one symbol graphic, which holds two or more identical logic symbols, each with its own unique physical pin numbers. You can create a symmetrical split symbol using the Duplicate Section icon in the canvas window. Each symbol section contains the same set of pins but different pin numbers, as shown in the following image: Asymmetrical Split Symbols An asymmetrical split symbol is a symbol whose physical package contains one or more unique schematic symbols. You can create an asymmetrical split symbol by clicking the New Section icon in the canvas window. Asymmetrical symbols have a unique set of logical pins, as shown in the following image: Creating Symbols Using the Spreadsheet Interface To simplify the development of large symbols, Allegro X System Capture has a Spreadsheet Interface . You can copy from a spreadsheet into the interface. This saves time and helps minimize errors introduced by manual entry. In conclusion, the DE-HDL library development using Allegro X System Capture course involves several critical steps and supports various symbol creation techniques. This course helps librarians create and modify symbols effortlessly and deepens their understanding of library development within Allegro X System Capture. To learn more about this topic, enroll in the DE-HDL Library Development using Allegro X System Capture course on the Cadence Support portal . Click the training byte link now or visit Cadence Support and search for training bytes under Video Library. If you find the post useful and want to delve deeper into training details, enroll in the following online training course for lab instructions and a downloadable design: DE-HDL Library Development using Allegro X System Capture (Online). You can become Cadence Certified once you complete the course. Cadence Training Services now offers free Digital Badges for all popular online training courses. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can add the digital badge to your email signature or any social media channels, such as Facebook or LinkedIn, to highlight your expertise. To find out more, see the blog post Take a Cadence Masterclass and Get a Badge . You might also be interested in the training Learning Map that guides you through recommended course flows as well as tool experience and knowledge-level training modules. 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As a verification engineer, you’re surely looking for ways to automate the debugging process. Have you developed your own scripts to ease specific debugging steps that tools don’t offer? Working with scripts locally and manually is challenging—so is reusing and organizing them. What if there was a way to create your own app with the required functionality and register it with the tool? The answer to that question is “Yes!” The Verisium Debug Python App Store lets you instantly add additional features and capabilities to your Verisium Debug Application using Python Apps that interact with Verisium Debug via the Python API. Join me, Principal Education Application Engineer Bhairava Prasad, for this Training Webinar and discover the Verisium Debug Python App Store. The app store allows you to search for existing apps, learn about them, install or uninstall them, and even customize existing apps. Date and Time Wednesday, November 20, 2024 07:00 PST San Jose / 10:00 EST New York / 15:00 GMT London / 16:00 CET Munich / 17:00 IST Jerusalem / 20:30 IST Bangalore / 23:00 CST Beijing REGISTER To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System*. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details. A quick reminder: If you haven’t received a registration confirmation within one hour of registering, please check your spam folder and ensure your pop-up blockers are off and cookies are enabled. For issues with registration or other inquiries, reach out to eur_training_webinars@cadence.com . Like this topic? Take this opportunity and register for the free online course related to this webinar topic: Verisium Debug Training To view our complete training offerings, visit the Cadence Training website Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe . Hungry for Training? Choose the Cadence Training Menu that’s right for you. Related Courses Xcelium Simulator Training Course | Cadence Related Blogs Unveiling the Capabilities of Verisium Manager for Optimized Operations - Verification - Cadence Blogs - Cadence Community Verisium SimAI: SoC Verification with Unprecedented Coverage Maximization - Corporate News - Cadence Blogs - Cadence Community Verisium SimAI: Maximizing Coverage, Minimizing Bugs, Unlocking Peak Throughput - Verification - Cadence Blogs - Cadence Community Related Training Bytes Introducing Verisium Debug (Video) (cadence.com) Introduction to UVM Debug of Verisium Debug (Video) (cadence.com) Verisium Debug Customized Apps with Python API Please see course learning maps a visual representation of courses and course relationships. Regional course catalogs may be viewed here . *If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help .

Hearing is one of the most essential senses for engaging with the world. It enables us to converse, appreciate music, and remain alert to our surroundings. Hearing loss is a prevalent issue affecting millions of individuals globally and disconnecting them from a world where sound is vital to others and the environment. The World Health Organization (WHO) reports that over 5% of the global population requires hearing rehabilitation, a striking statistic highlighting this issue's pervasive nature. Technology has transformed audiology, evolving from simple ear trumpets to sophisticated modern hearing aids. This advancement began with the invention of the transistor, paving the way for devices that are fully wearable inside or behind the ear. Although hearing aids have been available for many years, historically, access to these critical devices has been insufficient, resulting in numerous individuals lacking the necessary support. However, recent advances in hearing aid technology promise improved acoustic experiences, employing modern techniques like binaural processing and neural networks. These innovations demand sophisticated architecture to balance high memory needs with low power consumption in a user-friendly design. Cadence is at the forefront of this technological evolution, offering tools and IP solutions that enhance the accessibility, efficiency, and impact of hearing aids, paving the way for a more inclusive future. This blog explores how Cadence's advanced DSPs are transforming hearing aid design and making them more accessible, efficient, and impactful. Hearing Aids: A Testament to Human Ingenuity The transition from analo g to digital technology in the late 20th century further transformed hearing aids, offering superior sound quality, customization, and the ability to connect to various electronic devices, thus enhancing the user experience markedly. Today's hearing aids are highly effective, versatile, and nearly invisible, a significant advancement from early attempts to address hearing loss. They also feature advanced noise cancellation and connectivity options, allowing users to integrate seamlessly into the digital world. This progression not only highlights the industry's commitment to improving user experience and accessibility but also offers a glimpse into a future where hearing loss is no longer a barrier. Challenges Despite advancements and sophistication, there are several challenges related to hearing aid design and adoption. Users demand smaller, more discreet devices that don't sacrifice performance. While the shift towards sleeker designs is aesthetically pleasing, it introduces substantial complexities in product design. Designers face the challenges of integrating essential components, such as batteries and peripherals, into increasingly compact spaces. Power consumption remains a critical concern, as these devices must remain operational throughout the day. Leveraging neural networks to enhance the signal-to-noise ratio (SNR) for better quality demands additional memory capacity. Consequently, there is a pressing need for flexible, low-power architectures that incorporate all necessary memory and peripherals without compromising the device’s compact size. Adopting AI for adjusting hearing aid volume to fit an individual's specific auditory requirements is a significant challenge and demands more memory and effort. Besides this, reliability and cost are significant challenges for manufacturers. Cadence's Role in Transforming Hearing Aids In hearing aid development, the capacity to evaluate the energy efficiency of SoCs across different frequencies in real time is crucial. These applications demand cohesive, energy-efficient solutions that can uphold high performance. The Cadence Tensilica HiFi and Fusion F1 DSP family emphasize minimal power usage while providing robust performance, ideally suited for a wide range of audio and voice applications. The Cadence Tensilica HiFi DSP family, a high-performance audio technology with AI acceleration and advanced DSP capability, offers feature-rich audio, speech, and imaging for wearables, automotive, home entertainment, digital assistants, and ASR. The Tensilica HiFi DSP family accelerates innovation with its comprehensive instruction set and supports fixed- and floating-point data types. Simplifying software development, it offers C/C++ programming, an auto-vectorizing compiler, and a rich DSP software library through the Cadence Tensilica Xplorer development environment. With the flexibility to customize and enhance performance through additional instructions and better I/O bandwidth, the Tensilica HiFi and Fusion DSP families offer a robust, low-energy audio solution compatible across an expansive software ecosystem for various applications and devices. Conclusion Technological advancements are driving hearing aid evolution; the future of hearing aids lies in further miniaturization and functionality enhancement. Cadence's ongoing innovations aim to improve signal processing and noise reduction, even in challenging environments. The integration of neural networks promises more apparent sound transmission and greater adaptability. Cadence is working on improving how these devices process signals and reduce noise and has initiated a collaborative venture with distinguished entities like GlobalFoundries (GF), Hoerzentrum Oldenburg gGmbH, and Leibniz University Hannover. This collaboration has borne fruit in the form of the industry's first binaural hearing aid system-on-chip (SoC) prototype, the Smart Hearing Aid Processor ( SmartHeAP ). Learn More Cadence, GlobalFoundries, Hoerzentrum Oldenburg and Leibniz University Hannover Collaborate to Advance Hearing Aid Technology Cadence Extends Battery Life and Improves User Experience for Next-Generation Hearables, Wearables and Always-On Devices Advancing the Future of Hearing Aids with Cadence Bluetooth LE Audio, Hearing Aids, and Mindtree

Celebrated for their unparalleled engineering expertise and pioneering mindset, McLaren stands at the forefront of innovation. Theirs is a story of engineering excellence, a symphony of speed driven by the relentless pursuit of aerodynamic perfection. In 2022, Cadence was named an Official Technology Partner of the McLaren Formula 1 Team. The multi-year partnership between McLaren and Cadence has helped redefine the boundaries of what’s possible in Formula 1 aerodynamics. Shaving off a fraction of a second per lap can make all the difference in a podium finish, and track conditions bring layers of complexity to the design process. That’s where Cadence steps in with Fidelity CFD Software. The Cadence Fidelity CFD software is a comprehensive suite of computational fluid dynamics (CFD) solutions. Access to this solution allows the McLaren F1 team to accelerate their CFD workflow, enabling them to assess designs faster and more precisely. It also allows them to investigate airflows and tackle design projects that require advanced compute power and precision. With Fidelity Flow’s solver capabilities and Python-driven automation, Cadence’s CFD software aids the advancement of aerodynamic simulations that go into McLaren’s F1 cars. With a customized, high-quality, multi-block meshing strategy and optimized workflow, Fidelity CFD makes design exploration more automated, thereby helping establish a strong foundation for McLaren’s future success on the track. Lando Norris, F1 driver for McLaren, said, “As a driver, I saw the impact of every decision made in the design room in every simulation run. The work on aerodynamics directly translates to the confidence I have on track, the grip in every turn, and the speed on every straight. This partnership, this technology, is what will give us the edge. It's not just about battling opponents; it's about mastering the airflow around the car in every driving condition on every track.” If you’re interested in learning more about the importance of CFD in McLaren’s racing success, be sure to attend our upcoming webinar, “CFD and Experimental Aerodynamics in McLaren F1 Engineering.” Christian Schramm, McLaren’s director of advanced projects, and Cadence’s Benjamin Leroy will be the main speakers for the event. Register today to secure your spot! For more insights on the Formula 1 car design process, take a look at the case study, “ McLaren Formula 1 Car Aerodynamics Simulation with Cadence Fidelity CFD Software .” Learn more about how McLaren and Cadence are engineering success . “Designed with Cadence” is a series of videos that showcases creative products and technologies that are accelerating industry innovation using Cadence tools and solutions. For more Designed with Cadence videos, check out the Cadence website and YouTube channel .

Peripheral Component Interconnect Express (PCIe) is a high-speed interface standard widely used for connecting processors, memory, and peripherals. With the increasing reliance on PCIe to handle sensitive data and critical high-speed data transfer, ensuring data integrity and encryption during verification is the most essential goal. As we know, in the field of verification, randomization is a key technique that drives robust PCIe verification. It introduces unpredictability to simulate real-world conditions and uncover hidden bugs from the design. This blog examines the significance of randomization in PCIe IDE verification, focusing on how it ensures data integrity and encryption reliability, while also highlighting the unique challenges it presents. For more relevant details and understanding on PCIe IDE you can refer to Introducing PCIe's Integrity and Data Encryption Feature . The Importance of Data Integrity and Data Encryption in PCIe Devices Data Integrity : Ensures that the transmitted data arrives unchanged from source to destination. Even minor corruption in data packets can compromise system reliability, making integrity a critical aspect of PCIe verification. Data Encryption : Protects sensitive data from unauthorized access during transmission. Encryption in PCIe follows a standard to secure information while operating at high speeds. Maintaining both data integrity and data encryption at PCIe’s high-speed data transfer rate of 64GT/s in PCIe 6.0 and 128GT/s in PCIe 7.0 is essential for all end point devices. However, validating these mechanisms requires comprehensive testing and verification methodologies, which is where randomization plays a very crucial role. You can refer to Why IDE Security Technology for PCIe and CXL? for more details on this. Randomization in PCIe Verification Randomization refers to the generation of test scenarios with unpredictable inputs and conditions to expose corner cases. In PCIe verification, this technique helps us to ensure that all possible behaviors are tested, including rare or unexpected situations that could cause data corruption or encryption failures that may cause serious hindrances later. So, for PCIe IDE verification, we are considering the randomization that helps us verify behavior more efficiently. Randomization for Data Integrity Verification Here are some approaches of randomized verifications that mimic real-world traffic conditions, uncovering subtle integrity issues that might not surface in normal verification methods. 1. Randomized Packet Injection: This technique randomized data packets and injected into the communication stream between devices. Here we Inject random, malformed, or out-of-sequence packets into the PCIe link and mix valid and invalid IDE-encrypted packets to check the system’s ability to detect and reject unauthorized or invalid packets. Checking if encryption/decryption occurs correctly across packets. On verifying, we check if the system logs proper errors or alerts when encountering invalid packets. It ensures coverage of different data paths and robust protocol check. This technique helps assess the resilience of the IDE feature in PCIe in below terms: (i) Data corruption: Detecting if the system can maintain data integrity. (ii) Encryption failures: Testing the robustness of the encryption under random data injection. (iii) Packet ordering errors: Ensuring reordering does not affect data delivery. 2. Random Errors and Fault Injection: It involves simulating random bit flips, PCRC errors, or protocol violations to help validate the robustness of error detection and correction mechanisms of PCIe. These techniques help assess how well the PCIe IDE implementation: (i) Detects and responds to unexpected errors. (ii) Maintains secure communication under stress. (iii) Follows the PCIe error recovery and reporting mechanisms (AER – Advanced Error Reporting). (iv) Ensures encryption and decryption states stay synchronized across endpoints. 3. Traffic Pattern Randomization: Randomizing the sequence, size, and timing of data packets helps test how the device maintains data integrity under heavy, unpredictable traffic loads. Randomization for Data Encryption Verification Encryption adds complexity to verification, as encrypted data streams are not readable for traditional checks. Randomization becomes essential to test how encryption behaves under different scenarios. Randomization in data encryption verification ensures that vulnerabilities, such as key reuse or predictable patterns, are identified and mitigated. 1. Random Encryption Keys and Payloads: Randomly varying keys and payloads help validate the correctness of encryption without hardcoding assumptions. This ensures that encryption logic behaves correctly across all possible inputs. 2. Randomized Initialization Vectors (IVs): Many encryption protocols require a unique IV for each transaction. Randomized IVs ensure that encryption does not repeat patterns. To understand the IDE Key management flow, we can follow the below diagram that illustrates a detailed example key programming flow using the IDE_KM protocol. Figure 1: IDE_KM Example As Figure 1 shows, the functionality of the IDE_KM protocol involves Start of IDE_KM Session, Device Capability Discovery, Key Request from the Host, Key Programming to PCIe Device, and Key Acknowledgment. First, the Host starts the IDE_KM session by detecting the presence of the PCIe devices; if the device supports the IDE protocol, the system continues with the key programming process. Then a query occurs to discover the device’s encryption capabilities; it ensures whether the device supports dynamic key updates or static keys. Then the host sends a request to the Key Management Entity to obtain a key suitable for the devices. Once the key is obtained, the host programs the key into the IDE Controller on the PCIe endpoint. Both the host and the device now share the same key to encrypt and authenticate traffic. The device acknowledges that it has received and successfully installed the encryption key and the acknowledgment message is sent back to the host. Once both the host and the PCIe endpoint are configured with the key, a secure communication channel is established. From this point, all data transmitted over the PCIe link is encrypted to maintain confidentiality and integrity. IDE_KM plays a crucial role in distributing keys in a secure manner and maintaining encryption and integrity for PCIe transactions. This key programming flow ensures that a secure communication channel is established between the host and the PCIe device. Hence, the Randomized key approach ensures that the encryption does not repeat patterns. 3. Randomization PHE: Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0. PHE validation using a variety of traffic; incorporating randomization in APIs provided for validating PHE feature can add more robust Encryption to the data. Partial Header Encryption in Integrity and Data Encryption for PCIe has more detailed information on this. Figure 2: High-Level Flow for Partial Header Encryption 4. Randomization on IDE Address Association Register values: IDE Address Association Register 1/2/3 are supposed to be configured considering the memory address range of IDE partner ports. The fields of IDE address registers are split multiple values such as Memory Base Lower, Memory Limit Lower, Memory Base Upper, and Memory Limit Upper. IDE implementation can have multiple register blocks considering addresses with 32 or 64, different registers sizes, 0-255 selective streams, 0-15 address blocks, etc. This Randomization verification can help verify all the corner cases. Please refer to Figure 2. Figure 3: IDE Address Association Register 5. Random Faults During Encryption: Injecting random faults (e.g., dropped packets or timing mismatches) ensures the system can handle disruptions and prevent data leakage. Challenges of IDE Randomization and its Solution Randomization introduces a vast number of scenarios, making it computationally intensive to simulate every possibility. Constrained randomization limits random inputs to valid ranges while still covering edge cases. Again, using coverage-driven verification to ensure critical scenarios are tested without excessive redundancy. Verifying encrypted data with random inputs increases complexity. Encryption masks data, making it hard to verify outputs without compromising security. Here we can implement various IDE checks on the IDE callback to analyze encrypted traffic without decrypting it. Randomization can trigger unexpected failures, which are often difficult to reproduce. By using seed-based randomization, a specific seed generates a repeatable random sequence. This helps in reproducing and analyzing the behavior more precisely. Conclusion Randomization is a powerful technique in PCIe verification, ensuring robust validation of both data integrity and data encryption. It helps us to uncover subtle bugs and edge cases that a non-randomized testing might miss. In Cadence PCIe VIP, we support full-fledged IDE Verification with rigorous randomized verification that ensures data integrity. Robust and reliable encryption mechanisms ensure secure and efficient data communication. However, randomization also brings various challenges, and to overcome them we adopt a combination of constrained randomization, seed-based testing, and coverage-driven verification. As PCIe continues to evolve with higher speeds and focuses on high security demands, our Cadence PCIe VIP ensures it is in line with industry demand and verify high-performance systems that safeguard data in real-world environments with excellence. For more information, you can refer to Verification of Integrity and Data Encryption(IDE) for PCIe Devices and Industry's First Adopted VIP for PCIe 7.0 . More Information: For more info on how Cadence PCIe Verification IP and TripleCheck VIP enables users to confidently verify IDE, see our VIP for PCI Express , VIP for Compute Express Link for and TripleCheck for PCI Express For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website .

Hello,

I'm reading the Design specification for IP6514E.

We will use the DAC mode.

It would seem to be very simple but I don't see any code sequence, i.e.

  1.Write 03(Basic Read) to this register

  2, Write start adress to this register

  3. Write "execute" to this register

  4. Read the data from this register

Thanks,

Stefan

Hello,

I am new in formal verification and I have a concept question about how to verify an I2C Slave block.

I think the response should be valid for any serial interface which needs to receive information for several clocks before making an action.

The the protocol description is the following: 

I have a serial clock (SCL), Serial Data Input (SDI) and Serial Data Output (SDO), all are ports of the I2C Slave block.

The protocol looks like this:

The first byte which is received by the slave consists in 7bits of sensor address and the 8th bit is the command 0/1 Write/Read.

After the first 8 bits, the slave sends an ACK (SDO = 1 for 1 clock) if the sensor address is correct.

Lets consider only this case, where I want to verify that the slave responds with an ACK if the sensor address is correct.

The only solution I found so far was to use the internal buffer from the block which saves the received bits during 8 clocks. The signal is called shift_s.

I also needed to use internal chip state (state_s) and an internal counter (shift_count_s).

Instead of doing an direct check of the SDO(sdo_o) depending on SDI (sdi_d_i), I used the internal shift_s register.

My question is if my approach is the correct one or there is a possibility to write the verification at a blackbox level.

Below you have the 2 properties: first checks connection from SDI to internal buffer, the second checks the connection between internal buffer and output.

property prop_i2c_sdi_store;
  @(posedge sclk_n_i)
  $past(i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR)
    |-> i2c_bl.shift_s == byte'({ $past(i2c_bl.shift_s), $past(sdi_d_i)});
endproperty
APF_I2C_CHECK_SDI_STORE: assert property(prop_i2c_sdi_store);

property prop_i2c_sensor_addr(sens_addr_sel, sens_addr);
@(posedge sclk_n_i) (i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR) && (i2c_addr_i == sens_addr_sel) && (i2c_bl.shift_count_s == 7)
  ##1 (i2c_bl.shift_s inside {sens_addr, sens_addr+1}) |-> sdo_o;
endproperty
APF_I2C_CHECK_SENSOR_ADDR0: assert property(prop_i2c_sensor_addr(0, `I2C_SENSOR_ADDRESS_A0));
APF_I2C_CHECK_SENSOR_ADDR1: assert property(prop_i2c_sensor_addr(1, `I2C_SENSOR_ADDRESS_A1));
APF_I2C_CHECK_SENSOR_ADDR2: assert property(prop_i2c_sensor_addr(2, `I2C_SENSOR_ADDRESS_A2));
APF_I2C_CHECK_SENSOR_ADDR3: assert property(prop_i2c_sensor_addr(3, `I2C_SENSOR_ADDRESS_A3));

PS: i2c_addr_i is address selection for the slave (there are 4 configurable sensor addresses, but this is not important for the case).

Thank you!

This is the 19th installment of The Rationalist, my column for the Times of India.

A friend of mine was very impressed by the interview Narendra Modi granted last week to Akshay Kumar. ‘Such a charming man, such great work ethic,’ he gushed. ‘He is the kind of uncle I would want my kids to have.’ And then, in the same breath, he asked, ‘How can such a good man be such a bad prime minister?”

I don’t want to be uncharitable and suggest that Modi’s image is entirely manufactured, so let’s take the interview at face value. Let’s also grant Modi his claims about the purity of his neeyat (intentions), and reframe the question this way: when it comes to public policy, why do good intentions often lead to bad outcomes? To attempt an answer, I’ll refer to a story a friend of mine, who knows Modi well, once told me about him. 

Modi was chilling with his friends at home more than a decade ago, and told them an incident from his childhood. His mother was ill once, and the young Narendra was tending to her. The heat was enervating, so the boy went to the switchboard to switch on the fan. But there was no electricity. My friend said that as he told this story, Modi’s eyes filled with tears. Even after all these years, he was moved by the memory.

My friend used this story to make the point that Modi’s vision of the world is experiential. If he experiences something, he understands it. When he became chief minister of Gujarat, he made it his stated mission to get reliable electricity to every part of Gujarat. No doubt this was shaped by the time he flicked a switch as a young boy and the fan did not budge. Similarly, he has given importance to things like roads and cleanliness, since he would have experienced the impact of those as a young man.

My term for him, inspired by Rajat Kapoor’s 2014 film, is ‘the ankhon dekhi prime minister’. At one level, this is a good thing. He sees a problem and works for the rest of his life to solve it. But what of things he cannot experience?

The economy is a complex beast, as is society itself, and beyond a certain level, you need to grasp abstract concepts to understand how the world works. You cannot experience them. For example, spontaneous order, or the idea that society and markets, like language, cannot be centrally directed or planned. Or the positive-sum nature of things, which is the engine of our prosperity: the idea that every transaction is a win-win game, and that for one person to win, another does not have to lose. Or, indeed, respect for individual rights and free speech.

One understands abstract concepts by reading about them, understanding them, applying them to the real world. Modi is not known to be a reader, and this is not his fault. Given his background, it is a near-miracle that he has made it this far. He wasn’t born into a home with a reading culture, and did not have either the resources or the time when he was young to devote to reading. The only way he could learn about the world, thus, was by experiencing it.

There are two lessons here, one for Modi himself and others in his position, and another for everyone.

The lesson in this for Modi is a lesson for anyone who rises to such an important position, even if he is the smartest person in the world. That lesson is to have humility about the bounds of your knowledge, and to surround yourself with experts who can advise you well. Be driven by values and not confidence in your own knowledge. Gather intellectual giants around you, and stand on their shoulders.

Modi did not do this in the case of demonetisation, which he carried out against the advice of every expert he consulted. We all know the damage it caused to the economy.

The other learning from this is for all of us. How do we make sense of the world? By connecting dots. An ankhon-dekhi approach will get us very few dots, and our view of the world will be blurred and incomplete. The best way to gather more dots is reading. The more we read, the better we understand the world, and the better the decisions we take. When we can experience a thousand lives through books, why restrict ourselves to one?

A good man with noble intentions can make bad decisions with horrible consequences. The only way to hedge against this is by staying humble and reading more. So when you finish reading this piece, think of an unread book that you’d like to read today – and read it!

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 24th installment of The Rationalist, my column for the Times of India.

Back in the last decade, I was a cricket journalist for a few years. Then, around 12 years ago, I quit. I was jaded as hell. Every game seemed like déjà vu, nothing new, just another round on the treadmill. Although I would remember her fondly, I thought me and cricket were done.

And then I fell in love again. Cricket has changed in the last few years in glorious ways. There have been new ways of thinking about the game. There have been new ways of playing the game. Every season, new kinds of drama form, new nuances spring up into sight. This is true even of what had once seemed the dullest form of the game, one-day cricket. We are entering into a brave new world, and the team leading us there is England. No matter what happens in the World Cup final today – a single game involves a huge amount of luck – this England side are extraordinary. They are the bridge between eras, leading us into a Golden Age of Cricket.

I know that sounds hyperbolic, so let me stun you further by saying that I give the IPL credit for this. And now, having woken up you up with such a jolt on this lovely Sunday morning, let me explain.

Twenty20 cricket changed the game in two fundamental ways. Both ended up changing one-day cricket. The first was strategy.

When the first T20 games took place, teams applied an ODI template to innings-building: pinch-hit, build, slog. But this was not an optimal approach. In ODIs, teams have 11 players over 50 overs. In T20s, they have 11 players over 20 overs. The equation between resources and constraints is different. This means that the cost of a wicket goes down, and the cost of a dot ball goes up. Critically, it means that the value of aggression rises. A team need not follow the ODI template. In some instances, attacking for all 20 overs – or as I call it, ‘frontloading’ – may be optimal.

West Indies won the T20 World Cup in 2016 by doing just this, and England played similarly. And some sides began to realise was that they had been underestimating the value of aggression in one-day cricket as well.

The second fundamental way in which T20 cricket changed cricket was in terms of skills. The IPL and other leagues brought big money into the game. This changed incentives for budding cricketers. Relatively few people break into Test or ODI cricket, and play for their countries. A much wider pool can aspire to play T20 cricket – which also provides much more money. So it makes sense to spend the hundreds of hours you are in the nets honing T20 skills rather than Test match skills. Go to any nets practice, and you will find many more kids practising innovative aggressive strokes than playing the forward defensive.

As a result, batsmen today have a wider array of attacking strokes than earlier generations. Because every run counts more in T20 cricket, the standard of fielding has also shot up. And bowlers have also reacted to this by expanding their arsenal of tricks. Everyone has had to lift their game.

In one-day cricket, thus, two things have happened. One, there is better strategic understanding about the value of aggression. Two, batsmen are better equipped to act on the aggressive imperative. The game has continued to evolve.

Bowlers have reacted to this with greater aggression on their part, and this ongoing dialogue has been fascinating. The cricket writer Gideon Haigh once told me on my podcast that the 2015 World Cup featured a battle between T20 batting and Test match bowling.

This England team is the high watermark so far. Their aggression does not come from slogging. They bat with a combination of intent and skills that allows them to coast at 6-an-over, without needing to take too many risks. In normal conditions, thus, they can coast to 300 – any hitting they do beyond that is the bonus that takes them to 350 or 400. It’s a whole new level, illustrated by the fact that at one point a few days ago, they had seven consecutive scores of 300 to their name. Look at their scores over the last few years, in fact, and it is clear that this is the greatest batting side in the history of one-day cricket – by a margin.

There have been stumbles in this World Cup, but in the bigger picture, those are outliers. If England have a bad day in the final and New Zealand play their A-game, England might even lose today. But if Captain Morgan’s men play their A-game, they will coast to victory. New Zealand does not have those gears. No other team in the world does – for now.

But one day, they will all have to learn to play like this.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This blog describes an efficient way to name the histories saved by the simulation runs in Virtuoso ADE Assembler.(read more)

Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera. (read more)

Have you ever wanted to write a DRC rule deck to check for space or width constraints on polygons? Or have you wondered how the multiple lines of an LVS rule deck extract and conduct a comparison between the schematic and layout? Maybe you've been curious about the role of rule deck writers in creating high-quality designs ready for tape-out.

If any of these questions interest you, there is good news: the latest version (v23.1) of the Physical Verification Rules Writer (PVLRW) course is designed to teach you rule deck writing. This free 16-hour online course includes audio and labs designed to make your learning experience comfortable and flexible. Whether you are new to the concept or an experienced CAD/PDK engineer, the course is structured to enhance your rule deck writing skills.

The PVLRW course covers six core modules: Layer Processing, DRC Rules, Layout Extraction, ERC and LVS Rules, Schematic Netlisting, and Coloring Rules. There are also three optional appendix sections. Each module explains relevant rules with syntax, concepts, graphics, examples, and case studies.

This course is based on tool versions PEGASUS231 and Virtuoso Studio IC231.

Pegasus Input and Output

Pegasus is a cloud-ready physical verification signoff solution that enables engineers to support faster delivery of advanced-node integrated circuits (ICs) to market.

Pegasus requires input data in the form of layout geometry, schematic netlists, and rules that direct the tool operation. The rules fall into two categories: those that describe the fabrication process and those that control the job-specific operation.

Pegasus provides log and report files, netlists, databases, and error databases as output.

Overview of Pegasus Rule File

The rule decks written in Physical Verification Language (PVL) work for the Cadence PV signoff tools Pegasus and PVS (Physical Verification System).   

The PVL rules are placed in a file that gets selected in a run from the GUI or the command line, as the user directs. PVL rules may be on separate lines within the file and can also be contained in named rule blocks.

Each line of code starts with a PVL rule that uses prefix type notation. It consists of a keyword followed by options, input layer or variable names, and output layer or variable names.

A rule block has the format of the keyword rule, followed by a rule name you wish to give it, followed by an opening curly brace. You enter the rules you wish to perform, followed by a closing curly brace on the last separate line.

  Sample Rule deck with individual lines of code and rule blocks.

DRC Rules

The first step in a typical Pegasus flow is a Design Rule Check (DRC), which verifies that layout geometries conform to the minimum width, spacing, and other fabrication process rules required by an IC foundry. Each foundry specifies its own process-dependent rules that must be met by the layout design.

There are three types of DRC rules: layer definition rules, layer derivation rules, and DRC design check rules. Layer definition rules identify the layers contained in the input layout database, and layer derivation rules derive additional layers from the original input layers, allowing the tool to test the design against specific foundry requirements using the design check rules.

A sample DRC Rule deck

A layout view displaying the DRC violations

LVS Rules

The Pegasus Layout Versus Schematic (LVS) tool compares the layout netlist with the schematic netlist to check for discrepancies.

There are two essential LVS rule sets: LVS extraction rules and comparison rules. LVS extraction rules help extract drawn devices and connectivity information from the input layout geometry data and outputs into a layout netlist. The LVS extraction rule set also includes the layer definition, derivation, extraction, connectivity, and net listing rules.

LVS comparison rules are associated with comparing the extracted layout netlist to a schematic netlist.

A sample LVS Rule deck. 

TCL, Macros, and Conditional commands

Tcl is supported and used in various Pegasus functionalities, such as Pegasus rule files and Pegasus configurator. Macros are functional templates that are defined once and can be used multiple times in a rule file. Conditional Commands are used to process or skip specific commands in the rule file.

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• On the Cadence Support portal, select Register Now and provide the requested information on the Registration page.
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• If you need help with registration, contact support@cadence.com.

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Related Resources

About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis. Subscribe to receive email notifications about our latest Custom IC Design blog posts.

Hi 

I am looking into chamfering the edge of PCB for Board edge connectors. I have performed fillet command earlier but new to chamfering.

Below is the description :

As seen above, the PCB edge are chamfered in thickness as well as at the corners.

Using OrCAD PCB hotfix S023.

I'd like to be able to edit a footprint for a part in my design without needing to find the footprint filepath and directly open that file in PCB Editor. I see that I can view footprints from Capture, and that doing so shows me the footprint path, but I can't find any way to launch the editor. Is there any way to go directly from a part in a Capture schematic or a placed part in a PCB Editor board design to editing that part's footprint?

Hello, I was wondering how can I create variable fields in the layout.

To start, I have a template for some type of designs, and I would like that one of the texts on the silkscreen changes accordingly to an external variable, like the folder name, or a text file in the same folder.

I was thinking something similar to a page frame that changes the date automatically. How can I generate that type of fields?

Dear all,

I defined two design variables in ADE Assembler, say V1 and V2, that define the voltage 1 and voltage 2 of a "vpulse" voltage source in my schematic.

Then, I define V1 = 1.0, and V2 = 2.0, run a transient simulation, and everything is as expexcted. The source provides pulses between 1.0 V and 2.0 V.

Next, I set V1 = 1.0:0.5:1.5, thereby creating a parametric sweep with 1.0 V and 1.5 V for V1. I keep V2 at 2.0 V. Then the simulation fails, and all I get is "netl err" in my Output Expressions and an error message that the results directory does not exist and nothing can be plotted: This is reasonable, as the results directory is deleted on starting a new simulation, and as there is no simulation result, none of my output expressions can be plotted.

WARNING (OCN-6040): The specified directory does not exist, or the directory does not contain valid PSF results.
        Ensure that the path to the directory is correct and the directory has a logFile and PSF result files.
WARNING (ADE-1065): No simulation results are available.
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.

Normally, this kind of para,metric sweep is not a problem, I have done this many times before. There must be something special in THIS PARTICULAR test bench or simulator setup. The trouble is, I don't get any useful error messages.

Does anyone know what might be the problem here OR where to find useful information to investigate further (log files stored somewhere)? Thank you!

Regards,

Volker

P.S. Using Corners instead does not help either. Running it through all values by hand works, though.

I have tried replicating the setup described in a previous post (here), with the proposed solution.

The MDL measurements return a value of 0 for all exported result but the first.

Using Viva I can actually see the correct value for each contribution.

I am using :
- Spectre 23.1.0.538.isr10
- Viva IC23.1-64b.ISR8.40

What should I do differently?

Thanks!

**** test.measure ****

Measurement Name   :  noi_test
Analysis Type      :  noise
noi_total             =  6.9282e-06
r1_flicker            =  0
r1_thermal            =  0
r1_total              =  0
r2_flicker            =  0
r2_thermal            =  0
r2_total              =  0

For reasons too complicated to go into here, I need to generate the code for a veriloga view from a outside the normal Verilog-A editor. I would start with an "empty" veriloga view generated from the symbol in the normal way so I get the port order correct, then use external code to provide "guts" of the veriloga view by overwriting the generated code.

My understanding is that and code changes made external to the normal flow do not get picked up by Cadence - the Verilog-A code gets read at design time, not at netlist time. Would simply forcing a check and save of the veriloga view after the code is modified fix that problem? Or is there an easier way to incorporate externally generated Verilog-A code?

I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics.

Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va),  mod2 (inside an external file mod2.va),  and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module.

At the bottom of the module I use "`include mod1.va", "`mod2.va", etc.

When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning:

Warning from spectre during AHDL compile.
WARNING (VACOMP-1047): The Verilog-A file contains more than one module
definition. ADE can process only one module per Verilog-A file. Put
only one module in each Verilog-A file so that ADE can identify pin
names, directions, and hierarchy within each separate module.

Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored?

Hello,


I would like to use the simulation software xrun/simvision that comes with XCELIUM. We are currently using classroom licenses and want to disable all ip addresses on the student pcs except the license server ip. We want to make sure that students cannot copy confidential data from the Cadence tools.


Problem:

When I launch the xrun simulation while all ip addresses are blocked, it starts but the performance is very slow. The GUI starts after 5 minutes and the simulation is ready after 10 minutes. The interesting thing is that when I enable all blocked ip addresses, everything works at a reasonable speed.

Terminal Output (execution without internet connection):

xrun -gui design.vhd

waiting for SimVision/Verisium Debug to connect...


Is there a way to run the simulation tools without an Internet connection? Or can you give me the ip addresses that are used by the simulation tools so that I can enable only those specific ips?


Regards,

Max

Hello,
I'm trying to characterize a full adder that use transmission gate.
Unfortunately, the power calculation are wrong for the cell are always negative.
Is there any method or commands that can can help in power calculation or add the power consumption by the input pins to the power calculation ?
Another question, Is liberate support the characterization or transmission gate cells as standard cells or I should use liberate AMS for these type of cells ?
Thanks in advance,
Tareq 

Hello everyone, 
I have a testbench for generating s2p files from a SP simulation that was working until few months ago. Today I have reopened (w/o making changes that I am aware of) and I get the error as shown below:

first I show the testbench settings:

notice how the s2p generation is disabled: the field "file" is left blank

in the corner I defined some parameters, "filename" is the word that is suppose to generate the name for the s2p. 

where the two variables are defined as follows

And now the output log:

spectre.out file gives the following error:


When clicking on the error message at "9", the input.scs file opens up and the line 9 gets highlighted in green



now, so far I understood that the problem seem to be related tom the "pathcds" variable, but I really don't understand what the error message here means, since I don't see any error in the input.scs file

by the way - if for instance I define the variable "filename" as shown below, then I get no errors:

thanks
Tommaso

Hi,

reading Verilog®-A Language Reference I found this description of ddt function I don't understand:

Use the time derivative operator to calculate the time derivative of an argument.

ddt( input [ , abstol | nature ] )

input is a dynamic expression.

abstol is a constant specifying the absolute tolerance that applies to the output of the ddt operator. Set abstol at the largest signal level that you consider negligible.

nature is a nature from which the absolute tolerance is to be derived.

Can anyone explain how abstol and nature are defined? how using them? an example would be really appreciated.

Thanks

Andrea

Hello,

I am aware of command script .svcf file that saves signals and loads them in while opening Simvision.

I am wondering, if there is a way for saving signals while we are in an interactive session and loading them next time when we open Simvision interactively.

Any ideas on how to do this?

Thank you in advance.

Swetha. C

I would like to send an update about a vmanager regression status x days after the regression has been run. In the current environment, the vmanager regression is creating a new filepath for logs automatically based on regression name/date, so I can't use a cron job to gather logs, as the log location is not known. 

I tried to use the pre session script to launch a detached shell script that would run after a delay, but when the pre_script runs, it waits until everything is completed before finishing and moving on to starting the regression.

Here is the test pre_script I am using:

#!/bin/sh

echo "pre_script start"

delay_script "FIRST" 1
nohup delay_script "SECOND" 30 & disown
delay_script "THIRD" 1

echo "pre_script end"
exit 0

Here is the test delay_script I am using:

#!/bin/sh

echo "Starting $1"

sleep $2

echo "Ending $1"

Here is the script output when run from terminal. After the "pre_script end", I get control back.

Here is the script output when run from vmanager. There is no "nohup", and the pre_session phase doesn't complete until all the delay scripts complete.

My question is, is there a better way to achieve my goal here? (The goal being to run a script from the vmanager log directory automatically x days after the regression). I think I could use the pre_script to send directory information for an auxiliary cron job to pick up, but I would prefer to not have to have extra cronjobs needed for this.

I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code covered grade, block covered grade, statement covered grade, expression covered grade, toggle covered grade.

As I dont know the difference I started to read the IMC user guide and came to know there are 3 things we come across while doing a code coverage local, covered, average

From my understanding

local - child instances metrics doesnt reach the parent level. For example, we have an instance Q and its sub instances like Q.a, Q.b. Block Local grade of Q can be 100% even when its instances Q.a and Q.b a block local grades isnt at 100%.

In the attached image there is formula 

The key difference between average and covered is the weights.

Average : Mathematically taking the above scenario where Q.a, and Q.b has 10 blocks each. Q.a has covered 8 blocks and q.b has covered 2 blocks. Now if we take the normal average it should be total covered/ totatl number = 8+2/10+10 yielding 50%. But when we add weights saying Q.a is 70% and Q.b is 30% the new number would be (8*0.7+2*0.3) / (10*0.7+10*0.3) resulting 62%. Because of the weights we see 12% bump.

Covered: there is no role of weights.

Among these 3 metrics i've changed my default view to this in the image to get more realistic picture when i do analyze metrics. Do you guys agree with the approach?

Hi,
I want to parameterized width and length of a NMOS, but it ignore it and I face this error:
*WARNING* Value input must be a number - setting back to previous value.

Does anybody know how I can fix this issue?
Thanks

Hello,

First, I had something working that broke in the past few versions that I've been meaning to get working again. There was some setting I recall in the GUI that allowed me to have inputs be placed in the waveform viewer with yellow traces, and output signals with orange traces to match the name colors. How can I set this to happen in the .simvisionrc file?

Second, I would like to add something to my .simvisionrc file to go through foreach signal and depending on key locations based on the signal's Path.Name (mainly the model and design areas) such that if the path contains "mon", then to auto-set the trace and name colors to something such as cyan. I'd like to have loops for various key areas of the design to color-code the signals.

Third, I am interested if there is a possibility of coloring names/traces foregound colors to based on which position they are in the waveform viewer to make banding, ideally such that every three (or whatever) are one color (or a color mutation, adding some gray to signals colorized by the auto-coloring mentioned already, etc) that allows for the signal names/traces to be colorized along with the built-in optional black/gray background banding.

Thanks in advance

Hi, I am uploading a register class, which can be used for modeling hardware registers. I am uploading the source code and examples on how to run it. I also have a user guide which has all the APIs listed and explained. The user guide is ARV.pdf in the attached tar file. I have named the class ARV, which stands for Architect's Register View. It has got very good randomization and coverage features. Users have told me that its better than RAL. You can download it from http://verisilica.info/ARV.php
. There is a limit of 750KB in this cadence website. The ARV file is 4MB. That is why, I am uploading it at this site. I have a big pdf documentation and a doxygen documentation there. That is the reason for the bigger file size. The password to open the ZIP file is ovm_arv. I hope, everyone will use these classes.

Please contact me for any help.
Regards ANil

As noted in white papers, posts on the Team Specman Blog, and the Specman documentation, IntelliGen is a totally new stimulus generator than the original "Pgen" and, as a result, there is some amount of effort needed to migrate an existing verification environment to fully leverage the power of IntelliGen.  One of the main steps in migrating code is running the linters on your code and adressing the issues highlighted. 

Included below is a simple utility you can include in your environment that allows you to collect some valuable statistics about your code base to allow you to better gauge the amount of work that might be required to migrate from Pgen to IntelliGen.  The ICFS statistics reported are of particular benefit as the utility not only identifies the approximate number of ICFSs in the environment, it also breaks the total number down according to generation contexts (structs/units and gen-on-the-fly statements) allowing you to better focus your migration efforts. 

IMPORTANT: Sometimes a given environment can trigger a large number of IntelliGen linting messages right off the bat.  Don't let this freak you out!  This does not mean that migration will be a long effort as quite often some slight changes to an environment remove a large number of identified issues.  I recently encountered a situation where a simple change to three locations in the environment, removed 500+ ICFSs!

The methods included in the utility can be used to report information on the following:
- Number of e modules
- Number of lines in the environment (including blanks and comments)
- Number and type of IntelliGen Guidelines linting messages
- Number of Inconsistently Connected Field Sets (ICFSs)
- Number of ICFS contexts and how many ICFSs per context
- Number of soft..select overlays found in the envioronment
- Number of Laces identified in the environment

To use the code below, simply load it before/after loading e-code and then
you can execute any of the following methods:

- sys.print_file_stats()             : prints # of lines and files
- sys.print_constraint_stats()   : prints # of constraints in the environment
- sys.print_guideline_stats()    : prints # of each type of linting message
- sys.print_icfs_stats()            : prints # of ICFSs, contexts and #ICFS/context
- sys.print_soft_select_stats() : prints # of soft select overlay issues
- sys.print_lace_stats()           : *Only works for SPMNv6.2s4 and later* prints # of laces identified in the environment

Each of the above calls to methods produces it's own log files (stored in the current working directory) containing relevant information for more detailed analysis.
- file_stats_log.elog : Output of "show modules" command
- constraint_log.elog : Output of the "show constraint" command
- guidelines_log.elog : Output of "gen lint -g" (with notification set to MAX_INT in order to get all warnings)
- icfs_log.elog       : Output of "gen lint -i" command
- soft_select_log.elog: Output of the "gen lint -s" command
- lace_log.elog       : Output of the "show lace" command

Happy generating!

Corey Goss

Hello All,

Following is the einstein's puzzle solved by cadence Incisive92  (solved in less than 3 seconds -> FAST!!!!!!)

Thanks,

Vinay Honnavara

Verification engineer at Keyu Tech

vinayh@keyutech.com

 // Author: Vinay Honnavara

// Einstein formulated this problem : he said that only 2% in the world can solve this problem
// There are 5 different parameters each with 5 different attributes
// The following is the problem

// -> In a street there are five houses, painted five different colors (RED, GREEN, BLUE, YELLOW, WHITE)

// -> In each house lives a person of different nationality (GERMAN, NORWEGIAN, SWEDEN, DANISH, BRITAIN)

// -> These five homeowners each drink a different kind of beverage (TEA, WATER, MILK, COFFEE, BEER),

// -> smoke different brand of cigar (DUNHILL, PRINCE, BLUE MASTER, BLENDS, PALL MALL)

// -> and keep a different pet (BIRD, CATS, DOGS, FISH, HORSES)


///////////////////////////////////////////////////////////////////////////////////////
// *************** Einstein's riddle is: Who owns the fish? ***************************
///////////////////////////////////////////////////////////////////////////////////////

/*
Necessary clues:

1. The British man lives in a red house.
2. The Swedish man keeps dogs as pets.
3. The Danish man drinks tea.
4. The Green house is next to, and on the left of the White house.
5. The owner of the Green house drinks coffee.
6. The person who smokes Pall Mall rears birds.
7. The owner of the Yellow house smokes Dunhill.
8. The man living in the center house drinks milk.
9. The Norwegian lives in the first house.
10. The man who smokes Blends lives next to the one who keeps cats.
11. The man who keeps horses lives next to the man who smokes Dunhill.
12. The man who smokes Blue Master drinks beer.
13. The German smokes Prince.
14. The Norwegian lives next to the blue house.
15. The Blends smoker lives next to the one who drinks water.
*/




typedef enum bit [2:0]  {red, green, blue, yellow, white} house_color_type;
typedef enum bit [2:0]  {german, norwegian, brit, dane, swede} nationality_type;
typedef enum bit [2:0]  {coffee, milk, water, beer, tea} beverage_type;
typedef enum bit [2:0]  {dunhill, prince, blue_master, blends, pall_mall} cigar_type;
typedef enum bit [2:0]  {birds, cats, fish, dogs, horses} pet_type;




class Einstein_problem;

    rand house_color_type house_color[5];
    rand nationality_type nationality[5];
    rand beverage_type beverage[5];
    rand cigar_type cigar[5];
    rand pet_type pet[5];
        rand int arr[5];
    
    constraint einstein_riddle_solver {
    
        
    
        foreach (house_color[i])
            foreach (house_color[j])
               if (i != j)
                house_color[i] != house_color[j];
        foreach (nationality[i])
            foreach (nationality[j])
               if (i != j)
                nationality[i] != nationality[j];
        foreach (beverage[i])
            foreach (beverage[j])
               if (i != j)
                beverage[i] != beverage[j];
        foreach (cigar[i])
            foreach (cigar[j])
               if (i != j)
                cigar[i] != cigar[j];
        foreach (pet[i])
            foreach (pet[j])
               if (i != j)
                pet[i] != pet[j];
    
    
        //1) The British man lives in a red house.
        foreach(nationality[i])
                (nationality[i] == brit) -> (house_color[i] == red);
                
        
        //2) The Swedish man keeps dogs as pets.
        foreach(nationality[i])
                (nationality[i] == swede) -> (pet[i] == dogs);
                
                
        //3) The Danish man drinks tea.        
        foreach(nationality[i])
                (nationality[i] == dane) -> (beverage[i] == tea);
        
        
        //4) The Green house is next to, and on the left of the White house.
        foreach(house_color[i])        
                 if (i<4)
                    (house_color[i] == green) -> (house_color[i+1] == white);
        
        
        //5) The owner of the Green house drinks coffee.
        foreach(house_color[i])
                (house_color[i] == green) -> (beverage[i] == coffee);
                
        
        //6) The person who smokes Pall Mall rears birds.
        foreach(cigar[i])
                (cigar[i] == pall_mall) -> (pet[i] == birds);
        
        
        //7) The owner of the Yellow house smokes Dunhill.
        foreach(house_color[i])
                (house_color[i] == yellow) -> (cigar[i] == dunhill);
        
        
        //8) The man living in the center house drinks milk.
        foreach(house_color[i])
                if (i==2) // i==2 implies the center house (0,1,2,3,4) 2 is the center
                    beverage[i] == milk;
        
        
        
        //9) The Norwegian lives in the first house.
        foreach(nationality[i])        
                if (i==0) // i==0 is the first house
                    nationality[i] == norwegian;
        
        
        
        //10) The man who smokes Blends lives next to the one who keeps cats.
        foreach(cigar[i])        
                if (i==0) // if the man who smokes blends lives in the first house then the person with cats will be in the second
                    (cigar[i] == blends) -> (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i>0 && i<4) // if the man is not at the ends he can be on either side
                    (cigar[i] == blends) -> (pet[i-1] == cats) || (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i==4) // if the man is at the last
                    (cigar[i] == blends) -> (pet[i-1] == cats);
        
        foreach(cigar[i])        
                if (i==4)
                    (pet[i] == cats) -> (cigar[i-1] == blends);
        
        
        //11) The man who keeps horses lives next to the man who smokes Dunhill.
        foreach(pet[i])
                if (i==0) // similar to the last case
                    (pet[i] == horses) -> (cigar[i+1] == dunhill);
        
        foreach(pet[i])        
                if (i>0 & i<4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill) || (cigar[i+1] == dunhill);
                    
        foreach(pet[i])        
                if (i==4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill);
                    


        //12) The man who smokes Blue Master drinks beer.
        foreach(cigar[i])
                (cigar[i] == blue_master) -> (beverage[i] == beer);
        
        
        //13) The German smokes Prince.
        foreach(nationality[i])        
                (nationality[i] == german) -> (cigar[i] == prince);
        

        //14) The Norwegian lives next to the blue house.
        foreach(nationality[i])
                if (i==0)
                    (nationality[i] == norwegian) -> (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i>0 & i<4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue) || (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i==4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue);
        

        //15) The Blends smoker lives next to the one who drinks water.            
        foreach(cigar[i])            
                if (i==0)
                    (cigar[i] == blends) -> (beverage[i+1] == water);
        
        foreach(cigar[i])        
                if (i>0 & i<4)
                    (cigar[i] == blends) -> (beverage[i-1] == water) || (beverage[i+1] == water);
                    
        foreach(cigar[i])        
                if (i==4)
                    (cigar[i] == blends) -> (beverage[i-1] == water);
        
    } // end of the constraint block
    


    // display all the attributes
    task display ;
        foreach (house_color[i])
            begin
                $display("HOUSE : %s",house_color[i].name());
            end
        foreach (nationality[i])
            begin
                $display("NATIONALITY : %s",nationality[i].name());
            end
        foreach (beverage[i])
            begin
                $display("BEVERAGE : %s",beverage[i].name());
            end
        foreach (cigar[i])
            begin
                $display("CIGAR: %s",cigar[i].name());
            end
        foreach (pet[i])
            begin
                $display("PET : %s",pet[i].name());
            end
        foreach (pet[i])
            if (pet[i] == fish)
                $display("THE ANSWER TO THE RIDDLE : The %s has %s ", nationality[i].name(), pet[i].name());
    
    endtask // end display
    
    
endclass




program main ;

    initial
        begin
            Einstein_problem ep;
            ep = new();
            if(!ep.randomize())
                $display("ERROR");
            ep.display();
        end
endprogram // end of main

        

Hi all, I've trained a device model with the approach of an artificial neural network, and it shows well fit. 

May I know how to transfer the trained model to Verilog-A, so that, we can use this model to do circuit simulation?

And I've searched for some lectures that provide the Verilog-A code in the appendix, but I'm freshman in the field of Verilog-A, 

could anyone tell me each statement? such as

real hlayer-w[0:(NI*NNHL)-1   

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