According to an embodiment, there is provided a sheet processing apparatus includes a stacking unit that stacks a sheet conveyed thereto; a first alignment unit that aligns the sheet or a bundle of sheets stacked in the stacking unit in a sheet conveying direction; a second alignment unit that aligns the sheet or the bundle of sheets stacked in the stacking unit in a direction orthogonal to the sheet conveying direction; a pressing unit that presses the bundle of sheets at an end portion thereof on a predetermined one side; and a control unit that causes at least one of the first and second alignment units to execute an alignment operation during a press operation of the sheet or the bundle of sheets performed by the pressing unit.

A sheet processing device includes a clamp configured to clamp an edge portion of a sheet, the edge portion being on a side of an edge parallel to a direction in which the sheet has been conveyed; a first processing unit configured to perform a first process on the sheet at the side of the edge, the first processing unit being disposed at a first position; a second processing unit configured to perform a second process on the sheet at the side of the edge, the second processing unit being disposed at a second position that is different from the first position in a vertical direction; and a moving unit configured to move the clamp from the first position to the second position or vice versa so that the clamp moves on a loop passing through the first position and the second position.

A creasing device forms a crease in a to-be-folded portion of a sheet. The creasing device includes a sheet-information reading unit that reads any one of sheet information and binding information; a determining unit that determines a surface, on which the crease is to be formed, of the sheet according to the one of the sheet information and the binding information read by the sheet-information reading unit; and a creasing unit that forms the crease on the surface determined by the determining unit.

A sheet binding apparatus which forms concavity and the convexity on a sheet bundle including a plurality of sheets in a thickness direction so as to bind the sheet bundle, the sheet binding apparatus includes: a pair of concave-convex members, each of which has concave-convex portion in the thickness direction of the sheet bundle and which forms the concavity and the convexity on the sheet bundle in the thickness direction while niping the sheet bundle therebetween; wherein in the pair of concave-convex members, one of the concave-convex members has a greater difference in height of the concave-convex portion than that of the other concave-convex member which engages with the above-described concave-convex member.

Disclosed is an image forming system including: the relay apparatus; the image forming device which is connected to the first communication control unit of the relay apparatus and which acquires the sheet interval information of the downstream post-processing device through the first communication system; and the second post-processing device which is connected to the second communication control unit of the relay apparatus, the second post-processing device being compliant with the second communication system.

Disclosed is an image forming system including: an image forming device to notify a downstream post-processing device of sheet information relating to a sheet on which an image is formed, before the sheet is discharged, and to notify the downstream post-processing device of set separation information indicating a final sheet of each set of document in synchronization with the sheet information relating to the final sheet of each set in case that a plurality of sets of document are printed, the image forming device being compliant with a first communication system; a post-processing device which is connected to a downstream of the image forming device and is compliant with a second communication system which is different from the first communication system; and the relay apparatus which is connected to the image forming device through the first communication system and is connected to the post-processing device through the second communication system.

A sheet processing apparatus includes a pair of squeezing members having a projection and a recess to engage each other, to squeeze a sheet bundle inserted therebetween in a direction of thickness of the sheet bundle, and a pressure applying unit to apply pressing force to the squeezing members to squeeze and bind the sheet bundle. The pressing force generated between the squeezing members by the pressure applying unit increases in strength as a relative distance between the squeezing members decreases.

In the invention, for a first sheet, regardless of the sheet size (width), a lateral registration detector is moved in a direction towards an edge face of the sheet from a home position to detect the edge face of the sheet. With lateral deviation in the sheet position corrected, punching is performed by a puncher. For the second and subsequent sheets, the lateral registration detector is moved in advance to near the edge face of the sheet with reference to the detected position of the sheet edge of the first sheet, and the edge face is detected at a given timing. With lateral deviation in the sheet position corrected, punching is performed by the puncher.

In a provided apparatus, an upper roller to be engaged with a sheet upper face and a lower roller to be engaged with a sheet lower face are arranged at a sheet discharging port in a manner capable of being pressure-contacted and being separated, the upper roller is formed with a large-diameter soft roll face and a small-diameter hard roll face, and a pressurization force of roller lifting-lowering means with which the upper roller is pressure-contacted to and is separated from the lower roller is switched to be high or low.

An image forming system includes the following elements. An image forming apparatus forms images on plural sheets sequentially transported with a spacing therebetween. A sheet transport apparatus includes a transport section which receives and transports the plural sheets farther downstream. The sheet transport apparatus supplies a different type of sheet from a different-type-of-sheet supply device, inserts it into the spacing, and transports the sheets. The sheet transport apparatus includes the following elements. A transport information obtaining unit obtains information concerning transporting of sheets. A different-type-of-sheet stop unit supplies the different type of sheet, on the basis of the information concerning transporting of sheets, and stops the different type of sheet at a position before the transport section. A different-type-of-sheet supply information output unit outputs information concerning the supply of the different type of sheet, the information being obtained regarding a standby state of the different type of sheet.

In a sheet storing apparatus of the present invention, a tailing end supporting member which temporarily supports a tailing end of a dropping sheet bundle is arranged between a discharging port of a processing tray to discharge the sheet bundle and the upmost sheet on a stack tray as being movable between an operating position above a sheet placement face and a waiting position outside the stack tray.

A sheet processing apparatus including a stacking tray that stacks sheets, a conveying member that conveys a sheet to the stacking tray and discharges the sheet bundle from the stacking tray, wherein the conveying member includes a conveying roller and a conveying belt stretched by a plurality of stretch rollers, and a sheet processor that performs predetermined processing to the sheet bundle. When the conveying member conveys the sheet to the stacking tray, a part of the conveying belt that is not wound on the stretch roller contacts the conveying roller by moving the conveying belt as such a nip for conveying the sheet is formed. When the conveying member discharges the sheet bundle from the stacking tray, a part of the conveying belt that is wound on the stretch roller contacts the conveying roller by moving the conveying belt so that a nip for conveying the sheet is formed.

A sheet processing apparatus includes: a folding processing unit that folds a sheet by reversely rotating a second conveying member in a condition in which the sheet is held by a first and the second conveying members; a calculating unit that calculates an amount of deflection of the sheet held by the first and second conveying members from timings at which the sheet is detected by first and second detecting units disposed upstream of the first conveying member and downstream of the second conveying member and a distance between disposed positions of the first and second detecting units; and a control unit that sets, from the calculated amount of deflection of the sheet, an amount of conveyance for the first conveying member in a direction opposite to a sheet conveying direction in a condition in which the sheet is held by the first and second conveying members.

To provide a sheet storage apparatus for enabling sheets that are carried out of an image formation apparatus or the like on the upstream side to be loaded and stored in a predetermined position with a correct posture neatly at high speed, a sheet discharge roller and a reverse roller spaced a distance are disposed in a sheet discharge outlet and a tray, a kick member is provided to be swingable in a vertical direction passing a sheet discharge path of a sheet discharged from the sheet discharge outlet, and a posture of the kick member is controlled by shift means. The shift means controls the kick member among a waiting posture retracted upward from the sheet discharge path, an engagement posture for imposing a load on the sheet to engage, and an actuation posture dropping onto the tray together with the sheet.

The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

The stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package.

Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.

Described herein are methods and systems for providing corrective maintenance using global knowledge sharing. A method to provide corrective maintenance with a CM system includes performing a query to generate a ranking of fixable causes based on factors (e.g., symptoms, configuration, test). The ranking may be determined based on a fixable cause percent match with the factors. The ranking of fixable causes may be associated with one or more solutions for each fixable cause. The ranking can be updated based on performing tests or solutions.

A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).

In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

A method for manufacturing a light-emitting device includes a step of forming an etching resistant protection layer on a substrate provided with an organic planarizing layer, a step of forming a plurality of electrodes on the etching resistant protection layer, a step of forming an organic compound layer on the substrate provided with the plurality of electrodes, a step of forming a resist layer on the organic compound layer formed on parts of electrodes among the plurality of electrodes using a photolithographic method, and a step of removing the organic compound layer in a region not covered with the resist layer by dry etching, wherein an entire surface of the organic planarizing layer on the substrate on which steps up to the step of forming the plurality of electrodes have been performed is covered with at least one of the etching resistant protection layer and the electrode.

A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.

A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.

A light-emitting device in which reduction in performance due to moisture is suppressed is provided. The light-emitting device has a structure in which a partition having a porous structure surrounds each of light-emitting elements. The partition having a porous structure physically adsorbs moisture; therefore, in the light-emitting device, the partition functions as a hygroscopic film at a portion extremely close to the light-emitting element, so that moisture or water vapor remaining in the light-emitting device or entering from the outside can be effectively adsorbed. Thus, reduction in performance of the light-emitting device due to moisture or water vapor can be effectively suppressed.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

A vehicular imaging and display system includes a rear backup camera at a rear portion of a vehicle, a video processor for processing image data captured by the rear camera, and a video display screen responsive to the video processor to display video images. During a reversing maneuver of the equipped vehicle, the video display screen displays video images captured by the rear camera. During forward travel of the equipped vehicle, the video display screen is operable to display images representative of a portion of the field of view of the rear camera to display images representative of an area sideward of the equipped vehicle responsive to at least one of (a) actuation of a turn signal indicator of the vehicle, (b) detection of a vehicle in a side lane adjacent to the equipped vehicle and (c) a lane departure warning system of the vehicle.

The purpose of the present invention is to provide a projection image display device in which all of the multiple light sources to be used are positioned optimally, regardless of the mode of installation of the device. This projection image display device has two illumination optical systems (1, 2) that are each provided with a light source (111, 211), a color separator for separating into three colors of light, a liquid crystal panel (150, 250) for forming an optical image, and a color synthesis prism (160, 260) for color-synthesizing. A polarization beam splitter (3) for synthesis synthesizes an optical image formed by the illumination optical system (1, 2), and projects the same from a projection lens (4). The optical axis (101, 201) of each light source (111, 211) is positioned within the same plane as the optical axis (401) of the projection lens (4), and so as to orthogonally intersect the optical axis (401) of the projection lens.

A liquid crystal display element disclosed includes: a first substrate; a second substrate; a liquid crystal layer sandwiched between the first substrate and the second substrate; a first transparent electrode provided at a display region of the first substrate; and a second transparent electrode provided at a display region of the second substrate, at least one of d1 and d2 being not larger than 60 nm, where d1 represents a thickness of the first transparent electrode and d2 represents a thickness of the second transparent electrode.