1 Bolivian Boliviano = 0.2049 Singapore Dollar

1 Bolivian Boliviano = 10.6449 Russian Ruble

1 Bolivian Boliviano = 0.6285 Malaysian Ringgit

1 Bolivian Boliviano = 2163.6735 Indonesian Rupiah

1 Japanese Yen = 0.0273 Tunisian Dinar

1 Japanese Yen = 92.4294 Sierra Leonean Leone

1 Japanese Yen = 0.0132 Singapore Dollar

1 Japanese Yen = 0.6881 Russian Ruble

1 Japanese Yen = 0.0406 Malaysian Ringgit

1 Japanese Yen = 139.8628 Indonesian Rupiah

The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested in the next generation tools. The same complaints can be heard from the foundries regarding their wafer pricing

Companies have tried royalty-based models before in the past (e.g., $/wafer or even profit sharing). But it hasn't been sticky. Is the industry ready for a new model?  I think sharing in the upside and potential downside of a particular design from inception to volume is fair. But it also would mean that EDA companies and foundries would have to participate even earlier (and later) in the product lifecycle - from design spec/marketing through product introduction.

That's a pretty big change that goes beyond just the business model. But maybe at 32nm and below, where designs cost upwards of $75M to bring to market, this type of collaboration and risk/reward model is required and desired

What is the meaning of this error?

I used already two ports (PORT1 and PORT2 for input and output, respectively.

-------------------------------------------------------------------------------------------------------------------------

Also when I apply the PSP analysis for S-parameter the value of maximum S21 value (4.75 dB) is much lower than the maximum power gain (17.6 dB).

while the same circuit is designed using  ADS program the two values are approximately the same around (17.1 dB).

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

Hi,

I am designing a resistive feedback TIA which needs a capacitor in its feedback loop for stability.

I would like to know the effect of a feedback capacitor on the phase margin to determine the optimal capacitance value.

My plan is to add it to the results after the stb analysis by using the direct plot>main form > phase margin (add to outputs).However it not getting added to my results list.

What could be a problem? Is there a way to add phase margin to the results using the calculator? 

I also find that the gain from the stability analysis(the closed loop gain) is different from that of the gain obtained for the closed loop simulation in AC analysis. Why is the difference, how is it computed in stability analysis?

Thanks,

-Rakesh.

I could barely recognize Ben Foster in 3:10 to Yuma, but I was blown away just the same by him as in his star making turn from Hostage. What makes Foster so special in Yuma?

Yuma contains two of Hollywood’s finest: Russell Crowe and Christian Bale. Bale is excellent, Crowe a little too relaxed to be cock-sure-dangerous. Both are unable to provide the powder-keg relationship that the movie demands.

Into this void steps Ben Foster. He plays Charlie Prince, sidekick to Crowe’s dangerous and celebrated outlaw Ben Wade. When Wade is captured, Prince is infuriated. He initiates an effort suffused with desperate passion to rescue his boss.

Playing Prince with a mildly effeminate gait, Foster quickly becomes the movie’s beating heart. What struck me in particular was that Foster was able to balance method acting with just plain good acting. He plays his character organically but isn’t above drawing attention with controlled staginess.

Gradually, Foster’s willingness to control a scene blend in with that of Prince’s. Is the character manipulating his circumstances in the movie or is it the actor playing a fine hand? Foster is so entertaining, the answer is immaterial.

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

I loved Nina Paley’s brilliant animated film Sita Sings the Blues. If you’re reading this, stop right now—and watch the film here.

Paley has set the story of the Ramayana to the 1920s jazz vocals of Annette Hanshaw. The epic tale is interwoven with Paley’s account of her husband’s move to India from where he dumps her by e-mail. The Ramayana is presented with the tagline: “The Greatest Break-Up Story Ever Told.”

All of this should make us curious. But there are other reasons for admiring this film:

The film returns us to the message that is made clear by every village-performance of the Ramlila: the epics are for everyone. Also, there is no authoritative narration of an epic. This film is aided by three shadow puppets who, drawing upon memory and unabashedly incomplete knowledge, boldly go where only pundits and philosophers have gone before. The result is a rendition of the epic that is gloriously a part of the everyday.

This idea is taken even further. Paley says that the work came from a shared culture, and it is to a shared culture that it must return: she has put the film on Creative Commons—viewers are invited to distribute, copy, remix the film.

Of course, such art drives the purists and fundamentalists crazy. On the Channel 13 website, “Durgadevi” and “Shridhar” rant about the evil done to Hinduism. It is as if Paley had lit her tail (tale!) and set our houses on fire!

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis...(read more)

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies...(read more)

Cadence's Digital Front-End Design Team first introduced the concept of a Rapid Adoption Kit (RAK) , self-guided and learn-by-doing training material, over two and a half years ago, helping its users across the globe deploy new products and flows. These...(read more)

Limny CMS version 2.0 suffers from a cross site request forgery vulnerability that allows for a malicious attacker to have an administrator account created. Proof of concept code included.

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