Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

An apparatus for assigning a plurality of access nodes of a wireless communication network to control areas includes a processing apparatus. The processing apparatus is configured to assign each access node in the plurality of access nodes to a control area of a plurality of control areas and to determine a first control phase. The first control phase is a period of time during which the assignment of access nodes to control areas remains constant. The processing apparatus is configured to, when changing from the first control phase to a following second control phase, reassign at least a subset of access nodes which were assigned during the first control phase to a first control area to a second control area and reassign at least a subset of access nodes which were assigned during the first control phase to a third control area to the first control area.

A method for transmitting uplink (UL) data requiring low latency in a wireless communication system according to the present invention, the method performed by a user equipment comprises transmitting contention PUSCH resource block (CPRB) indication information used for identifying a particular UE and/or particular data to an eNB; transmitting UL data to the eNB through CPRB resources of a contention based PUSCH (CP) zone; and receiving a hybrid automatic retransmit request (HARQ) response with respect to the UL data from the eNB through a physical hybrid ARQ indicator channel (PHICH).

A mechanism that allows the successful decoding of MCS information of cell edge UEs while retaining the performance for the other UEs of the cell is provided. In one aspect, a UE may determine an uplink control coding rate based on an uplink signal quality. The UE may encode uplink control data based on the uplink control coding rate. The UE may apply a pattern of unused resource element locations in uplink control resource elements based on the uplink control coding rate. The UE may transmit the uplink control resource elements with the pattern of unused resource element locations. In another aspect, an eNB may receive uplink control resource elements. The eNB may determine an uplink control coding rate based on a pattern of resource element locations in the uplink control resource elements. The eNB may decode uplink control data based on the uplink control coding rate.

In a communications system which complies with LTE including a base station which transmits data by using an OFDM (Orthogonal Frequency Division Multiplexing) method as a downlink access method, and a mobile terminal, in a case in which an uplink scheduling request signal is transmitted by using an S-RACH when an Ack/Nack signal is being transmitted by using an Ack/Nack exclusive channel, the transmission of the Ack/Nack signal is stopped while the uplink scheduling request signal is transmitted.

Various communication systems may benefit from managing signal interference. For example, certain wireless communication systems may benefit from a dynamic time division duplex system involving slot allocation. A method includes allocating, by an access point, in a time division duplex frame a plurality of radio resource slots, each one of the plurality of radio resource slots being allocated for a downlink or an uplink transmission, and determining that the allocation of the downlink or uplink transmission should be changed. The method also includes applying a permutation pattern to re-allocate at least one of the plurality of radio resource slots for the downlink or uplink transmission.

A time-reversal wireless system comprising a first wireless transceiver of a time-reversal client, one or more second wireless transceiver and/or a time-reversal client with the first wireless transceiver. The first wireless transceiver of the time-reversal client is wirelessly coupled to the one or more second wireless transceiver through a wireless broadband multipath channel associated with a space. The time-reversal client contains the first wireless transceiver. The time-reversal client also contains a processor and a memory configured to obtain a set of channel state information (CSI) in a channel probing phase, and/or to obtain a set of location-specific signatures based on the set of CSI and/or a time reversal operation in a channel probing phase. The set of CSI is captured when one or more probing signal is sent either from the first wireless transceiver to each of the at least one second wireless transceiver, or from each of the at least one second wireless transceiver to the first wireless transceiver, through the wireless broadband multipath channel associated with the space. A channel passband with bandwidth W0 is associated with the wireless broadband multipath channel. A first passband with bandwidth W1 is associated with the first wireless transceiver. The W1 is not larger than W0 such that the first passband is part of the channel passband. One or more second passband is associated with the one or more second wireless transceiver such that a bandwidth W2 associated with each of the one or more second passband is not larger than W1 such that the each of the one or more second passband is part of the first passband. Each of the set of CSI include a channel impulse response, a channel frequency response, and/or another channel state data of the wireless broadband multipath channel.

A data transmission apparatus in a communication system includes a reception unit configured to receive terminal information from a plurality of terminals through a new frequency band for transmission and reception of data between the plurality of terminals and an AP (access point); a determination unit configured to determine access timing of the terminals to the AP by using the terminal information, and generate terminal access information including information on the access timing; and a transmission unit configured to transmit the terminal access information and beacon frames to the terminals, wherein the terminals access the AP and transmit data frames to the AP, at the access timing based on the beacon frames.

Disclosed are a method for transmitting and receiving a frame in a wireless local area network (WLAN) system and an apparatus for the same. A method for generating interference/non-interference station lists includes receiving a first frame from a second station, acquiring a receiver address of the first frame from the first frame, and setting, based on whether to receive a second frame that is a response to the first frame from a third station indicated by the receiver address within a preset time from a time when the first frame has been received, the third station as an interference station or a non-interference station. Therefore, the performance of a communication system may be improved.

An apparatus, system and method are provided for transmitting data from logical channel queues over a telecommunications link, each of the logical channel queues capable of being associated with quality of service attributes, the method including determining available resources for transmission over the telecommunications link in a frame; selecting one of the logical channel queues based on a first one of the quality of service attributes; packaging data from the selected one of the logical channel queues until one of: a second one of the quality of service attributes for the selected one of the logical channel queues is satisfied, the available resources are used, or the selected one of the logical channel queues is empty; and repeating the selecting step and the packaging step for remaining ones of the logical channel queues.

The present disclosure provides an auxiliary communication method and system, a device having base station function and a terminal. The auxiliary communication method includes: determining whether it is needed to provide auxiliary communication for any terminal according to channel quality of communication channels with the any terminal and data transmission requirement of the any terminal; selecting a specified terminal which is connected to the device having the base station function as an auxiliary terminal for assisting communication of the any terminal, when it is determined that it is needed to provide auxiliary communication for the any terminal; communicating with the any terminal through the auxiliary terminal. The present disclosure enables accurately to determine the terminal assisted in communication. Wasting communication sources and blind assistance are avoided. And higher channel quality of the terminal between the terminal and the base station and higher data transmission rate can be ensured.

The present invention relates to a wireless communication system, and a method for determining a resource for device-to-device communication by a user equipment is disclosed. A method for determining a resource for device-to-device communication according to an embodiment of the present invention may comprise the steps of: receiving, from an eNode B (eNB), configuration information related to a resource pool configured for each level; selecting the resource pool of the device-to-device communication on the basis of the configuration information; and selecting a resource for the device-to-device communication in the resource pool. Herein, the resource pool may be configured to have two or more levels.

A technique for emulating virtual port control of airtime fairness for wireless stations using per station Enhanced Distributed Channel Access (EDCA) parameters. Specific parameters are received for each of a plurality of stations connected to the access point. An EDCA field of a beacon that stores a general EDCA parameter is set to an empty state. The beacon is broadcast to a plurality stations on the wireless communication network and within range of an access point. The beacon comprises a BSSID (Basic Service Set Identifier) for use by the plurality of stations to connect with the access point for access to the wireless communication network. The beacon also comprises an empty EDCA field. In response to broadcasting the empty EDCA parameter, receiving a direct inquiry from each of the plurality of stations for the general EDCA parameter. Each of the plurality of stations is responded to with a direct communication of a specific parameter corresponding to each station. A transmission is received from at least one of the stations complying with the specific parameter.

The disclosure relates in some aspects to resource requirement signaling and rate setting for communication on an unlicensed band. The disclosure also relates in some aspects to determining a token arrival rate as a function of traffic arrival information. In some aspects, the disclosed schemes may avoid traffic collisions on a resource and promote access fairness on the resource.

According to an aspect of the present invention, a device for communication according to a specific communication protocol is provided. The communication device includes a processor for generating and processing frames based on frame formats defined by the communication protocol. The processor generates a beacon frame so that information on a collision avoidance scheme supported by the device of a plurality kinds of information specified based on the communication protocol is omitted. Further, the processor processes a connection request frame transmitted from other device to extract information on a collision avoidance scheme supported by the other device, and controls communication with the other device based on comparison of the extracted information on the collision avoidance scheme with the information on the collision avoidance scheme supported by the device.

A remote maintenance system includes a maintenance management apparatus connected to a user apparatus and a communication relay apparatus connected to a remote-controlled apparatus. The maintenance management apparatus transmits, to the communication relay apparatus, message data whose destination is unique identification information of a mobile communication network assigned in advance to the communication relay apparatus. The communication relay apparatus notifies the maintenance management apparatus of an IP address that is dynamically assigned to itself upon reception of the message data. The maintenance management apparatus transmits, to the communication relay apparatus, information on remote operation received from the user apparatus whose destination is the notified IP address. The communication relay apparatus relays, to the remote-controlled apparatus, the information on the remote control received from the maintenance management apparatus.

This application provides a data transmission link establishment apparatus. The apparatus includes: a selection unit, configured to select a target node; a determining unit, configured to determine a backhaul node that needs to establish a data transmission link with the target node selected by the selection unit; a setting unit, configured to set protocol stack roles, in the data transmission link, of the target node and the backhaul node that is determined by the determining unit; and a configuration unit, configured to perform configuration on the target node and the backhaul node according to the protocol stack roles that are set by the setting unit, to establish the data transmission link between the target node and the backhaul node.

Provided are a device-to-device (D2D) operation method carried out by a terminal in an RRC connection state in a wireless communication system, and a terminal using the method. The method is characterized by: determining whether a radio resource control (RRC) connection establishment process is problematic; and transmitting a D2D signal using an exception resource, when the RRC connection establishment process is determined to be problematic.

A master user equipment (UE) device may coordinate device-to-device (D2D) communications amongst a plurality of UE devices. For example, a UE device, which has been designated as a master UE device, may coordinate a D2D communication between a first UE device and a second UE device. The master UE device may be a UE device that obtains an indication that it is a master UE device that is to coordinate D2D communications amongst the plurality of UE devices. In some embodiments, the coordinating the D2D communication may be on behalf of a network and/or to facilitate wireless communication between the network and at least one of the plurality of UE devices.

Provided are a device-to-device (D2D) operation method carried out by a terminal in an RRC connection state in a wireless communication system, and a terminal using the method. The method is characterized by: determining whether a communication link with a base station is problematic; and transmitting a D2D signal using an exception resource, when the communication link with the base station is determined to be problematic.

A query statement, issued to a local database server, is re-written. The query references at least one of a first or a second object. The first object is remote with respect to the local database server, for accessing a first materialized view that is local or remote with respect to the local database server. The second object is local with respect to the local database server, to access a second materialized view that is remote with respect to the local database server. Rewriting the query can include dynamically tracking a staleness state associated with one or more of the materialized views.

In one embodiment, a biased fabric is supplied. The biased fabric supply has a first specified width and a first bias angle of warp yarns relative to weft yarns. At least one overfeed roller configured to overfeed fabric from the biased fabric supply at an overfeed rate is provided. At least one spreading arm configured to stretch the fabric to a second specified width and a fabric oven configured to heat the biased fabric supply to a specified temperature and output a balanced crimp and/or elongation biased fabric are also provided.

A stretching assembly for cloth has a heating furnace, a pressing device and a shaping device. The heating furnace has two opposite sidewalls and a channel. The channel is formed through the opposite sidewalls of the heating furnace and has an inlet and an outlet. The pressing assembly is set to face the inlet of the heating furnace and has a first pressing wheel and a second pressing wheel. The first pressing wheel has multiple annular protruding segments formed on an external surface of the first pressing wheel. The second pressing wheel parallel the first pressing wheel to form a curved clearance between the pressing wheels and has multiple annular concave segments formed on an external surface of the second pressing wheel. The shaping device is set to face the outlet of the heating furnace, aligns with the pressing device and has two shaping wheels.