Using the EMX solver, X-FAB design engineers can efficiently develop next-generation RF technology for the latest communication standards (including sub-6GHz 5G, mmWave, UWB, etc.), which are enabling technologies for communications and electric vehicle (EV) wireless applications. (read more)

With the latest release (Sigrity and Systems Analysis 2022.1 HF2) of Clarity  3D Solver, support for encrypted component models is now available. With this functionality, vendors that supply 3D components, such as connectors, can now merge their...(read more)

If you have seen any images or demonstrations of the 17.4-2019 release, the GUI may look ...(read more)

Cadence Clarity 3D Solver supports encrypted component models! Using this functionality, vendors can supply their 3D components, such as connectors, to end customers without revealing the physical IP of these designs. The first connector vendor to take advantage of this functionality is Japan Aviation Electronics (JAE),(read more)

The Allegro PCB Editor Basic Techniques course provides all the essential training required to start working with Allegro® PCB Editor. The course covers all the design tasks, including padstack and symbol creation, logic import, constraints setup...(read more)

Hi, newbie here.

We are using AWR Design Enviroment in our university and so I have to install it (OS: Arch Linux)
I installed it in a Windows 10 VM without problems.

When I try to start it prompts "Failed to connect to license server", I guess thats the first problem.

After that when trying to generate my SUL License it will prompt Internal Error -8 (see Image)

I can't find something on Error -8 :/ and overall the available data to the license topic is quit low :/

If someone has a solution for that I would gladly hear about it :)

Hello, Currently i am designing a 96MHZ crystal oscillator using pierce topology and also I use for amplitude gain control circuit for regulation. The problem is when i run a PSS + Pnoise i get these warnings :

WARNING (CMI-2375): M2: Vgs has exceeded the oxide breakdown voltage of `vbox' = 6 V.
WARNING (CMI-2375): M4: Vgs has exceeded the oxide breakdown voltage of `vbox' = 6 V.
WARNING (CMI-2377): M4: Vgd has exceeded the oxide breakdown voltage of `vbox' = 6 V.
WARNING (CMI-2377): M3: Vgd has exceeded the oxide breakdown voltage of `vbox' = 6.6 V.

and also WARNING (CMI-2682): M5: The bulk-drain junction forward bias voltage (1.38154 V) exceeds VjdmFwd'=851.514mV ,The results are now incorrect because the junction current model has been linearized

Note : i am using Supply 1.2 V hence it is not possible to exceed the oxide breakdown. 

So i am asking why i am getting these warnings , it could be a convergence problem and the Results computed are not corrected.

Also when running DC and transient , i don't get these warnings.

Hi *,

I am simulating a 32kHz high Q crystal oscillator with a pulse shaping circuit. I set up a PSS analysis using the Shooting Newton engine. I set a beat frequency of 32k and used the crystal output and ground as reference nodes. After the initial transient the amplitude growth was already pretty much settled such that the shooting iterations could continue the job.

My problem is: In 5...10% of my PVT runs the simulator detects a frequency divider in the initial transient simulation. The output log says:

Frequency divided by 3 at node <xxx>

The Estimated oscillating frequency from Tstab Tran is = 11.0193 kHz .

However, the mentioned node is only part of the control logic and is always constant (but it has some ripples and glitches which are all less than 30uV). These glitches spoil my fundamental frequency (11kHz instead of 32kHz). Sometimes the simulator detects a frequency division by 2 or 3 and the mentioned node <xxx> is different depending on PVT - but the node is always a genuine high or low signal inside my control logic.

How can I tell the simulator that there is no frequency divider and it should only observe the given node pair in the PSS analysis setup to estimate the fundamental frequency? I have tried the following workarounds but none of them worked reliably:

- extended/reduced the initial transient simulation time

- decreased accuracy

- preset override with Euler integration method for the initial transient to damp glitches

- tried different initial conditions

- specified various oscillator nodes in the analysis setup form

By the way, I am using Spectre X (version 21.1.0.389.ISR8) with CX accuracy.

Thanks for your support and best regards

Stephan

I get multiple results at the same frequency in a 3-tone simulation.

I try to determine the IP3 of a mixer. I have 3 large signal tones: 0.75 GHz, 1.25 GHz and 1.26 GHz.

At the IM3 frequency of 490 MHz I observe 4 results, see also the screenshot of the table output. The frequencies are exactly the same (even when I subtract 490 MHz by using xval() ).

Which of the values do I have to use to determine the correct IP3?

Is there an option to merge these results?

Hello everybody,

As you can find in the attached image, I am trying to simulate a Colpitts oscillator. However, using pss analysis it shows a high output power. 

My question is where is the problem of my structure or simulation setup?

Best,

Hello everyone,

I am trying to perform a load pull simulation of a transistor to verify some gain calculations I made using its S-parameters. Specifically, I have calculated the optimal conjugate impedances for the input and output to later calculate the power dissipated and transmitted in each stage of the transistor. Then, I only varied the output impedance and recalculated these powers, noticing that the power delivered to the load is lower.

Now, what I want to do is simulate this behavior using the Load Pull simulation. I have taken the model shown in the image, but I believe it is a linear model. My question is: if the chosen model is linear, is the load pull simulation accurate? In the calculations I made, nonlinearities are not considered. I don’t want to take nonlinearities into account.

In short, do you have any ideas on how to verify the calculations made with the transistor’s S-parameters through a load pull simulation?

Can you recommend any transistor model that is nonlinear and also has an S-parameter file?

Thank you very much in advance.

Hello everyone,

For my cross-coupled oscillator design, I have a problem with stability analysis. Based on my achieved results which are attached, where is my design problem?

Best,

https://ibb.co/bgKFP4N

https://ibb.co/3FGRLmV

https://ibb.co/pwSZDSF

Hi I noticed that some figures from the old posts in the cadence blogs have been missing.

I think this problem happened before and Andrew Beckett asked the original author to fix the issue:

 Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" 

Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts,

Thanks

Leandro

I have been involved in the Virtuoso RF Solution for the last four years. Most of the customers I work with have a SiP package already in progress. They often ask "How do I get my SiP design into Virtuoso RF Solution?" I am excited about new functionality in the latest ICADVM20.1 ISR25 release. It is a new GUI under the Tools menu called Enablement. (read more)

This blog introduces you to an efficient way to debug interface elements or connect modules in a mixed-signal simulation.(read more)

Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.(read more)

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.(read more)

This blog helps in demonstrating the use of Pin to trunk routing style which helps in enhancing the layout experience.(read more)

Is there a way to set a thru via hole to thru via hole spacing constraint?

I need the hole to hole spacing, nit pad to pad spacing.

I can calculate the spacing using the via pad diameter, but this won't work for multiple via pad sizes.

I want to make an opening in the solder mask right above a trace that is acting like a guard ring. Do I really need to go and buy the Allegro Productivity Toolbox add-on for using the Cross-Copy tool for a basic operation like that??

/F

I have a small shape for connecting three SMD pads, but it won't connect to one of the pads (0.2x0.6 mm). Thermal relief connects are set to Full contact for SMD pin in Shape parameters, but that doesn't help.

However, if I decrease the Minimum aperture for gap width in Void controls in Shape parameters to something below 0.2 mm the shape connects to the pad. But it is a little contracted at the pad entrance. Just 0.002 mm. What is going on here? 

Tried to attach some pictures, but I get: "An error occurred. Please try again or contact your administrator.". Will try later again.

/F

Hi

I have fixed a SPACING RULE (SP1) for a CLASS_DIFF_PAIR whereas for via associated to the net (DP_VIA), the DISTANCE > 60mils respect to ANY other vias (PTH, BB, TEST vias)

Now my problem is that this rules should NOT be applied for GND VIAS (STICHING VIA) which must be placed at a distance < 40mils respect to DP_VIA

How to create an exemption to the SPACING RULE (SP1)?

Loading new netlist into 23.1 Apparently it does not like many of the specified footprints or padstacks. I have to open the footprint in 231., save the pad stack then save the footprint. This is very time consuming and frustrating to say the least.

I also get the following message

WARNING(SPMHNI-194): Symbol 'SMD_SOD123_ANODE_PIN1' used by RefDes D30 for device 'DIODE_0_SMD_SOD123_ANODE_PIN1_1N4148W-7-F' not found.

The symbol either does not exist in the library path (PSMPATH) or is an old symbol from a previous release.  

Set the correct library path if not set or use dbdo

     The current version of software is unable to open design smd_sod123_anode_pin1.

The design was last saved using version 16.5 and must be updated using DB Doctor. [help]


Going to DB Doctor does nothing, no option to update a footprint?

Tom

Hello,

Trying to figure out why this situation does not generate a DRC error.

A resistor was accidently placed so the pad was on top of another pad. See picture:

I have checked the CM and both Spacing Constraint Set and Same Net Spacing Constraint Set have Smd pin to Smd pin set to 0.1 mm.

I'm using Allegro PCB designer 22.1.

If someone has an idea why this does not give a DRC i would appreciate it. Thanks.

Regards,

Filip

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Hai Community,

I have a PCB board which has multiple high speed nets and I want to perform the EMI and EMC checking.

Which Cadence tool should I use for checking the EMI and EMC coupling?

Regards,

Rohit Rohan

Dear Community,

In OrCAD X Profession, the workspace feature enables the users to store the libraries (Schematic Symbol, Footprint and PSpice Models) and Designs (Schematic and PCB layout) in the cloud workspace.

But storing these libraries and design are stored in servers in the USA, Europe, Asia and Japan Servers.

I don't want to store my designs in any of these servers instead I want to create the workspace in my local PC and store all my libraries and designs in the local workspace.

Is this possible, if possible then can anyone provide the steps/procedure or videos of how to do it?

Regards,

Rohit Rohan

Dear Community,

I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional.

Regards,

Rohit Rohan

Socionext, a leader in SoC design, recently made significant strides in enhancing its design efficiency for a complex billion-gate project. Faced with the initial challenges of lengthy eight-day iterations and a protracted two-month timing signoff process, the objective was to reduce the iteration cycle to just three days. By integrating Cadence's cutting-edge solutions—Certus Closure Solution, Tempus Timing Solution, and Quantus Extraction Solution—Socionext achieved remarkable improvements.

Notably, the Tempus DSTA tool dramatically cut timing closure time by 73%, outperforming conventional single-machine STA methods. This achievement, combined with the synergistic use of Cadence's Certus Closure and Tempus Timing solutions, allowed Socionext to meet their ambitious three-day iteration target and double productivity. Additionally, integrating these solutions significantly decreased both human and machine resource needs, slashing memory and disk costs by up to 90% and halving engineering resources during the optimization and signoff phases.

For more on this collaboration, check out the "Designed with Cadence" success story video on Cadence's website and YouTube channel.

Also, don't miss the on-demand webinar "Fast, Accurate STA for Large-Scale Design Challenges," which provides a deeper dive into Socionext's breakthroughs and the innovative solutions that powered their success.

In this training webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. We will guide you through the essential steps in creating integrated circuits, the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow.

When Is the Webinar?

Date and Time

Wednesday, September 18, 2024
07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing 

REGISTER

To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System.

Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details.

If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

To view our complete training offerings, visit the Cadence Training website.

Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.

Want to Learn More?

This link gives you more information about the related training course and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Also, take this opportunity to register for the free Online Trainings related to this webinar topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Xcelium Integrated Coverage

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Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!

The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet the power, performance, and area (PPA) goals in a completely automated way. Use Cerebrus Apps to optimize some aspects of the design as well.

Running a full RTL to GDSII flow, Cadence Cerebrus has a lot of possibilities and combinations of different tool settings to explore.

Using the knowledge from previous runs, combined with on-the-fly analysis within the flow, Cadence Cerebrus can assess many settings combinations and fine-tune the flow accordingly in a very efficient manner.

As technology advances, projects become bigger and way more complex than before. The ability of a single engineer to run simultaneously a large number of blocks in a traditional way is limited. Cadence Cerebrus allows a single engineer to work more efficiently and implement more blocks, while maintaining the same or even better PPA, using compute power.

Being such a revolutionary tool, integrating Cerebrus into your existing flow is surprisingly simple as it can wrap around any existing flow scripts.

Please join me in this course, to learn about the features and basics of Cadence Cerebrus Intelligent Chip Explorer.

We’ll walk through the tool setting stage, explain what is a primitive and how it effects our run, talk about the cost function and the run goals.

We’ll understand the concept of scenarios, learn how to analyze the results of the different runs, and compare them.

In addition, we’ll talk about basic debug rules and methods to analyze failures.

Sounds Interesting?

Please join our “live” one-day Cadence Cerebrus Intelligent Chip Explorer Training @Cadence Feldkirchen planned for October 9th, 2024!

For more details and registration, please contact Training Germany.

If you would like to have an instructor-led training session in another region please contact your local training department.

Become Cadence Certified

Cadence Training Services offers a digital badge for this training course. This badge indicates proficiency in a certain technology or skill and gives you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding this digital badge to your email signature or any social media platform, such as Facebook or LinkedIn.

Related Training

Innovus Block Implementation with Stylus Common UI

Related Training Bytes

Cerebrus Primitives (Video) 

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Cerebrus - Verifying Distribution Script (Video)

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Cerebrus Web Interface Monitor and Control (Video) 

How to Setup Cerebrus for a Successful Run (Video) 

Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have (Webinar) (Video) 

Cerebrus Cost Functions (Video) 

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In this recent Training Webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow by guiding you through essential steps involved in creating integrated circuits—the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

Watch the Training Webinar recording from September 18, 2024: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

Want to Learn More?

This link gives you more information about this RTL-to-GDSII Flow, the related training course, and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

 Also, take this opportunity to register for the free Online Training related to this Webinar Topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Learning Maps

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

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In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

Related Resources 

Related Training Bytes:

Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

Running Prototype Implementation Flow in Joules RTL Design Studio (Video)

Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Please don't forget to obtain your Digital Badge after completing the training.

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Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit! - Digital Design - Cadence Blogs - Cadence Community

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Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community

Research by fDi Intelligence reveals which countries receive more than their ‘expected share’ of FDI. 

London has been named fDi’s inaugural Fintech Location of the Future for 2019/20, followed by Singapore and Belfast. 

Australia tops the FDI Strategy category of fDi's Tourism Locations of the Future 2019/20 rankings, followed by Costa Rica and Azerbaijan.

A look at the results of fDi’s rankings throughout 2019 finds that Singapore and New York dominated the year’s league tables, followed by Shanghai, Tokyo and London

The EU is considering a broader mandate for the EBRD, and its president, Sir Suma Chakrabarti, believes its model would work in sub-Saharan Africa.

Poor infrastructure and political instability deter tourism, but small and manageable steps to avoid chaos and promote hospitality can work wonders.

The chief executive of Ras Al Khaimah Economic Zone (RAKEZ), shares his views over the perks of free zones in emerging markets. 

Tanzania's economy is booming and its tourism sector is thriving. However, concerns about the president's strong-arm tactics and delays in the completion of key infrastructure projects are threatening this growth.

Kenya’s cabinet secretary for the national treasury and planning, Ukur Yatani, discusses the country’s agenda of fiscal reforms and the importance of constructing an east-west Africa highway.

The UN Sustainable Development Goals aim to end global poverty, but poorer countries are struggling to hit them. More help from richer countries is crucial, writes Mazdak Rafaty.

Atlantis in South Africa has a new SEZ focused on green manufacturing, which is hoping to turn around the area's fortunes. Annie Hessler reports.

The UK is the Europe's leading destination for foreign investment in green energy, followed by Spain, finds fDi’s Top European Locations for Renewable Energy Investment.

Authorities in the US, the EU and across the developed world are stepping up efforts to scrutinise foreign investment on the grounds of both national security and tech sovereignty.

Sustainability is gaining traction in the creative industries, with the Italian region of Trentino designing a film production rating protocol that is being considered by the EU.

Serbia’s minister of finance, Siniša Mali, explains why the country is one of Europe's economic stars, and how its FDI levels have risen on the back of this.

London event hears how the UK export credit agency is increasing its focus on trade with African countries. Jason Mitchell reports.

Foreign investment into Serbia is growing at a healthy pace thanks to its attractive automotive manufacturing industry and highly regarded free zones.