1 Papua New Guinean Kina = 176.3653 CFA Franc BCEAO

1 Papua New Guinean Kina = 0.2831 Swiss Franc

1 Brunei Dollar = 428.0882 CFA Franc BCEAO

1 Brunei Dollar = 0.6871 Swiss Franc

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions:

While your interconnect subsystem might have a correct functionality, are you starving your IP functions of the bandwidth they need? Are requests from latency-critical initiators processed on time? How can you ensure that all applications will receive the desired bandwidth in steady-state and corner use-cases?

To answer these questions, Cadence recommends the Performance Verification Methodology to ensure that the system performance meets requirements at the different levels:

1. Performance characterization: The first level of verification aims to verify the path-to-path traffic measuring the performance envelope. It targets integration bugs like clock frequency, buffer sizes, and bridge configuration. It requires to analyze the latency and bandwidth of design’s critical paths.
2. Steady state workloads: The second level of verification aims to verify the master-by-master defined loads using traffic profiles. It identifies the impact on bandwidth when running multi-master traffic with various Quality-of-Service (QoS) settings. It analyzes the DDR sub-system’s efficiency, measures bandwidth and checks whether masters’ QoS requirements are met.
3. Application specific use cases: The last level of verification simulates the use-cases and reaches the application performance corner cases. It analyzes the master-requested bandwidth as well as the DDR sub-system’s efficiency and bandwidth.

Cadence has developed a set of tools to assist customers in performance validation of their SoCs. Cadence Interconnect Workbench simplifies the setup and measurement of performance and verification testbenches and makes debugging of complex system behaviors a snap. The solution works with Cadence Verification IPs and executes on the Cadence Xcelium® Enterprise Simulator or Cadence Palladium® Accellerator/Emulator, with coverage results collected and analyzed in the Cadence vManager  Metric-Driven Signoff Platform.

To verify the performance of the Steady State Workloads, Arm has just released a new AMBA Adaptive Traffic Profile (ATP) specification which describes AMBA abstract traffic attributes and defines the behavior of the different traffic profiles in the system.

With the availability of Cadence Interconnect Workbench and AMBA VIP support of ATP, early adopters of the AMBA ATP specification can begin working immediately, ensuring compliance with the standard, and achieving the fastest path to SoC performance verification closure.

For more information on the AMBA Adaptive Traffic Profile, you can visit Dimitry's blog on AMBA Adaptive Traffic Profiles: Addressing The Challenge. 

More information on Cadence Interconnect Workbench solution is available at Cadence Interconnect Solution webpage.

Thierry

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs.

Semiconductor designers have long been making test chips to validate test structures, memory bit cells, larger memory blocks, and precision analog circuits like current mirrors, PLLs, temperature sensors, and high-speed I/Os. This has been done at 90nm, 65nm, 40nm, 32nm, 28nm, etc., so having test chips at 16nm, 7nm, or finer geometries should not be a surprise. Still, as costs rise, there is debate about whether those chips are over-used given advancements in tooling, or whether they should be utilized even more, with more advanced diagnostics built into them.

Modern EDA tools are very good. You can simulate and validate almost anything with certain degree of accuracy and correctness. The key to having good and accurate tools and accurate results (for simulation) is the quality of the foundry data provided. The key to having good designs (layouts) is that the DRC deck must be of high quality and accurate and must catch all the things you are not supposed to do in the layout. Most of the challenges in advanced node is in the FEOL where semiconductor physics and lithography play outsize roles. Issues that were not an issue at more mature nodes can manifest themselves as big problems at 7nm or 5nm. Process variation across the wafer and variation across a large die also present problems that were of no consequence in more mature nodes.

The real questions to be asked are as follows:

What is the role of test chips in SoC designs?

1. Do all hard IP require test chips for validation?
2. Are test chips more important at advanced nodes compared to more mature nodes?
3. Is the importance of test chip validation relative to the type of IP protocols?
4. What are the risks if I do not validate in silicon?

In complex SoC designs, there are many high-performance protocols such as LPDDR4/4x PHY, PCIe4 PHY, USB3.0 PHY, 56G/112G SerDes, etc. Each one of these IP are very complex in and by itself. If there is any chance of failure that is not detected prior to SoC (tapeout) integration, the cost of retrofit is huge. This is why the common practice is to validate each one of these complex IP in silicon before committing to use such IP in chip integration. The test chips are used to validate that the IP are properly designed and meet the functional specifications of the protocols. They are also used to validate if sufficient margins are designed into the IP to mitigate variances due to process tolerances. All high-performance hard IP go through this test chip/silicon validation process. Oftentimes, marginality is detected at this stage. In advanced nodes, it is also important to have the test chips built under different process corners. This is intended to simulate process variations in production wafers so as to maximize yields. Advanced protocols such as 112G, GDDR6, HBM2, and PCIe4 are incredibly complex and sensitive to process variations. It is almost impossible to design these circuits and try to guarantee their performance without going through the test chip route.

Besides validating performance of the IP protocols, test silicon is also used to validate robustness of ESD structures, sensitivity to latch up, and performance degradation over wide temperature ranges. All these items are more critical in advanced nodes than more mature modes. Test chips are vehicles to guarantee design integrity in bite-size chunks. It is better to deal with any potential issues in smaller blocks than to try to fix them in the final integrated SoC.

Test chips will continue to play a vital role in helping IP and SoC teams lower the risk of their designs, and assuring optimal quality and performance in the foreseeable future. They are not going away!

To read more, please visit https://semiengineering.com/test-chips-play-larger-role-at-advanced-nodes/

I’m writing this on August 15. It is our Independence Day. A young Kashmiri Muslim told me in Srinagar a few months ago that this is the day on which everyone there tries to stay indoors. This is not because the people support Pakistan, but because they are most suspect on August 15. You are questioned, searched, and locked. If any of the readers have had a chance to view Sanjay Kak’s powerful documentary Jashn-e-Azadi (How We Celebrate Freedom) you’ll see how Sanjay, coming in to Srinagar for a visit around Independence Day, is struck by the fact that the only people present for the ceremony are the cops and members of the armed forces. (That’s Rave Out #1. For Jashn-e-Azadi.)

Last week’s announcement of the Indian Express-CNN/IBN poll, that an overwhelming majority of Kashmiris in the valley want azadi, also underlines the importance of a genuine rethinking on the question of independence rather than empty, nationalist sabre-rattling. (Anyway, that’s Rave Out #2. For Indian Express and CNN/IBN, as well as the good folk at CSDS who designed the poll.)

This is a good day for re-opening the pages of 13 December: A Reader, in which thirteen writers and journalists point out the injustice involved in the quick media-lynching of SAR Geelani and the denial of a fair trial to Afzal Guru. (This would be Rave Out #3, for the book, although wouldn’t it be great if the book weren’t needed?)

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

Physical synthesis has been around in various forms for many years. The basic idea is to bring some awareness of physical layout into synthesis. This week (June 3, 2015) Cadence is rolling out the Genus™ Synthesis Solution, a next-generation RTL synthesis tool that takes physical awareness in some new directions.

Here are four important things to know about Genus technology:

• A massively parallel architecture improves turnaround time by up to 5X while maintaining quality of results
• The Genus solution synthesizes up to 10M+ instances flat without impacting power, performance and area (PPA)
• The Genus solution provides tight correlation with the Innovus Implementation System, using the same placement and routing algorithms
• Globally focused PPA optimization saves up to 20% datapath area and power

Compared to previous-generation products such as the Cadence Encounter RTL Compiler Advanced Physical Option, the Genus solution approaches physical synthesis in a different way. The Encounter solution applied physical optimization “at the tail end of synthesis,” said David Stratman, senior principal product manager at Cadence. “We were doing a final incremental push, but we could only do so much, since we had locked in a lot of the earlier steps from a logical-only synthesis perspective.”

Genus Synthesis Solution supports the physical synthesis features in the previous Encounter solution, but it also brings the full physical scope upstream to RTL logic designers. “It’s going to enable the unit-level RTL designer to gain the benefits of physical synthesis without having to understand it,” Stratman said. As an example, users can apply generic (unmapped) placement at the earliest stages of synthesis, using a lightweight version of the Innovus placement engine. The bottom line: “Genus is a full solution where every step of synthesis can be done physically.”

Getting Massively Parallel

If you bring physical data into synthesis, you need a way to improve capacity and runtimes, especially with today’s gigantic advance-node SoCs. That’s why a massively parallel architecture is the cornerstone of the Genus solution. In this way, the Genus solution is following in the footsteps of the Innovus Implementation System, which also provides a massively parallel architecture.

Both the Innovus and Genus solutions can handle blocks of 10M instances flat. Given that SoCs today may have up to 100M instances, and often up to 50-100 top-level blocks, this is an important capability. Many tools today will only handle blocks of 1M instances. As a result, design teams often have to constrain block sizes.

Genus technology offers timing-driven, multi-level design partitioning across multiple threads and machines. It enables a near-linear runtime scaling without impacting PPA. According to Stratman, the Genus solution will scale well beyond 64 CPUs for a large design, with a “sweet spot” around 8-20 CPUs for today’s typical block sizes. Runs that used to take days, he noted, can now be done in hours.

As shown below, Genus technology leverages parallelism at three levels. The Genus solution can distribute design partitions to multiple threads or CPUs, and also supports local algorithm-level multithreading on each machine with shared memory. An adaptive scheduler ensures the best use of the available CPUs.

Fig. 1 – Genus Synthesis Solution provides three levels of parallelism

With its massive parallelism, Stratman said, Genus technology can obtain production-level quality of results (QoR) in runtimes typically seen in “prototype-level” synthesis runs. The “secret sauce,” he said, is in the partitioning. Cadence has found a way to generate partitions in a way that “slices the design more intelligently, and takes advantage of the Genus database to merge partitions without losing timing, power, or area,” Stratman said.

Playing in the Sandbox

In the Genus Synthesis Solution, a process called “sandboxing” allows any subset or partition of a design to be extracted along with full timing and a physical context. Optimization algorithms will treat a sandbox as a complete design.

The “Clipper” flow clips out or extracts the context of the larger SoC blocks. “It’s kind of a skeleton floorplan but it has all the timing information,” Stratman said. These extracted contexts include all the critical physical information to make the right RTL synthesis choices at the unit level. This information is used to streamline the handoffs between unit-level RTL designers, integration engineers, and implementation engineers. It’s a way for logic designers to gain some physical knowledge without having to be a physical synthesis expert, or without having to run a full top-level synthesis.

Fig. 2 – Clipper flow provides context for unit-level blocks

Correlation with Innovus Implementation System

Although Genus technology can work with third-party IC implementation systems, it shares algorithms and engines with Innovus Implementation System, as well as a common user interface. As shown below, both the Genus and Innovus solutions use a table-based Quantus QRC parasitic extraction, effective current source model (ECSM) and composite current source (CCS) delay calculations, and a unified global routing engine. Timing and wire length claim a 5% correlation.

Fig. 3 – Genus Synthesis Solution offers tight correlation with Innovus Implementation System

Genus technology doesn’t model everything to the same level of accuracy as the Innovus solution, however. “We chose to be lighter weight and more nimble to get expected runtimes,” Stratman said. A tight correlation is possible because the Genus and Innovus solutions use a similar code base. This correlation will be tighter than that between Encounter RTL Compiler Advanced Physical Option and the Encounter Digital Implementation System today.

Genus Synthesis Solution uses a new Hybrid Global Router that provides the ability to resolve congestion and construct layer-aware, timing-driven wire topologies. This accelerates analysis and debug, and reduces iterations. Users can avoid blockages and see a full Manhattan route as opposed to “flight lines.” Layer awareness is particularly important, given the large RC variations within the metal stack at advanced process nodes.

A version of the Innovus GigaPlace engine is available within the Genus solution. Here, users can do an RTL-level generic gate placement early in the synthesis flow (“generic gate” means there is no mapping into standard cell libraries, but there’s still an area estimate). This helps designers understand PPA tradeoffs earlier.

While users can go all the way to a design-rule “legal” placement with Genus Synthesis Solution, this isn’t generally recommended. “You can do a placement and use the same algorithms as GigaPlace and get a nice correlation without all the runtimes and additional steps of doing a fully legal placement,” Stratman said.

So where does Genus technology end and Innovus technology begin? That’s up to the user. You could use the Genus solution for logical synthesis and run all physical implementation in the Innovus system. If you run physical synthesis within the Genus solution, there’s more work earlier in the flow, but you get better insights into downstream problems and reduce iterations.

“Physical synthesis should be no more than 2X [runtime] of logic synthesis,” Stratman said. “All of the runtime that moves up should be shaved off of the place-and-route stages, because now you can do lightweight incremental optimization and incremental placement. The overall flow should be runtime neutral or better.”

Be Globally Aware

Finally, Genus Synthesis Solution offers a globally focused early PPA optimization across the whole datapath, delivering up to a 20% area reduction in the datapath. Stratman noted that this capability is a follow-on to an RCP feature called “globally focused mapping” that can determine the best cells to use in a library. What’s new with the Genus solution is that this concept has been applied at the arithmetic level.

For example, there are many ways to configure a multiplier – you may want to prioritize speed, power, or size. In the past, Stratman noted, synthesis tools have not been very good at globally optimizing the architecture selection for PPA optimization. “We can [now] find the most efficient global datapath implementation for a given region,” he said.

For further information about the Cadence Genus Synthesis Solution, including a datasheet and technical product brief, see this landing page.

Richard Goering

Related Blog Posts

Designer View – RTL Synthesis Success Strategies at 28nm and Below

Front-End Design Summit: The Future of RTL Synthesis and Design for Test

Physically-Aware Synthesis Helps Design a New Computer Architecture

One reason for attending the upcoming Design Automation Conference (DAC 2015) is to learn about challenges other engineers have faced, and hear about their solutions. And the best place to do that is the Cadence Theater, located at the Cadence booth (#3515). The Theater will host continuous half-hour customer and partner presentations from 10:00 am Monday, June 8, to 5:30 pm Wednesday June 4.

As of this writing, 43 presentations are scheduled. This includes 17 customer presentations, 23 partner presentations, and 3 Cadence presentations, The presentations are open to all DAC attendees and no reservations are required.

Cadence customers who will be speaking include engineers from AMD, ams, Allegro Micro, Broadcom, IBM, Netspeed, NVidia, Renesas, Socionet, and STMicroelectronics. Partner presentations will be provided by ARM, Cliosoft, Dini Group, GLOBALFOUNDRIES, Methodics, Methods2Business, National Instruments, Samsung, TowerJazz, TSMC, and X-Fab.

These informal presentations are given in an interactive setting with an opportunity for questions and answers. Audio recordings with slides will be available at the Cadence web site after DAC. To access recordings of the 2014 DAC Theater presentations, click here.

This Cadence DAC Theater presentation drew a large audience at DAC 2015

Here’s a listing of the currently scheduled Cadence DAC Theater presentations. The latest schedule is available at the Cadence DAC 2015 site.

Monday, June 8

Tuesday, June 9

Wednesday, June 10

In a Wednesday session (June 10, 10:00 am) at the theater, the Cadence Academic Network will sponsor three talks on academic/industry collaboration models. Speakers are Dr. Zhou Li, architect, Cadence; Prof. Xin Li, Carnegie-Mellon University; and Prof. Laleh Behjat, University of Calgary.

As shown above, there will be a giveaways for a set of Bose noise-cancelling headphones, an iPad Mini, and a GoPro Hero3 video camera.

See the Cadence Theater schedule for further details. And be sure to view our Multimedia Site for live blogging and photos and videos from DAC. For a complete overview of Cadence activities at DAC, see our DAC microsite.

Richard Goering

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DAC 2015: See the Latest in Semiconductor IP at “IPTalks!”

Cadence DAC 2015 and Denali Party Update

DAC 2015: Tackling Tough Design Problems Head On

Formal verification is a complex technology that has traditionally required experts or specialized teams who stood apart from the IC design and verification flow. Taking a different approach, a new release of the Cadence JasperGold formal verification platform (June 8, 2015) provides formal techniques that complement simulation, emulation, and debugging in the form of “Apps” or under-the-hood solutions that any design or verification engineer can use.

JasperGold was the initial (in fact only) product of Jasper Design Automation, acquired by Cadence in 2014. Jasper pioneered the formal Apps concept several years ago. While the company had previously sold JasperGold as a one-size-fits-all solution, Jasper began selling semi-automated JasperGold Apps that solved specific problems using formal analysis technology.

The new release is the next generation of JasperGold and will be available later this month. It includes three major improvements over previous Cadence and Jasper formal analysis offerings:

• A unified Cadence Incisive and JasperGold formal verification platform delivers up to 15X performance gain over previous solutions.
• JasperGold is integrated into the Cadence System Development Suite, where it provides formal-assisted simulation, emulation, and coverage. As a result, System Development Suite users can find bugs three months earlier than existing verification methods.
• JasperGold’s formal analysis engines are integrated with the recently announced Indago debug platform, automating root cause analysis and on-the-fly, what-if exploration.

Best of Both Formal Verification Worlds

Taking advantage of technologies from both Cadence and Jasper, the new JasperGold represents a “best of both worlds” solution, according to Pete Hardee, product management director at Cadence. This solution combines technologies from the Cadence Incisive Enterprise Verifier and Incisive Formal Verifier with JasperGold formal analysis engines.

For example, to ease migration from Incisive formal tools, Cadence has integrated an Incisive common front end into the JasperGold apps platform. Jasper formal engines can run within the Incisive run-time environment. Cadence has also brought some selected Incisive formal engines into JasperGold.

As shown to the right, the JasperGold platform supports both the existing JasperGold front-end parser and the Incisive front-end parser. Hardee observed that this dual parser arrangement simplifies migration from Incisive formal tools to JasperGold, and provides a common compilation environment for people who want to use JasperGold with Incisive simulation. Further, the common run-time environment enables formal-assisted simulation.

The combination of JasperGold engines and Incisive engines supports two use models for formal analysis: formal proofs and bug hunting. In the first case, formal engines try all combinations of inputs without a testbench. The test is driven by formal properties written in languages such as SVA (SystemVerilog assertions) or PSL (Property Specification Language). Completion of a property is exhaustive proof that something can or cannot happen. This provides a “much stronger result” than simulation, Hardee said.

He also noted that formal analysis doesn’t necessarily require that all properties are completed. “You can get a lot of value even if proofs don’t complete,” he said. “Proofs that run deep enough to find bugs are just fine.”

Bug hunting involves random searches, and JasperGold bug hunting engines are very fast. However, these engines don’t necessarily use the most optimal path to get to a bug. So, Cadence engineers brought a constraint solver from Incisive and integrated it into JasperGold. “It looks at the constraints in the environment and gives you a better starting point,” Hardee said. “It takes more up-front time, but once you’ve done that the bug hunting engines can actually take a shorter path and find a bug a lot quicker.”

Another new JasperGold capability from the Incisive Formal Verifier is called “search pointing.” This uses simulation to penetrate deeply into the state space, and then kicks off a random formal search from a given point that you’ve reached in simulation. This technique makes it possible to find bugs that are very deep in the design.

It is probably clear by now that a number of different formal “engines” may be required to solve a given verification problem. Traditionally, a formal tool (or user) will farm a problem out to many engines and see which one works best. To put more intelligence into that process, Cadence launched the Trident “multi-cooperating engine” a couple of years ago. That has now been brought into JasperGold, where it helps “orchestrate” the engines according to what will work best for the design. This is a big part of the reason for the 15X speedup noted earlier in this post.

Integration with System Development Suite

The Cadence System Development Suite is an integrated set of hardware/software development and verification engines, including virtual prototyping, Incisive simulation, emulation, and FPGA-based prototyping. As shown below, JasperGold technology is integrated into the System Development Suite in several places, including formal-assisted debug, formal-assisted verification closure, formal-assisted simulation, formal-assisted emulation, and the Incisive vManager verification planning tool.

Formal-assisted emulation sounds like it should be easy, especially since Cadence has both accelerated verification IP (VIP) and assertion-based VIP. However, there’s a complication. Accelerated VIP represents less verification content than simulation VIP, because you have to remove many checkers to get VIP to compile on a Palladium emulator. That’s because the Palladium requires synthesizable code.

What you can do, however, is use assertion-based VIP in “snoop mode” as shown below. Assertion-based VIP coded in synthesizable SystemVerilog can replace the missing checkers in accelerated VIP. In this diagram, everything in the green box is running in the emulator and is thus completely accelerated.

Another example of formal-assisted emulation has to do with deep traces. As Hardee noted, emulation will produce very long traces, and it can be very difficult to find a point of interest in the trace and determine what caused an error. With formal-assisted emulation, users can find interesting events within the traces and create properties that mark them, so a debugger can find these events and trace back to the root cause.

Formal-assisted verification closure is available with the new JasperGold release. This is possible because you can use the vManager product to determine which tasks were completed by formal engines. It’s important information for verification managers who are not used to formal tools, Hardee noted.

Another aspect of formal-assisted verification closure is the JasperGold Unreachability Analysis (UNR) App, which can save simulation users weeks of time and effort. This App takes in the simulation coverage database and RTL, and automatically generates properties to explore coverage holes and determine if holes are reachable or unreachable. The App then generates an unreachable coverage point database. If the unreachable code does something useful, there’s a bug in the design or the testbench; if not, you don’t have to worry about it. The diagram below shows how it works.

Formal-Assisted Debugging

The third major component of the JasperGold announcement is the integration of formal analysis into the Indago debugging platform. As shown below, this platform has several apps, including the Indago Debug Analyzer. Two formal debug capabilities from the Jasper Visualize environment have been added to the the Indago Debug Analyzer:

• Highlight Relevant Logic: This highlights the “cone of influence,” or the logic that is involved in reaching a given point
• Why: This button highlights the immediate causes for a given event, and allows users to trace backwards in time

More formal capabilities will come with the Indago Advanced Debug Analyzer app, scheduled for release towards the end of 2015. This includes Quiet Trace, a Jasper capability that reduces trace activity to transactions relevant to an event. Also, a what-if analysis allows on-the-fly trace editing and recalculation to explore effects and sensitivities, without having to re-compile and re-execute the simulation.

Finally, Cadence has a Superlint flow that is now fully integrated with the JasperGold Visualize debugger. This two-tiered flow includes a basic lint capability as well as automated formal analysis based on the JasperGold Structural Property Synthesis app. “This could be a very good entry point for designers to start using formal,” Hardee said.

“Formal is taking off,” Hardee concluded. “People are no longer talking about return on investment for formal—they have established that. Now they’re supporting a proliferation of formal in their companies such that a wider set of people experience the benefit from that proven return on investment.”

Further information is available at the JasperGold Formal Verification Platform (Apps) page.

Richard Goering

Related Blog Posts

- JUG Keynote—How Jasper Formal Verification Technology Fits into the Cadence Flow

- Why Cadence Bought Jasper—A New Era in Formal Analysis

- Q&A: An R&D Perspective on Formal Verification—Past, Present and Future

As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some of those insights in a “fireside chat” with Ed Sperling, editor in chief of Semiconductor Engineering, at the Design Automation Conference (DAC 2015) on June 9.

Topics of this discussion included industry consolidation, the need for more talent and more startups, Internet of Things (IoT) opportunities and challenges, the shift from ICs to full product development, and the challenges of advanced nodes. Following are some excerpts from this conversation, held at the DAC Pavilion theater on the exhibit floor.

Ed Sperling (left) and Lip-Bu Tan (right) discuss trends in semiconductors and EDA

Q: As you look out over the semiconductor and EDA industries these days, what worries you most?

Tan: At the top of my list is all the consolidation that is going on. Secondly, chip design complexity is increasing substantially. Time-to-market pressure is growing and advanced nodes have challenges.

The other thing I worry about is that we need to have more startups. There’s a lot of innovation that needs to happen. And this industry needs more top talent. At Cadence, we have a program to recruit over 10% of new hires every year from college graduates. We need new blood and new ideas.

Q: EDA vendors were acquiring companies for many years, but now the startups are pretty much gone. Where does the next wave of innovation come from?

Tan: I’ve been an EDA CEO for the last seven years and I really enjoy it because so much innovation is needed. System providers have very big challenges and very different needs. You have to find the opportunities and go out and provide the solutions.

The opportunities are not just in basic tools. Massive parallelism is critical, and the power challenge is huge. Time to market is critical, and for the IoT companies, cost is going to be critical. If you want to take on some good engineering challenges, this is the most exciting time.

Q: You live two lives—you’re a CEO but you’re also an investor. Where are the investments going these days and where are we likely to see new startups?

Tan: Clearly everybody is chasing the IoT. There is a lot of opportunity in the cloud, in the data center. Also, I’m a big believer in video, so I back companies that are video related. A big area is automotive. ADAS [Advanced Driver Assistance Systems] is a tremendous opportunity.

These companies can help us understand how the industry is transforming, and then we can provide solutions, either in terms of IP, tools, or the PCB. Then we need to connect from the system level down to semiconductors. I think it’s a different way to design.

Q: What happens as we start moving from companies looking to design a semiconductor to system companies who are doing things from the perspective that we have this purpose for our software?

Tan: We are extending from EDA to what we call system design enablement, and we are becoming more application driven. The application at the system level will drive the silicon design. We need to help companies look at the whole system including the power envelope and signal integrity. You don’t want to be in a position where you design a chip all the way to fabrication and then find the power is too high.

We help the customers with hardware/software co-design and co-verification. We have a design suite and a verification suite that can provide customers with high-level abstractions, as well as verify IP blocks at the system level. Then we can break things down to the component level with system constraints in mind, and drive power-aware, system-aware design.

We are starting to move into vertical markets. For example, medical is a tremendous opportunity.

Q: How does this approach change what you provide to customers?

Tan: Every year I spend time meeting with customers. I think it is very important to understand what they are trying to design, and it is also important to know the customer’s customer requirements. We might say, “Wait a minute, for this design you may want to think about power or the library you’re using.” We help them understand what foundry they should use and what process they should use. They don’t view me as a vendor—they view me as a partner.

We also work very closely with our IP and foundry partners. We work as one team—the ultimate goal is customer success.

Q: Is everybody going to say, FinFETs are beautiful, we’re going to go down to 10nm or 7nm—or is it a smaller number of companies who will continue down that path?

Tan: Some of the analog/mixed-signal companies don’t need to go that far. We love those customers—we have close to 50% of that business. But we also have customers in the graphics or processor area who are really pushing the envelope, and need to be in 16nm, 14nm, or 10nm. We work very closely with those guys to make sure they can go into FinFETs.

We always want to work with the customer to make sure they have a first-time silicon success. If you have to do a re-spin, you miss the opportunity and it’s very costly.

Q: There’s a new market that is starting to explode—IoT. How real is that world to you? Everyone talks about large numbers, but is it showing up in terms of tools?

Tan: Everybody is talking about huge profits, but a lot of the time I think it is just connecting old devices that you have. Billions of units, absolutely yes, but if you look close enough the silicon percentage of that revenue is very tiny. A lot of the profit is on the service side. So you really need to look at the service killer app you are trying to provide.

What’s most important to us in the IoT market is the IP business. That’s why we bought Tensilica—it’s programmable, so you can find the killer app more quickly. The other challenges are time to market, low power, and low cost.

Q: Where is system design enablement going? Does it expand outside the traditional market for EDA?

Tan: It’s not just about tools. IP is now 11% of our revenue. At the PCB level, we acquired a company called Sigrity, and through that we are able to drive system analysis for power, signal integrity, and thermal. And then we look at some of the verticals and provide modeling all the way from the system level to the component level. We make sure that we provide a solution to the end customer, rather than something piecemeal.

Q: What do you think DAC will look like in five years?

Tan: It’s getting smaller. We need to see more startups and innovative IP solutions. I saw a few here this year, and that’s good. We need to encourage small startups.

Q: Where do we get the people to pull this off? I don’t see too many people coming into EDA.

Tan: I talk to a lot of university students, and I tell them that this small industry is a gold mine. A lot of innovation is needed. We need them to come in [to EDA] rather than join Google or Facebook. Those are great companies, but there is a lot of fundamental physical innovation we need.

Richard Goering

Related Blog Posts

- Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

- DAC 2015: Google Smart Contact Lens Project Stretches Limits of IC Design

- Q&A with Nimish Modi: Going Beyond Traditional EDA

Are they basically the same thing? I am trying to get as much experience with Allegro since a lot of jobs I am looking at right now are asking for Cadence Allegro experience (I wish they asked for Altium experience...). I currently have access to PCB Editor, but I don't want to commit to learning Editor if Allegro is completely different. Also walmart one, are the Cadence Allegro courses worth it? I won't be paying for it and if it's worth it, I figure I might as well use the opportunity to say I know how to use two complex CAD tools.

Hello, I am using Encounter 8.1. My mouse is working fine, but my keyboard is not working well in Encounter. I can type in some boxes, but in many boxes I cannot type. The binding key is also not responding. How do I fix this issue? Thanks.

Hi,

When I import the top level Verilog file generated by Genus into Virtuoso, the power pins are left unconnected. I tried different configurations in "Global Net Options" tab. However, nothing changed. 

The cell is imported with three views, namely functional, schematic, and symbol. In www krogerfeedback com functional view everything looks OK, that is the top level Verilog file. In schematic, I can see the digital cells but VDD and VSS pins of the blocks are not connected. In the symbol view there are no pins for VDD and VSS. 

On top, we are trying to implement a digital block into Virtuoso. The technology is TSMC 65nm. On Genus and Innovus, everything goes straight and layout is generated successfully.

Thanks.

For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

I have a file that list all the `defines that is used in the current design. This file (define.vh) is generated, like so :

`define MACRO_1 5

`define MACRO_2 1'h0

... etc

But in genus when I run the command

read_hdl define.vh

read_hdl -sv top.sv

The tool work as if the defines never get parsed and returns with unreferenced errors. How can I resolve this? Do I have to include 'define.vh' in all the design files?

Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an estimate before submitting jobs." The answer...(read more)

RF Enthusiasts, Come connect with Cadence RF experts and discover the latest advances in Cadence RF technologies, including Spectre RF at the IEEE International Microwave Symposium (IMS) 2014. This year, IMS will be held in Tampa, Florida. Cadence...(read more)

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase Noise Profiles . We now have an easier way to do this. Starting in MMSIM 13.1 , you can specify the phase noise as an instance parameter in Spectre sources, including...(read more)

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Hello,

I am in a need of a skill program to find all instances of a specific cell (Including Mosaics), throughout the hierarchy. The program should print the instance's name, xy coordinates at the top level, and extract a label name that is dropped on top of it. In case there is no label on top of the found instance, the program should print "No Label Found" in the report text file. This program aims to map PADs cells within top level.

I am using the below Cadence's solution to find instances and it works well. The missing feature is to identify LABELs that are on top of the found instances. 

I tried to use dbGetOverlap() function, within the below code, in few setups but it seems to fail to identify the existence of labels on top of the found instances.

For example: 

overlapLabel=dbGetTrueOverlaps(cv cadr(instBox) list("M1" "text"))

I am interested to add to the Cadence's solution below some code in order to identify labels on top of the found instances.

Any tip would be greatly appreciated.

Thanks,

Danny

--------------------------------------------------------

Hi,

I am running simulation in ADEXL and need a custom function for VIVA to apply same procedure to all signals saved in output. For instance, I have clock nets and I want to get all of them and look at the duty-cycle, edge rate etc.

It is a little more involved than about part since I have some regex and setof to filter before processing but if I can get all signals for current history, I can postprocess them later.

In ocean, I am just doing outputs() and getting all saved signals but I was able to do this in VIVA calculator due to the difficulties in getting current history, test name and opening result directory

thanks

yayla

Version Info:

ICADV12.3 64b 500.21

spectre -W =>

Tool 'cadenceMMSIM' Current project version '16.10.479'
sub-version  16.1.0.479.isr9

I have a top cell & need to revise all the instances' cellview & export top cell as a new GDS file.

So I write a SKILL code to do so and I find out it will be a little bit slow by using the dbSave to save the cellview of each instance.

Code as below:

let( (topCV subCV )
topCV = dbOpenCellViewByType(newLibName topCellName "layout" "maskLayout" "a")
foreach(inst topCV->instances
subCV = dbOpenCellViewByType(newLibName inst->cellName "layout" "maskLayout" "a")
;;;revise code content
;;;...
;;;revise code content
dbSave(subCV)
dbClose(subCV)
)
dbSave(topCV)
dbClose(topCV)
system(strcat( "strmout -library " newLibName " -topCell " topCellName " -view layout -strmFile " resultFolder "/" topCellName ".gds -techLib " srcLibName " -enableColoring -logFile " topCellName "_strmOut.log" ) )
)

Even if the cell content is not revised, the run time of dbSave will be 2 minutes when there are ~ 1000 instances in topcell. The exported GDS file size is ~2MB.

And the dbSave becomes the bottle neck of the code runtime...

Is there any better way to do such a thing? 

Hi there,

I'm running a transient simulation, and I want to get all instances with model implementation hisim_hv because after that I want to process the data and to adjust some parameters for this kind of devices before dumping the values.

What is the easiest/fastest way to get those instances in skill/ocean?

What I did until now: 

- save the final OP of the simulation and then in skill

openResults()
selectResults('tranOp)
report(?type "hisim_hv" ?param "vgs")

Output seems to be promising, and looks like I can redirect it to a file and after that I have to parse the file.

Is there other simple way? I mean to not save data to file and to parse it.

Eventually having an instance name, is it possible to get the model implementation (hsim_hv, bsim4, etc..)? 

Best Regards,

Marcel

It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we...(read more)

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There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced ...(read more)

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...(read more)

I'm trying to generate IBIS models for the parts that I'm designing.  I'm designing using CADENCE Virtuoso.  

I'm wondering if there is a tutorial for generating IBIS models in CADENCE Virtuoso.   Please pardon me if my question is broad.      

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The Linley Processor Conference always opens with a keynote by Linley Gwenapp giving an overview of processors in whatever is the hottest area. Most of the other presentations during the conference...

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We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro® Package Designer Plus layout tools allowing you to work...

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Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater at DAC bring you up to speed.

The technology behind AI isn’t as new as you’d think—the principles that govern how AI learns have been in development since 1959, when Arthur Samuel defined the concept of “machine learning.” At the time, there was nothing even resembling the necessary compute power to put Samuel’s concepts into practice—but now we can. AI designs are huge, and they’re massively parallel—simulating them on older computers and simulators would have taken ages; never mind how long it would take to do some by-hand measure like they had to do in the '60s.

But with advancements in server technology and the parallelization technology in products like Xcelium Parallel Logic Simulator and JasperGold smart technology, plus hardware-based engines like the Palladium and Protium platforms, verifying AI designs is not only possible—it’s easy.  But, read on, its not just about simulation technology.

AI tech is flooding the industry. It’s applicable to almost every vertical—cloud computing can use AI to intelligently manage a user’s required resources, consumer electronics are using it to tailor a user experience based on a whole host of collected data, automotive companies want to use AI to drive cars, healthcare to assist in diagnoses given a set of symptoms and a database of other, similar patients—and that’s saying nothing of the multitude of industrial applications. AI is also useful in the creation of developers’ tools themselves. Part of what’s causing the semiconductor industry boom is just this—an exploding interest in AI chips. And with 5G technology imminent, and with the looming billion-gate plus sizes of the SoCs that implement 5G, AI-assisted developers' tools might need to become the norm, not an outlier.

So: in all of this, where is Cadence?

Cadence is focusing its efforts on two areas, dubbed “machine learning inside” and “machine learning outside.” ML inside in the digital design flow refers to improving PPA, faster engines, and better testing and diagnostics. None of this physically affects how you use a tool, but it makes using that tool a much better experience. ML outside talks about the design flow in general, working toward an automated design flow, as well as productivity improvements across the flow. These things do change how you use a tool, but don’t worry, it’s all for the better.

Additionally, Cadence is working to improve design enablement; that is, hardware and software co-design. Smart Genus and Innovus solutions make designing your SoC easier than ever—using the full flow can result in up to a 21% PPA gain.

If you’re looking specifically for IP to enable AI on your SoC, the Tensilica DNA 100 processor has you covered, too. It’s great for companies designing edge or AI chips, offers great compression rates and efficient power usage, and has 4.7X the performance of other AI SoC IP on similar array sizes.

Cadence has you covered no matter where you’re going in this new world of AI systems—with our AI-enabled tools, IP,  and our strong partner ecosystem, you can be at ease knowing you’ll be supported no matter how complex your needs are.

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t h...(read more)

I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here. In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired by Horst Diewald, chief architect of MSP430^TM microcontrollers at Texas Instruments, the group's line-up is an impressive "who's who" of the microcontroller space, including Analog Devices, ARM, Atmel, Cypress, Energy Micro, Freescale, Fujitsu, Microchip, Renesas, Silicon Labs, STMicro, and TI.

As the press release explains, unlike usual processor benchmark suites which focus on performance, the ULP benchmark will focus on measuring the energy consumed by microcontrollers running various computational workloads over an extended time period. The benchmarking methodology will allow the microcontrollers to enter into their idle or sleep modes during the majority of time when they are not executing code, thereby simulating a real-world environment where products must support battery life measured in months, years, and even decades.

Processor performance benchmarks seem to be as widely criticized as EPA fuel consumption figures for cars - and the criticism is somewhat related. There is a suspicion that manufacturers can tune the performance for better test results, rather than better real-world performance. On the face of it, the task to produce meaningful ultra low power benchmarks seems even more fraught with difficulties. For a start, there is a vast range of possible energy profiles - different ways that computing is spread over time - and a plethora of low power design techniques available to optimize the system for the set of profiles that particular embedded system is likely to experience. Furthermore, you could argue that, compared with performance in a computer system, energy consumption in an ultra low power embedded system has less to do with the controller itself and more to do with other parts of the system like the memories and mixed-signal real-world interfaces.

EEMBC cites that common methods to gauge energy efficiency are lacking in growth applications such as portable medical devices, security systems, building automation, smart metering, and also applications using energy harvesting devices. At Cadence, we are seeing huge growth in these areas which, along with intelligence being introduced into all kinds of previously "dumb" appliances, is becoming known as the "Internet of Things." Despite the difficulties, with which the parties involved are all deeply familiar, I applaud this initiative. While it may be difficult to get to apples-to-apples comparisons for energy consumption in these applications, most of the time today we don't even know where the grocery store is. If the EEMBC effort at least gets us to the produce department, we're going to be better off.

Pete Hardee 

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release.  Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release.

When we talk about low-power verification its easy to equate it with simulation.  For certain, simulation is the heart of a low-power verification solution. Simulation enables engineers to run their design in the context of power intent.  The challenge is that a simulation-only approach is inadequate. For example, if engineers could achieve SoC quality by verifying the individual function of each power control module (PCM), then simulation could be enough.  For a single power domain, simulation can be enough. 

However, when the SoC has multiple power domains -- and we have seen SoCs with hundreds of them -- engineers have to check the PCMs and all of the arcs between the power modes.  These SoCs often synchronize some of the domain switching to reduce overall complexity, creating the potential for signal skew errors on the control signals for the connected domains.  Managing these complexities requires verification methodologies including advanced debug, verification planning, assertion-based verification, Universal Verification Methodology - Low Power (UVM-LP), and more (see Figure 1).

Figure 1:  Comprehensive Low-Power Verification 

But even advanced verification methodologies on top of simulation aren't enough.  For example, the state machine that defines the legal and illegal power mode transitions is often written in software. The speed and capacity of the Palladium emulation platform is ideal to verify in this context, and it is integrated with simulation sharing debug, UVM acceleration, and static checks for low-power. And, it reports verification progress into a holistic plan for the SoC.  Another example is the ability to compare the design in the implementation flow with the design running in simulation to make sure that what we verify is what we intend to build.

Taken together, verification across multiple engines provides the comprehensive low-power verification needed for today's advanced node SoCs.  That's the heart of this low-power verification announcement. 

Another point you may have noticed is the extension of the Common Power Format (CPF) based power-aware support in the Incisive Enterprise Simulator to IEEE 1801.  We chose to bring IEEE 1801 to simulation first because users like you sometimes need to mix vendors for regression flows.  Over time, Cadence will extend the low-power capabilities throughout its product suite to IEEE 1801.

If you are using CPF today, you already have the best low-power solution. The evidence is clear:  the upcoming IEEE 1801-2013 update includes many of the CPF features contributed to 1801/UPF to enable methodology convergence.  Since you already have those features in the CPF flow, any migration before you have a mature IEEE 1801-2013 tool flow would reduce the functionality you have today.

If you are using Unified Power Format (UPF) 1.0 today, you want to start planning your move toward the IEEE 1801-2013 standard.  A good first step would be to move to the IEEE 1801-2009 standard.  It fills holes in the earlier UPF 1.0 definition.  While it does lack key features in -2013, it is an improvement that will make the migration to -2013 easier. The Incisive 13.1 release will run both UPF 1.0 and IEEE 1801-2009 power intent today.

Over the next few weeks you'll see more technical blogs about the low-power capabilities coming in the Incisive 13.1 release.  You can also join us on June 19 for a webinar that will introduce those capabilities using the reference design supplied with the Incisive Enterprise Simulator release.

=Adam "The Jouler" Sherer

(Yes, "Sherilog" is still here.  :-) )

DAC is right around the corner! On the demo floor at Cadence® Booth #2214, we will demonstrate how to use the Cadence mixed-signal and low-power solution to design, verify, and implement a microcontroller-based mixed-signal design. The demo design architecture is very similar to practical designs of many applications like power management ICs, automotive controllers, and the Internet of Things (IoT). Cadene tools demonstrated in this design include Virtuoso® Schematic Editor, Virtuoso Analog Design Environment, Virtuoso AMS Designer, Virtuoso Schematic Model Generator, Virtuoso Power Intent Assistant, Incisive® Enterprise Simulator with DMS option, Virtuoso Digital Implementation, Virtuoso Layout Suite, Encounter® RTL Compiler, Encounter Test, and Conformal Low Power. An extended version of this demo will also be shown at the ARM® Connected Community Pavilion Booth #921.

For additional highlights on Cadence mixed-signal and low-power solutions, stop by our booth for:

• The popular book, Mixed-signal Methodology Guide, which will be on sale during DAC week!
• A sneak preview of the eBook version of the Mixed-signal Methodology Guide
• Customer presentations at the Cadence DAC Theater
  • 9am, Tuesday, June 4  ARM  Low-Power Verification of A15 Hard Macro Using CLP 
  • 10:30am, Tuesday, June 4  Silicon Labs  Power Mode Verification in Mixed-Signal Chip
  • 12:00pm, Tuesday, June 4  IBM  An Interoperable Flow with Unified OA and QRC Technology Files
  • 9am, Wednesday, June 5  Marvell  Low-Power Verification Using CLP
  • 4pm, Wednesday, June 5  Texas Instruments  An Inter-Operable Flow with Unified OA and QRC Technology Files
• Partner presentations at the Cadence DAC Theater
  • 10am, Monday, June 3  X-Fab  Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
  • 3:30pm, Monday, June 3  TSMC TSMC Custom Reference Flow for 20nm -  Cadence Track
  • 9:30am,Tuesday, June 4  TowerJazz   Substrate Noise Isolation Extraction/Model Using Cadence Analog Flow
  • 12:30pm, Wednesday, June 5  GLOBALFOUNDRIES  20nm/14nm Analog/Mixed-signal Flow
  • 2:30pm, Wednesday, June 5  ARM  Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-efficient Processors for Mixed-signal Applications
• Technology sessions at suites
  • 10am, Monday, June 3    Low-power Verification of Mixed-signal Designs
  • 2pm, Monday, June 3      Advanced Implementation Techniques for Mixed-signal Designs
  • 2pm, Monday, June 3      LP Simulation: Are You Really Done?
  • 4pm, Monday, June 3      Power Format Update: Latest on CPF and IEEE 1801  
  • 11am, Wednesday, June 5   Mixed-signal Verification
  • 11am, Wednesday, June 5   LP Simulation: Are You Really Done?
  • 4pm, Wednesday, June 5   Successful RTL-to-GDSII Low-Power Design (FULL)
  • 5pm, Wednesday, June 5   Custom/AMS Design at Advanced Nodes

We will also have three presentations at the Si2 booth (#1427):

• 10:30am, Monday, June 3   An Interoperable Implementation Solution for Mixed-signal Design
• 11:30am, Tuesday, June 4   Low-power Verification for Mixed-signal Designs Using CPF
• 10:30am, Wednesday, June 5   System-level Low-power Verification Using Palladium

We have a great program at DAC. Click the link for complete Cadence DAC Theater and Technology Sessions. Look forward to seeing you at DAC!     

ST Microelectronics reported their success with IEEE 1801 / UPF low-power simulation using Incisive Enterprise Simulator at CDNLive India in November 2013. We were able to meet with Mohit Jain just after his presentation and recorded this video that explains the key points in his paper.

With eight years of experience and pioneering technology in native low-power simulation, Mohit was able to apply Incisive Enterprise Simulator to a low-power demonstrator in preparation for use with a production set-top box chip.  Mohit was impressed with the ease in which he was able to reuse his existing IEEE 1801 / UPF code successfully, including the power format files and the macro models coded in his Liberty files. Mohit also discusses how he used the power-aware Cadence SimVision debugger.

The Cadence low-power verification solution for IEEE 1801 / UPF also incorporates the patent-pending Power Supply Network visualization in the SimVision debugger.  You can learn more about that in the Incisive low-power verification Rapid Adoption Kit for IEEE 1801 / UPF here in Cadence Online Support.

Just another happy Cadence low-power verification user!

Regards,

 Adam "The Jouler" Sherer 

Hello, i saw that MAESTRO is a plotting addon is it a part of ADE EXPLORER?

i cant see the relation between the two.i started to read manual and regarding MAESTRO i only see code.

is there some simple examples?
Thanks.

Hello, i have a realy mistick thing going with copying libraries in cadence virtuoso,

When i copy straight forwart the whole library it gives me a warning that accsess was denied,but when i go into the library and copy it as a single file, then it goes fine.

another problem is it doesnt show in the massage console  ALL the files which could not be copied.(which is the much bigger problem,becuase i would have to pass threw all the subdirectories to verify if all files are there)

Is there a way to see which files wasnt able to be copied?

Thanks. 

Hi,
I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response.

First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated.

Thanks,

-Rakesh.

Hello , i am trying to extract netlist from a circuit  in assembler

I have found the manual shown bellow , however there is no such option in tools in assembler.

how do i view the NETLIST of this circuit?

Thanks.

ASSEMBLER VIEW menu

Hello, I have a problem with a certain type of transistor,my hyrarchy has a lot components an sub components and visually inspecting them is very hard.

is there a way like in other cadence layout viewer tools , to enter the name of the component or a NET somewhere and it will focus on it visualy or give the hyrarchy path to it?

Thanks.

Hello

The document I referenced is https://filebox.ece.vt.edu/~symort/rfworkshop/Mixer_workshop_instruction.pdf. (This is cadence workshop document)

While following the pxf simulation in the above article, the results are different and I have a question.

My result picture is shown below.

<my result error>

<document result>

<my direct plot>

<document direct plot>

The difference with the documentation is that in the direct plot screen after the pxf simulation,

1.output harmonics-> input sideband

2.Frequency axis: out-> frequency axis: absin

3.The results for port0 (RF port) are also different (see photo below).

4.The frequency values in the box are different.

My screen shows 5G, 10G, 1K ~ 10M, but the document is the same as 1K ~ 10M.

Ask for a solution. Thank you.