science and technology VIVA Calculator function to get the all outputs and apply a procedure to all of them By feedproxy.google.com Published On :: Sat, 02 May 2020 01:24:40 GMT Hi, I am running simulation in ADEXL and need a custom function for VIVA to apply same procedure to all signals saved in output. For instance, I have clock nets and I want to get all of them and look at the duty-cycle, edge rate etc. It is a little more involved than about part since I have some regex and setof to filter before processing but if I can get all signals for current history, I can postprocess them later. In ocean, I am just doing outputs() and getting all saved signals but I was able to do this in VIVA calculator due to the difficulties in getting current history, test name and opening result directory thanks yayla Version Info: ICADV12.3 64b 500.21 spectre -W => Tool 'cadenceMMSIM' Current project version '16.10.479'sub-version 16.1.0.479.isr9 Full Article
science and technology Select all members of a constraint with SKILL By feedproxy.google.com Published On :: Mon, 04 May 2020 08:54:21 GMT I want to select a constraint, and then run a SKILL command that returns a list with the members of that constraint. Is this possible? Thx, Full Article
science and technology Displaying contents of a modeless dialog box during execution of a SKILL script By feedproxy.google.com Published On :: Tue, 05 May 2020 00:47:02 GMT I have a modeless informational dialog box defined at the beginning of a SKILL script, but its contents don't display until the script finishes. How do you get a modeless dialog box contents to display while a SKILL script is running? procedure(myproc() prog((myvars) hiDisplayAppDBox() ; opens blank dialog box - no dboxText contents show until script completes! ....rest of SKILL code in script...launches child processes );prog );proc Full Article
science and technology Default param values not saved in OA cell property. By feedproxy.google.com Published On :: Tue, 05 May 2020 06:34:40 GMT When I place a pcell and do not change the W parameter (default is used) the value is not saved in the OA cell property. When I change the default value of the super master now, the old pcell will get the new default value automatically because there is nothing saved inside the OA cell for this parameter. Do you have any Idea, that how we can save the default values in the OA cell properties so that this value doesn't get updated if the default values are updated in the new PDKs Full Article
science and technology Create the title & frame for view schematic By feedproxy.google.com Published On :: Tue, 05 May 2020 08:55:25 GMT Hi all, I want to write a script SKILL to create the title & frame for view schematic. My question is whether SKILL supports any function for me to do this. Best regards, Huy Hoang Full Article
science and technology How to save the cellview of all instances in a top cell faster? By feedproxy.google.com Published On :: Wed, 06 May 2020 06:47:41 GMT I have a top cell & need to revise all the instances' cellview & export top cell as a new GDS file. So I write a SKILL code to do so and I find out it will be a little bit slow by using the dbSave to save the cellview of each instance. Code as below: let( (topCV subCV ) topCV = dbOpenCellViewByType(newLibName topCellName "layout" "maskLayout" "a") foreach(inst topCV->instances subCV = dbOpenCellViewByType(newLibName inst->cellName "layout" "maskLayout" "a") ;;;revise code content ;;;... ;;;revise code content dbSave(subCV) dbClose(subCV) ) dbSave(topCV) dbClose(topCV) system(strcat( "strmout -library " newLibName " -topCell " topCellName " -view layout -strmFile " resultFolder "/" topCellName ".gds -techLib " srcLibName " -enableColoring -logFile " topCellName "_strmOut.log" ) ) ) Even if the cell content is not revised, the run time of dbSave will be 2 minutes when there are ~ 1000 instances in topcell. The exported GDS file size is ~2MB. And the dbSave becomes the bottle neck of the code runtime... Is there any better way to do such a thing? Full Article
science and technology How to get m0 layer info in a layout By feedproxy.google.com Published On :: Wed, 06 May 2020 11:27:53 GMT HI All, I am new to skill. My requirement is open layout get m0 layer cordinates in a layout dump info into a text file For example 2 input Nand, A,B output , vcc , vssx and internal net (n2) will be the m0 layers. I need info like in a text file. n2 co ordinate vssx (co ordinate) a (co ordinate) b (co ordinate ) . I found similar code in cadence form . Can you help me on this procedure(printPts()let( (type (cnt 0) (objList geGetSelSet()))foreach(obj objList ++cnt type = obj~>objType case(type ("inst" printf("%s %L at %L " type obj~>xy)) ("rect" printf("%s on layer %L at %L " type obj~>lpp obj~>bBox)) ("polygon" printf("%s on layer %L at %L " type obj~>lpp obj~>points)) ("path" printf("%s on layer %L at %L " type obj~>lpp obj~>points)) ("pathSeg" printf("%s on layer %L at %L " type obj~>lpp list(obj~>beginPt obj~>endPt))) ("label" printf("%s on layer %L at %L " type obj~>lpp obj~>xy)) (t printf("%s not defined " type)) ))printf("%n objects selected " cnt)); end of let); end of printPts Full Article
science and technology Skill code to disable all callbacks By feedproxy.google.com Published On :: Wed, 06 May 2020 11:40:02 GMT Can anybody assist with a Skill code /function to disable all callbacks Full Article
science and technology Highlight shapes info By feedproxy.google.com Published On :: Thu, 07 May 2020 19:10:02 GMT I could not find info about the highlight shapes/layers in the cadence doc directory, forum, support library. I have a script that creates highlight shapes on the y* drawing layer. My understand is the highlight is a virtual shape. The shapes go away when the cadence session is closed or when you close data of that cellview if it is not global. If they are vitual shapes it would be okay to use valid or process layers when I create the highlight set with geCreateHilightSet. Ex: ( The command I use to create the hiighlight set geCreateHilightSet(cv list(lay purp) nil) ) Current y0-9 drawing To N-P_implant drawing Paul Full Article
science and technology Parasitic node coordinates By feedproxy.google.com Published On :: Thu, 07 May 2020 20:15:50 GMT Howdy, In the netlist generated after parasitic extraction, nodes have been added at fracture points to add parasitic devices. For example, in the image below, I'm referring to the nodes IN#1 and IN#2. Is there a way to determine their co-ordinates relative to the layout co-ordinate system? I could not find them in the Skill command reference and when I query the parasitic elements in the extracted view, it gives the graphical pin locations of the elements rather than the physical. Thanks Audi Full Article
science and technology Choices in radio field to be displayed in two rows By feedproxy.google.com Published On :: Fri, 08 May 2020 16:28:25 GMT Hi, I am trying add multiple choices to my radio field in cdf parameters. when i see the select the instance and try editing the Instance properties I can not view them in a single window. Instead i get a vertical sliding bar. Is there a way to display them in multiple rows? -Haareeth Full Article
science and technology skill ocean: how to get instances of type hisim_hv from simulation results? By feedproxy.google.com Published On :: Fri, 08 May 2020 20:46:12 GMT Hi there, I'm running a transient simulation, and I want to get all instances with model implementation hisim_hv because after that I want to process the data and to adjust some parameters for this kind of devices before dumping the values. What is the easiest/fastest way to get those instances in skill/ocean? What I did until now: - save the final OP of the simulation and then in skill openResults()selectResults('tranOp)report(?type "hisim_hv" ?param "vgs") Output seems to be promising, and looks like I can redirect it to a file and after that I have to parse the file. Is there other simple way? I mean to not save data to file and to parse it. Eventually having an instance name, is it possible to get the model implementation (hsim_hv, bsim4, etc..)? Best Regards, Marcel Full Article
science and technology ddDeleteObj() and its warnings By feedproxy.google.com Published On :: Sat, 09 May 2020 13:54:06 GMT Hello, After deleting cells using the following loop: foreach(cellId ddGetObj(libName)~>cells ddDeleteObj(cellId) ) the following warnings are printed in the CIW: *WARNING* (SCH-2162): "... symbol" has been updated since "... schematic" was last saved. Validate that the schematic is correct and run Check and Save to suppress this warning.*WARNING* (DB-270337): dbGetInstHeaderMaster: Failed to open cellview '...' from library '...' in read-only mode because the cellview does not exist. This cellview was instantiated in cellview '...' of library '...'. Ensure that the cellview exists in the library. Is it possible to turn them off? Thank you Best regards, Aldo Full Article
science and technology When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC to Enable Machine Learning By feedproxy.google.com Published On :: Fri, 29 Sep 2017 19:59:59 GMT As the stakes for winning server segment market share grow ever higher an increasing number of companies are seeking to grasp the latest Holy Grail of multi-chip coherence. The approach promises to better enable applications such as machine learning...(read more) Full Article SoC verification perspec system verifier Accellera pss portable stimulus
science and technology Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AMBA5 By feedproxy.google.com Published On :: Thu, 12 Oct 2017 22:05:00 GMT It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we...(read more) Full Article iwb interconnect amba5 Interconnect Workbench Palladium Performance Analysis AMBA CoreLink xcelium ARM
science and technology Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3 of 3) By feedproxy.google.com Published On :: Mon, 16 Oct 2017 08:10:00 GMT Here we conclude the blog series and highlight the results of Mediatek 's use of Cadence Perspec™ System Verifier for their SoC level verification. In case you missed it, Part 1 of the blog is here , and Part 2 of the blog is here . One of their key...(read more) Full Article uvm Perspec coherent perspec system verifier coherency library coherency Accellera mediatek ARM pss portable stimulus
science and technology Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey By feedproxy.google.com Published On :: Fri, 01 Dec 2017 22:48:00 GMT It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com. There were 33 user responses in favor of Perspec as the #1 tool, and dr...(read more) Full Article
science and technology Portable Stimulus User Gives Perspec PSS Technology Nearly Perfect Review By feedproxy.google.com Published On :: Mon, 08 Jan 2018 09:01:00 GMT It’s always good to hear what real users think of products. Here is a very detailed review (~4000 words) by an Anonymous user, nick named Ant-Man (from the movie). Overall it’s a very strong endorsement of Perspec, and summarize...(read more) Full Article
science and technology Cadence Collaborates with Test & Verification Solutions on Portable Stimulus By feedproxy.google.com Published On :: Thu, 18 Jan 2018 15:01:00 GMT The Cadence® Connections® Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. The program members help customer accelerate the adoption of new...(read more) Full Article CDNLive Test DVcon pss verification
science and technology Preparing Accellera Portable Stimulus Standard for Ratification By feedproxy.google.com Published On :: Tue, 13 Mar 2018 15:35:00 GMT The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process forward towards ratification. While we can't predict exactly when it will be ratified, the goal is now more clearly in sight! Cadence booth was busy with a lo...(read more) Full Article pswg Perspec perspec system verifier pss portable stimulus
science and technology What’s Hot in Verification at this Year’s CDNLive? It’s Portable Stimulus Again! By feedproxy.google.com Published On :: Tue, 27 Mar 2018 21:23:00 GMT CDNLive is a user conference, and verification is one of the largest categories of content with multiple tracks covering multiple days. Portable stimulus is one of the hottest new areas in verification, and continues to be popular in all venues. At l...(read more) Full Article CDNLive Perspec pss portable stimulus
science and technology AMIQ and Cadence demonstrate Accellera PSS v1.0 interoperability By feedproxy.google.com Published On :: Thu, 12 Jul 2018 00:04:00 GMT There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced ...(read more) Full Article Perspec perspec system verifier AMIQ Accellera pss portable stimulus
science and technology Perspec Portable Stimulus Hands-On Workshop at DAC 2018 By feedproxy.google.com Published On :: Fri, 20 Jul 2018 22:54:00 GMT Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...(read more) Full Article Perspec AMIQ pss portable stimulus
science and technology Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application By feedproxy.google.com Published On :: Thu, 16 Aug 2018 22:17:00 GMT Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and...(read more) Full Article
science and technology Willamette HDL and Cadence Develop the Industry's First PSS Training Course for Perspec System Verifier By feedproxy.google.com Published On :: Sat, 01 Dec 2018 01:20:00 GMT Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...(read more) Full Article whdl Perspec perspec system verifier willamette hdl Accellera pss portable stimulus Accellera PSS
science and technology Verification Reflections on 2018 By feedproxy.google.com Published On :: Thu, 20 Dec 2018 15:57:00 GMT In my predictions for 2018 I had identified five key trends driving verification in 2018 – Security, Safety, Application Specificity, Processor Ecosystems and System Design Enablement, all centered around ecosystems. Looking back now as the yea...(read more) Full Article security functional safety verification
science and technology DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety, Security and More By feedproxy.google.com Published On :: Wed, 29 May 2019 23:45:00 GMT Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more) Full Article security 5G DAC DAC2019 prototyping palladium z1 Safety tortuga logic Protium Emulation ARM AI
science and technology Cashing the PSS Promises By feedproxy.google.com Published On :: Sun, 08 Dec 2019 16:10:00 GMT A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...(read more) Full Article uvm CDNLive Acceleration virtual prototypes Perspec perspec system verifier Emulation DVcon Accellera System Design & Verification pss portable stimulus verification
science and technology detecting duplicate shapes By feedproxy.google.com Published On :: Thu, 04 Jul 2019 07:41:49 GMT Is there any way I can find duplicated shapes? I would like to find two or more shapes are identical and they are placed in the same location. Full Article
science and technology Generating IBIS models in cadence virtuoso By feedproxy.google.com Published On :: Wed, 04 Sep 2019 20:25:36 GMT I'm trying to generate IBIS models for the parts that I'm designing. I'm designing using CADENCE Virtuoso. I'm wondering if there is a tutorial for generating IBIS models in CADENCE Virtuoso. Please pardon me if my question is broad. Full Article
science and technology Visibility to "component value" property in Edit/Properties dialog? By feedproxy.google.com Published On :: Thu, 12 Sep 2019 18:59:09 GMT Hi, I want to add values to components in my SiP design such as 1nF or 15nH. There is already in existence a COMP_VALUE property reserved for this as shown during BOM generation. This property is not visible under the Edit/Properties dialog for component or symbol find filters. We have already created user properties called COMP_MFG and COMP_MFG_PN that it editable at a component level. When we try to add COMP_VALUE it is reported as a reserved name in Cadence but this name is not listed in the properties dialog. Is there a way to turn on the visibility and editablility of this or other hidden reserved Cadence property names? How can I assign a string value to the COMP_VALUE property? Thanks Full Article
science and technology Chiplet Interface for Heterogeneous SiP By feedproxy.google.com Published On :: Thu, 17 Oct 2019 07:38:18 GMT https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/cowos-info I came across cadence old article that discussing about TSMC advance packaging technology such as InFO & CoWoS. However, I couldn’t find information such as what I/O interface standard is required to realize this multi-chip SiP. For example, Intel using their proprietary AIB interface for EMIB solution. Besides, any idea if inFO also able to supports multi-chip integration for older node process to new node process such as 40-nm to 16-nm? Full Article
science and technology About Degassing Hole By feedproxy.google.com Published On :: Thu, 05 Dec 2019 02:08:06 GMT I use "Degassing" function in APD. It provides the options "Even Layers" and "Odd Layers". My first question is that is there any additional setting to choose the specific layer? The second question is that is there any way to select a range to place degassing hoe? I don't want to place holes at the whole layer. Thanks! Full Article
science and technology SIP to Allegro pcb designer 17.2 ver By feedproxy.google.com Published On :: Tue, 28 Jan 2020 13:25:18 GMT Iam new to Package design SIP tool. I had created the DIE package using SIP. Kindly give the direction how to map the created DIE package in Allegro pcb editor 17.2 ver. In Allegro design capture CIS tool we had created the schematics file. The DIE which we are using is having 100pins, We had created the DIE in SIP tool. Out of 100 Die pins, only 90 pins is getting connected others are NC pins. We had mapped the Bond fingers only for 90 Die pins in the SIP package. But in the Schematics we had created the DIE logic symbol for 100 pins. Please advice whether we can able to import the DIE package in the allegro tool. In this scenario while importing the 100 pin DIE package in allegro pcb editor will the net connectivity will be shown from the DIE pad to Bond fingers and from Bond fingers to respective components? Please suggest whether we are going in the right path or please advice what we have to proceed with. Thanks in Advance, Rajesh Full Article
science and technology Unable to add wire bond finger from die pins By feedproxy.google.com Published On :: Wed, 29 Jan 2020 11:54:40 GMT I have created a die and other components as symbols in sip and placed the symbols in sip through logic import capture netlist. It shows net connectivity but i couldn't add bond finger from the die pins. Please help on this. Full Article
science and technology How to check a cluster of same net vias spacing, with have no shape or cline covered By feedproxy.google.com Published On :: Fri, 14 Feb 2020 04:12:15 GMT Hi all, I have a question regarding the manufacture : how to check a cluster of same net vias spacing, with have no shape or cline covered Full Article
science and technology BoardSurfers: Allegro In-Design Impedance Analysis: Screen your Routed Design Quickly By community.cadence.com Published On :: Tue, 28 Apr 2020 13:12:00 GMT Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints,... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology IC Packagers: Shape Connectivity in the Allegro Data Model By community.cadence.com Published On :: Tue, 28 Apr 2020 13:14:00 GMT Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology RAMAC Park and the Origin of the Disk Drive By community.cadence.com Published On :: Wed, 29 Apr 2020 12:00:00 GMT Did you know that there is a park in San Jose named after a disk drive? Actually, technically it is named after the first computer that used disk drives. You couldn't just go and buy a disk drive... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology My Journey - From a Layout Designer to an Application Engineer By community.cadence.com Published On :: Wed, 29 Apr 2020 14:41:00 GMT Today, we are living in the era where whatever we think of as an idea is not far from being implemented…thanks to machine learning (ML) and artificial intelligence (AI) entering into the... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis By community.cadence.com Published On :: Wed, 29 Apr 2020 15:00:00 GMT In this week’s Whiteboard Wednesdays video, Dave Apte discusses how to create the lowest power design possible by using architectural exploration and Cadence’s Stratus HLS solution.... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology 1G Mobile: AMPS, TOPS, C-450, Radiocom 2000, and All Those Japanese Ones By community.cadence.com Published On :: Thu, 30 Apr 2020 12:00:00 GMT You can't read anything about technology these days without reading about 5G. But before there was 5G, there was 4G. And before that 3G, 2G, and 1G. A 0G even. For the next few Thursdays,... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Specman’s Callback Coverage API By community.cadence.com Published On :: Thu, 30 Apr 2020 14:30:00 GMT Our customers’ tests have become more complex, longer, and consume more resources than before. This increases the need to optimize the regression while not compromising on coverage. Some advanced... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Library Characterization Tidbits: Recharacterize What Matters - Save Time! By community.cadence.com Published On :: Thu, 30 Apr 2020 14:50:00 GMT Recently, I read an article about how failure is the stepping stone to success in life. It instantly struck a chord and a thought came zinging from nowhere about what happens to the failed arcs of a... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Start Your Engines: AMSD Flex – Your Instant Access to Latest Spectre Features! By community.cadence.com Published On :: Fri, 01 May 2020 06:59:00 GMT Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Linley Processor Conference 2020 Keynote By community.cadence.com Published On :: Fri, 01 May 2020 12:00:00 GMT The Linley Processor Conference always opens with a keynote by Linley Gwenapp giving an overview of processors in whatever is the hottest area. Most of the other presentations during the conference... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology 2019 HF1 Release for Clarity, Celsius, and Sigrity Tools Now Available By community.cadence.com Published On :: Fri, 01 May 2020 21:20:00 GMT The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads . SIGRITY2019 HF1 For information about supported platforms, compatibility... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Sunday Brunch Video for 3rd May 2020 By community.cadence.com Published On :: Sun, 03 May 2020 12:00:00 GMT www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: EDA101 Video Tuesday: Weekend Update Wednesday: RAMAC Park and the Origin of the Disk Drive Thursday: 1G Mobile: AMPS, TOPS, C-450,... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Signoff in the Cloud By community.cadence.com Published On :: Mon, 04 May 2020 12:00:00 GMT Here's a nightmare. You sign off your design with the usual margins. It is a 7nm chip that is meant to run at 3GHz. But it only runs at 2.7GHz. You get Cadence to help you work out what is going... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article
science and technology Wally Rhines: Predicting Semiconductor Business Trends After Moore's Law By community.cadence.com Published On :: Tue, 05 May 2020 12:00:00 GMT I recently attended a webinar presented by Wally Rhines about his new book, Predicting Semiconductor Business Trends After Moore's Law . Wally was the CEO of Mentor, as you probably know. Now he... [[ Click on the title to access the full blog on the Cadence Community site. ]] Full Article