Hello All,

I'm a novice to this forum and probably this subject has been already discussed here.

My company has purchased OrCAD Capture 17.4 tools that have a new GUI if compared to my earlier used OrCAD Capture 9.2. I have been using Capture 9.2 for ~18 years and its GUI is really convenient. The GUI of 17.4 looks to be a modern one with new icons and really has improved features and new capabilities.

However, my main complain about GUI 17.4 is that the schematic windows cannot be cascaded. Although they can be set floating, this is even more annoying because all toolbars remain in the Capture window and when you select a tool, the Capture window pops over already open schematic window and you need a lot of useless extra clicks to return back to the currently edited schematic page. I always used cascading of schematic windows before because my complex designs includes many pages, not speaking about the library windows that are typically open simulatneously. My view is that the lack of CASCADING in Capture GUI 17.4 is critical and unacceptable for complex projects, and I would very highly appreciate if the Cadence guys will return back the CASCADING capability for schematic pages. In case this will be done, this will make the GUI really great and comfortable to use.

Does anybody have opinion on this issue?

Many thanks,

Pavel

hello,

We have a number of workstations with version 17.2 that work on a floating license server

We want to know if it can be upgraded to version 17.4

If so, should the floating license server be upgraded as well?

In addition, how can you know where the license was purchased from?

Thanks!

Hello,

A mybe silly question came to my mind: When routing sense lines, is it better to hav them as close as possible to DUT or afer the decoupling capacitors ?

Force in red, sense in purple.

Best way is 1 or 2 ?

Thanks in advance and Merry Christmas to everybody !

Hi,

I found that under the Dark Theme of PCB Environment Editor 17.4,

the window background is not all dark, resulting in unclear text display。

As shown in the figure below：

Hi

In the environment I'm currently working, axes are shown for schematic, symbol, and layout views.For schematics and symbols, I'd prefer a dim gray, such that the axes are just visible but not dominant. For the layout, I'd prefer a brighter color. Is there a way to realize this? So far when I change the color of the 'axis' layer in the display resource editor, the axes in all three views get changed together:

Thanks very much for your input!

Dear all,

I defined two design variables in ADE Assembler, say V1 and V2, that define the voltage 1 and voltage 2 of a "vpulse" voltage source in my schematic.

Then, I define V1 = 1.0, and V2 = 2.0, run a transient simulation, and everything is as expexcted. The source provides pulses between 1.0 V and 2.0 V.

Next, I set V1 = 1.0:0.5:1.5, thereby creating a parametric sweep with 1.0 V and 1.5 V for V1. I keep V2 at 2.0 V. Then the simulation fails, and all I get is "netl err" in my Output Expressions and an error message that the results directory does not exist and nothing can be plotted: This is reasonable, as the results directory is deleted on starting a new simulation, and as there is no simulation result, none of my output expressions can be plotted.

WARNING (OCN-6040): The specified directory does not exist, or the directory does not contain valid PSF results.
        Ensure that the path to the directory is correct and the directory has a logFile and PSF result files.
WARNING (ADE-1065): No simulation results are available.
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.

Normally, this kind of para,metric sweep is not a problem, I have done this many times before. There must be something special in THIS PARTICULAR test bench or simulator setup. The trouble is, I don't get any useful error messages.

Does anyone know what might be the problem here OR where to find useful information to investigate further (log files stored somewhere)? Thank you!

Regards,

Volker

P.S. Using Corners instead does not help either. Running it through all values by hand works, though.

Hi,

I have a LEF file with simple definitions of pad design which uses M8, M9, and AP layers. However, I failed to import the design with CIW > Import > LEF... as I encountered "ERROR: (OALEFDEF-90019): Ignoring the line 30 in the layer map file ... as it contains a syntax error. Each entry in the layer map file must have two values, LEFLayerName and OALayerNumber separated by a blank space." All lines in the file report the same OALEFDEF-90019 error.

The tech.layermap file looks like this:


# techLayer       techPurpose     stream# dataType

ref drawing 0 0
DNW drawing 1 0
PW drawing 2 0

IC 23.1-64b.ISR8.40

Hi all, I'm trying to run an stb analysis in a dspf extracted view via Probe terminal. The instance exist in the dspf and I already prepended the X that is placed in the dspf extraction.

Spectre complains with the following error:

Error found by spectre during STB analysis `stb'.
    ERROR (SPECTRE-16408): The probe parameter must be specified to perform stability analysis.

Analysis `stb' was terminated prematurely due to an error.

What is missing here?

Dear community

We would like to have more minimalistic and customized sheet borders for our schematics. I used this guide to create a starting point. Essentially, I made a copy of the US_8ths library and modified the Title symbol to look something like that:

Problem 1

The variable ilInst~>libName points to the library of the sheet border symbols, not to the library of the schematic. How do I need to modify this field in order to see the library name of the schematic where the border is instantiated?

Problem 2

The function CCSgetCreator() was taken from here. This solution does not seem to work with our management toll (we use VersIC); the function always returns nil as value. What is the simplest way to display the name of the user that created the schematic? A custom field that could be filled manually would also do the job for us; it doesn't need to be something that automatically fetches data from a database system.

Thanks for any input.

I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics.

Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va),  mod2 (inside an external file mod2.va),  and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module.

At the bottom of the module I use "`include mod1.va", "`mod2.va", etc.

When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning:

Warning from spectre during AHDL compile.
WARNING (VACOMP-1047): The Verilog-A file contains more than one module
definition. ADE can process only one module per Verilog-A file. Put
only one module in each Verilog-A file so that ADE can identify pin
names, directions, and hierarchy within each separate module.

Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored?

Hello,


I would like to use the simulation software xrun/simvision that comes with XCELIUM. We are currently using classroom licenses and want to disable all ip addresses on the student pcs except the license server ip. We want to make sure that students cannot copy confidential data from the Cadence tools.


Problem:

When I launch the xrun simulation while all ip addresses are blocked, it starts but the performance is very slow. The GUI starts after 5 minutes and the simulation is ready after 10 minutes. The interesting thing is that when I enable all blocked ip addresses, everything works at a reasonable speed.

Terminal Output (execution without internet connection):

xrun -gui design.vhd

waiting for SimVision/Verisium Debug to connect...


Is there a way to run the simulation tools without an Internet connection? Or can you give me the ip addresses that are used by the simulation tools so that I can enable only those specific ips?


Regards,

Max

Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Hello everyone, 
I have a testbench for generating s2p files from a SP simulation that was working until few months ago. Today I have reopened (w/o making changes that I am aware of) and I get the error as shown below:

first I show the testbench settings:

notice how the s2p generation is disabled: the field "file" is left blank

in the corner I defined some parameters, "filename" is the word that is suppose to generate the name for the s2p. 

where the two variables are defined as follows

And now the output log:

spectre.out file gives the following error:


When clicking on the error message at "9", the input.scs file opens up and the line 9 gets highlighted in green



now, so far I understood that the problem seem to be related tom the "pathcds" variable, but I really don't understand what the error message here means, since I don't see any error in the input.scs file

by the way - if for instance I define the variable "filename" as shown below, then I get no errors:

thanks
Tommaso

Hi,

I'm searching for a way to get a quick overview of too low cpk-values after a montecarlo sim. The non-MC results have the spec and thus the easy/understandable red/green/(yellow) colorcoding, but for MC sims I don't get a highlight for high variations inside the limits.

Is this possible (besides copying each expression into avg()+3*std()) and ..-..)?

It would be really handy to scan through finished sims...

(My final application is then to export the table for my reports and documentation...)

Regards,

leo

Hi

I have a rather strange question - is there a way to tell layout XL to NOT place the error/warning markers on a design when I open a cell?  I do a lot of my layout by using arrays from placed instances and create mosaics that completely ignore the metadata that Layout XL uses with its bindings with schematic (and instances get deleted etc. but I do like using it to generate all my pins etc.) and it's just really annoying when I open a design that I know is LVS clean and since the connectivity metadata is all screwed up (because I did not use it to actually complete the layout) I have a design that's just blinking at me at every gate, source and drain.  I typically delete them at the high level heirarchically but the second I go in and modify something and come back up it places all of them again.  I know that if I flatten all the p cells it goes away but sometimes it's nice to have that piece of metadata but that's about it.  Is there a way to "break" the features of XL like this?  I realize what a weird question this is but it's becoming more of an issue since we moved to IC 23 from IC 6 where there is no longer a layout L that I can use free from these annoyances that can't use any of the connectivity metadata.

Thanks

Chris

Hello everyone,

I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process.

My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run.

I would really appreciate it if you could guide me on the following:

1. How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2.
2. Where to specify view priorities or other settings to control which view is used during simulation.
3. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches.

Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views.

Thank you so much for your time and assistance!

Hi,

Do anyone know if it's possible in simvision waveform viewer to see a timestamp of where uvm_errors/$errors occurred in a simulation via post-processing? 

Cheers,

Antonio

I want to use jaspergold to formally verify functionality of my custom multiplier. I am computing the expected result using A*B to check against output of my multiplier. Here, A and B are two logic signed operands. However, jaspergold is performing the operation A*B incorrectly.

I have reproduced this issue using the attached example. JasperGold compiles and elaborates the module and subsequently runs a formal proof. The tool raises a counterexample to assertion whose screenshot is attached below:

I simulated the same example using xrun and it was giving the correct product output in simvision waveform. Please help me resolve this issue. I am using 2023.03 version of Jasper Apps.

Thanks and regards

Anubhav Agarwal

I'm trying to use Jasper for checking parameter propagation in a large design. I have a list of top-level parameters, each with a HDL path of a module parameter somewhere lower in the hierarchy that's supposed to receive its value from the top-level module. The FPV app seems like an excellent tool for this, but elaborating the entire design in it is extremely time-consuming and memory-intensive. So, I'm trying to black-box everything but the interesting HDL paths. I thought using `elaborate -top dut_module_name -bbox_i * -no_bbox_i inst_foo -no_bbox_i inst_bar (...)` would work, but it doesn't. Jasper just starts flooding the log with warnings from modules that are definitely not on the whitebox list, and eventually dies due to insufficient memory. When I use -bbox_m * it correctly elaborates the top-level module with all of its sub-modules black-boxed. But then the -no_bbox_i switches have no effect. Could anyone suggest a working solution for this use case?

Hello,

I have been running this `uvm_reg_hw_reset_seq` sequence for the AHB protocol. My UVM Adapter looks like:

Issue: When I use basic reg.write, my write access are working well, as that is managed by the driver i.e. once adapter gives the packet to the driver, the driver supplies the address and the control signals to the DUT on the first clock cycle and then the write data on the next clock cycle. But when I am performing the read operation, somehow the UVM adapter is reading the data at the same clock cycle where read address + Controls are supplied and this is triggering read failure messages from the `uvm_reg_hw_reset_seq` sequence. What should I modify in the driver/sequencer/adapter so that the UVM adapter can read the data on the next cycle instead of the same clock cycle.

Just FYI: The waveforms of the read operation are correct, it is just the Adapter and the `uvm_reg_hw_reset_seq`. The AHB Driver + AHB Monitor is fully proven and verified to be working correctly.

I exported vplan to .odf file in vManager and after editing it I imported it to vManager. The vplan was expected to be synchronized and updated. However, nothing has changed to it. Does anyone know why?

When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:

# A fatal error has been detected by the Java Runtime Environment:
#
#  SIGSEGV (0xb) at pc=0x00007efc52861b74, pid=14182, tid=18380
#
# JRE version: OpenJDK Runtime Environment Temurin-17.0.3+7 (17.0.3+7) (build 17.0.3+7)
# Java VM: OpenJDK 64-Bit Server VM Temurin-17.0.3+7 (17.0.3+7, mixed mode, sharing, tiered, compressed oops, compressed class ptrs, g1 gc, linux-amd64)
# Problematic frame:
# C  [libucis.so+0x238b74]

......

For more details please refer to the attached log file "hs_err_pid21143.log".

Two approaches were tried to solve this problem but neither has worked.
Method.1:

Setting larger heap size of Java process by "-memlimit" options.For example "vmanager -memlimit 8G".

Method.2:

Enlarging stack memory size limit of the Coverage engine by setting "IMC_NATIVE_STACKSIZE" environment variable to a larger value. For example "setenv IMC_NATIVE_STACKSIZE 1024000"

According to "hs_err_pid*.log" it is almost certain that the memory overflow triggered Java's CrashOnOutOfMemoryError and caused Verisium Manager to crash. There are some arguments about memory management of Java like "Xms, Xmx, ThreadStackSize, Xss5048k etc" and maybe this problem can be fixed by setting these arguments during analysis. However, how exactly does Verisium Manager specify these arguments during analysis? I tried to set them by the form of setting environment variables before analysis but it didn't work in analysis and their values didn't change.

Is there something wrong with my operation or is there a better solution?

Thank you very much.

I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code covered grade, block covered grade, statement covered grade, expression covered grade, toggle covered grade.

As I dont know the difference I started to read the IMC user guide and came to know there are 3 things we come across while doing a code coverage local, covered, average

From my understanding

local - child instances metrics doesnt reach the parent level. For example, we have an instance Q and its sub instances like Q.a, Q.b. Block Local grade of Q can be 100% even when its instances Q.a and Q.b a block local grades isnt at 100%.

In the attached image there is formula 

The key difference between average and covered is the weights.

Average : Mathematically taking the above scenario where Q.a, and Q.b has 10 blocks each. Q.a has covered 8 blocks and q.b has covered 2 blocks. Now if we take the normal average it should be total covered/ totatl number = 8+2/10+10 yielding 50%. But when we add weights saying Q.a is 70% and Q.b is 30% the new number would be (8*0.7+2*0.3) / (10*0.7+10*0.3) resulting 62%. Because of the weights we see 12% bump.

Covered: there is no role of weights.

Among these 3 metrics i've changed my default view to this in the image to get more realistic picture when i do analyze metrics. Do you guys agree with the approach?

Hello,

I have a question about toggle coverage.

In my case, there are many unused registers or wires that are affecting the toggle coverage score negatively.

Is it possible to automatically exclude registers or wires that are not used from toggle coverage?

My RTL code is as follows, Is it possible to automatically disable tb.top1.b and tb.top1.c without using an exclude file?

module top1;

  reg a;

  reg b;

  reg [31:0] c;

  initial

  begin

  #1 a=1'b0;

  #1 a=1'b1;

  #1 a=1'b0;

  end

endmodule

module tb;

  top1 top1();

endmodule

Hi, I'm using the xcelium simulator to simulate a testbench, in which I first stimulate my design to do something (part "A") and then do a direct follow-up test on the design (part "B").

I need two things from this testbench: the results of the test (part "B", passed/failed) and coverage information, but the coverage information should only include part A and explicitly not part B.

I could do the following: run the testbench with part A and B, get the "passed/failed" result of the test and then follow up another simulator run with another testbench, that only includes part A and get the coverage information from that simulation run.

Is there a way to force xcelium to give me the coverage information of only a part of the simulation? Ideally, I would like to write the verilog code of my testbench to look something like this:

• do A
• dump coverage information
• do B

But maybe there is another way to tell xcelium to consider only part of the testbench for the coverage information. I did have a look at the manual, but was not able to find something useful for this problem. Any ideas?

I am running simulation in gui mode using Indago and every time there is UVM_ERROR occur simulation stops. I have to resume it manually. is there any way to disable this feature. 

Hello,

First, I had something working that broke in the past few versions that I've been meaning to get working again. There was some setting I recall in the GUI that allowed me to have inputs be placed in the waveform viewer with yellow traces, and output signals with orange traces to match the name colors. How can I set this to happen in the .simvisionrc file?

Second, I would like to add something to my .simvisionrc file to go through foreach signal and depending on key locations based on the signal's Path.Name (mainly the model and design areas) such that if the path contains "mon", then to auto-set the trace and name colors to something such as cyan. I'd like to have loops for various key areas of the design to color-code the signals.

Third, I am interested if there is a possibility of coloring names/traces foregound colors to based on which position they are in the waveform viewer to make banding, ideally such that every three (or whatever) are one color (or a color mutation, adding some gray to signals colorized by the auto-coloring mentioned already, etc) that allows for the signal names/traces to be colorized along with the built-in optional black/gray background banding.

Thanks in advance

Hi

I have tried using "add net constraints" command to place one-cold constraints on a tristate enable bus. In the command line we need to specify the "net pathname" on which the constraints are to be enforced.

The bus here is 20-bit. How should the net pathname be specified to make this 20-bit bus signals one_hot or one_cold.

The bus was declared as follows:
ten_bus [19:0]

The command I used was

add net constraints one_hot /ren_bus[19]

What would the above command mean?
Should we not specify all the nets' pathnames on the bus?
Is it sufficient to specify the pathname of one net on the bus?
I could not get much info regarding the functionality of this command. I would be obliged if anyone can throw some light.

Thanks
Prasad.

When posting code to the forums, copy from a text editor such as notepad, not from word or Outlook. Be sure to click the HTML tab BEFORE you paste your text.

Click on the "html" mode tab on your "reply" dialog box. Then wrap your text with like this:

pasted text

NOTE: Do not put a space in the I have done that here so it will show up as text. Also, be sure to click the HTML tab BEFORE you paste your text. This is how it will look when coded correctly pasted text

The two macros below introduce new syntax for adding definitions to more than one 'when' determinant value at the same time. The first macro overloads 'extend' keyword and the second is the equivalent for 'when' keyword.

A use example:

extend [HUGE, BIG] packet {
    // definitions that pertain to these subtypes
};

The above code would be expanded in the following (naive) way:

extend HUGE packet {
    // definitions that pertain to these subtypes
};
extend BIG packet {
    // definitions that pertain to these subtypes
};


The macros code:

define 'statement>
       "extend ['name>,...] 'name> ({;...})" as computed {
    for each in 'names> do {
        result = appendf("%sextend %s %s %s;",result,it,'name>,);
    };
    result = appendf("{%s}",result); // required only for versions 6.1.1 or earlier
};

define 'struct_member>
       "when ['name>,...] 'name> ({;...})" as computed {
    for each in 'names> do {
        result = appendf("%swhen %s %s %s;",result,it,'name>,);
    };
    result = appendf("{%s}",result); // required only for versions 6.1.1 or earlier
};

Hello All,

starting with version 8.1 the contents of the ce_tools directory will no longer
be shipped with Specman. The directory contains some unsupported AE/R&D
ware and has not been updated for several releases (i.e. most of those old
packages don't work with the latest release).
 
Attached is the contents of this directory. Please read the README before
using any of the packages.


Regards,
-hannes

Please include a brief summary of how to use it.

Hi, I am uploading a register class, which can be used for modeling hardware registers. I am uploading the source code and examples on how to run it. I also have a user guide which has all the APIs listed and explained. The user guide is ARV.pdf in the attached tar file. I have named the class ARV, which stands for Architect's Register View. It has got very good randomization and coverage features. Users have told me that its better than RAL. You can download it from http://verisilica.info/ARV.php
. There is a limit of 750KB in this cadence website. The ARV file is 4MB. That is why, I am uploading it at this site. I have a big pdf documentation and a doxygen documentation there. That is the reason for the bigger file size. The password to open the ZIP file is ovm_arv. I hope, everyone will use these classes.

Please contact me for any help.
Regards ANil

I've heard lots of people asking for a way to generate Makefiles for Specman code, and it seems there are some who don't use "irun" which takes care of this automatically. So I wrote this little utility to build a basic Makefile based on the compiled and loaded e code.

It's really easy to use: at any time load the snmakedeps.e into Specman, and use "write makefile <name> [-ignore_test]".
This will dump a Makefile with a set of variables corresponding to the loaded packages, and targets to build any compiled modules.
Using -ignore_test will avoid having the test file in the Makefile, in case you switch tests often (who doesn't?).

It also writes a stub target so you can do "make stub_ncvlog" or "make stub vhdl" etc.

The targets are pretty basic, I thought it was more useful to #include this into the main Makefile and define your own more complex targets / dependencies as required.

The package uses the "reflection" facility of the e language, which is now documented since Specman 8.1, so you can extend this utility if you want (please share any enhancements you make).

 Enjoy! :-)

Steve.

Hi everybody,

The attached package is a tiny code example with a demo for an upcoming Team Specman blog post about writing macros.

Hilmar

In a nutshell, tags allows you to navigate through program code distributed over multiple files effectively. e.g if you see a function call or a struct in e-code and want to "jump" to the definition (which may be in a different file) then you just hit CTRL+] in Vim! Pressing CTRL+t will take you back where you came from. Check out http://vim.wikia.com/wiki/Browsing_programs_with_tags#Using_tags if you want to learn more about how to use tags with Vim.

This utility can generate tags file for your e files. It can either walk through e import order, a directory recursively or all directories on SPECMAN_PATH recursively! The tags file will have tags for struct, unit, types, events, defines, fields, variables, etc.

For help and some examples, just run ctags4e -help.

ncsim will consume an increasing ammount of memory when a function has an output port that return an associative array which was not initialized. My simulator version is 12.10-s011.

Below is a code example to reproduce the failure. The code is inside a class (uvm_object):

function void a_function(output bit ret_val[int]);

// empty 

endfunction : get_cov

Attached is the latest emacs mode for e/Specman - version 1.23

Please follow the install instructions in the top section of the actual file
(after unzipping it) to install/load this package with your emacs.

Can anyone tell me how i can supress few strings or integers while reading with $sscanf.

I read a line from a file into a string. there are few strings and integers seperated by white spaces in the line. I am interested in one string which comes at postion 5 in the line. how can i suppress all other strings and integers with $scanf.

i tried the following syntax but it dint work.

 $sscanf(line,"* * * * %s",string_arg);

i am tring to supress first 4 integers/strings in the line.

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

  data :uint(bits:16);
  opcode :uint(bits:16);
  !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
  event data_e;
  event opcode_e;

  cover data_e is {
     item data using radix = HEX, ranges = {
     //I dont want to write all of this
     range([0], "My range1");
     range([10], "My range2");
     //... many values in between
    range([700], "My rangen");
    };

    item opcode;

   cross data, opcode;
};

post_generate() is also {
    emit data_e;
};
};

Hi all, I've trained a device model with the approach of an artificial neural network, and it shows well fit. 

May I know how to transfer the trained model to Verilog-A, so that, we can use this model to do circuit simulation?

And I've searched for some lectures that provide the Verilog-A code in the appendix, but I'm freshman in the field of Verilog-A, 

could anyone tell me each statement? such as

real hlayer-w[0:(NI*NNHL)-1   

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Hello Team,
I am currently following this AWR script posted on them, to run a python script directly from inside AWR using VBA script.

Launching Python from AWRDE VBA Script - AWR Scripts - AWR Knowledgebase

Following all the basic steps with no changes to the code. I have Vscode and python-3.12.2 installed in my system. 

This is the error I am getting while running this code. 

Thank you for your help 

Best Regards

SID

Hi, in EMX I'm trying to define the ports of a CPW line as suggested in one document of the support area (i.e. P1:Gright,Gleft). The EMX simulation works fine. When I generate the schematic, I get this:

Basically, the two ground ports of each end of the CPW are properly defined as a unique node (e.g. G2_1, G2_2). 

However, when I try a simulation I get this error: 

I hope you can help me. Thanks.

Hi, newbie here.

We are using AWR Design Enviroment in our university and so I have to install it (OS: Arch Linux)
I installed it in a Windows 10 VM without problems.

When I try to start it prompts "Failed to connect to license server", I guess thats the first problem.

After that when trying to generate my SUL License it will prompt Internal Error -8 (see Image)

I can't find something on Error -8 :/ and overall the available data to the license topic is quit low :/

If someone has a solution for that I would gladly hear about it :)