Hi,

My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2

I have an expression where the EvalType is "sweeps". Here is the expression (I also attached the snapshot):

(peakToPeak(leafValue(swapSweep(delay(?wf1 clip((VT("/clk0") - VT("/clk180")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value1 0 ?edge1 "rising" ?nth1 1 ?td1 0 ?tol1 nil ?wf2 clip((VT("/tx_padp") - VT("/tx_padn")) (VAR("mt_stop") - (4.0 / VAR("datarate"))) VAR("mt_stop")) ?value2 0 ?edge2 "rising" ?nth2 1 ?tol2 nil ?td2 nil ?stop nil ?multiple nil) "VDD_FIXED_NOISE") "VREGLN_cmode" 0.85 "VREGDRV_novn" 0.4 "datarate" 1.658e+10) ?overall t) / 10.0)

What this expression does is that it compares the delay between the output data with respect to a reference clock. I then get this information for two conditions (VDD_FIXED_NOISE = 0 or 10mV) to get the effect of the supply-induced jitter. In the expression, I need to give the value of each parameter in different modes to distinguish them from each other. Now I want to sweep the base supply values and see the supply variation effects. For example, I want to change VREGLN_cmode from 0.85 to 0.81 and see how my supply-induced jitter changes. For that, the hard way is to copy the expression and change that value accordingly (e.g. "VREGLN_cmode" 0.81). I'm looking for an easier way to use a variable in the expression. Something like VAR("VREGLN_Sweep"). But I see it doesn't work in my expression and it gives an eVal error. I tested this before in other expressions (not sweep type) and it always worked. I have only one test and these variables are all Design Variables and not Global variables.
I want to know what mistake am I doing here and is there a way to make this work. Sorry that if I could not explain better my inquiry. Thank you.

Hello, Currently i am designing a 96MHZ crystal oscillator using pierce topology and also I use for amplitude gain control circuit for regulation. The problem is when i run a PSS + Pnoise i get these warnings :

WARNING (CMI-2375): M2: Vgs has exceeded the oxide breakdown voltage of `vbox' = 6 V.
WARNING (CMI-2375): M4: Vgs has exceeded the oxide breakdown voltage of `vbox' = 6 V.
WARNING (CMI-2377): M4: Vgd has exceeded the oxide breakdown voltage of `vbox' = 6 V.
WARNING (CMI-2377): M3: Vgd has exceeded the oxide breakdown voltage of `vbox' = 6.6 V.

and also WARNING (CMI-2682): M5: The bulk-drain junction forward bias voltage (1.38154 V) exceeds VjdmFwd'=851.514mV ,The results are now incorrect because the junction current model has been linearized

Note : i am using Supply 1.2 V hence it is not possible to exceed the oxide breakdown. 

So i am asking why i am getting these warnings , it could be a convergence problem and the Results computed are not corrected.

Also when running DC and transient , i don't get these warnings.

Hi, 
In the MATLAB, I am using cds_srr and cds_innersrr commands. Although I set the path to the spectre root, I face this error:

One or more output arguments not assigned during call to "cds_innersrr".

Error in cds_srr (line 20)
sig = cds_innersrr(dirname, dataset, signame, verbose);

Error in techsweep_spectre_run (line 64)
struct_n = cds_srr(c.outfile, c.sweep, params_n{1});

I would highly appreciate it if you could help me.

Hi,

In our design team, we're looking for a strategy to make all cell views self-contained. We are struggling to do so when nport devices are involved.

The nport file requires a full path, whereas what we need is a relative path to the current path of the cell in which we're using the nport.

I have browsed through the forums & cadence support pages, but could not find a solution.

1) There is a proposal from Andrew to add the file directory in ADE option "Simulation Files." :https://community.cadence.com/cadence_technology_forums/f/rf-design/27167/s-parameter-datafile-path-in-nport . This, however, is not suitable, because the cell is not self contained.

2) The new cadence version off DataSource "cellView" in nport options:

This however is not suitable for us due to two reasons:

i- Somehow we don't get this option in the nport cell (perhaps some custom modification from our PDK team)

ii- Even if we had this option, it requires to select the library, which again makes it unsuitable: We often copy design libraries for derivative products using "Hierarchical Copy" feature. And when the library is copied, the nport will still be pointing to the old library. Thus, it is still not self-contained.

In principle, it should not be difficult (technically) to point to a text file relative to the cell directory (f.ex we can make a folder under the same cell with name "sparFiles" & place all spar files under this folder), however it does not seem to be possible.

Could you perhaps recommend us a work-around to achieve our goal: making the cells which contain nport devices self-contained so that when we copy a cell, we do not have to update all the nport file destinations ?

Thanks in advance.

My Cadence Version: IC23.1-64b.ISR4.51

My Spectre version: 23.1.0.362.isr5

Hi *,

I am simulating a 32kHz high Q crystal oscillator with a pulse shaping circuit. I set up a PSS analysis using the Shooting Newton engine. I set a beat frequency of 32k and used the crystal output and ground as reference nodes. After the initial transient the amplitude growth was already pretty much settled such that the shooting iterations could continue the job.

My problem is: In 5...10% of my PVT runs the simulator detects a frequency divider in the initial transient simulation. The output log says:

Frequency divided by 3 at node <xxx>

The Estimated oscillating frequency from Tstab Tran is = 11.0193 kHz .

However, the mentioned node is only part of the control logic and is always constant (but it has some ripples and glitches which are all less than 30uV). These glitches spoil my fundamental frequency (11kHz instead of 32kHz). Sometimes the simulator detects a frequency division by 2 or 3 and the mentioned node <xxx> is different depending on PVT - but the node is always a genuine high or low signal inside my control logic.

How can I tell the simulator that there is no frequency divider and it should only observe the given node pair in the PSS analysis setup to estimate the fundamental frequency? I have tried the following workarounds but none of them worked reliably:

- extended/reduced the initial transient simulation time

- decreased accuracy

- preset override with Euler integration method for the initial transient to damp glitches

- tried different initial conditions

- specified various oscillator nodes in the analysis setup form

By the way, I am using Spectre X (version 21.1.0.389.ISR8) with CX accuracy.

Thanks for your support and best regards

Stephan

Hello everybody,

As you can find in the attached image, I am trying to simulate a Colpitts oscillator. However, using pss analysis it shows a high output power. 

My question is where is the problem of my structure or simulation setup?

Best,

Hello everyone,

I am trying to perform a load pull simulation of a transistor to verify some gain calculations I made using its S-parameters. Specifically, I have calculated the optimal conjugate impedances for the input and output to later calculate the power dissipated and transmitted in each stage of the transistor. Then, I only varied the output impedance and recalculated these powers, noticing that the power delivered to the load is lower.

Now, what I want to do is simulate this behavior using the Load Pull simulation. I have taken the model shown in the image, but I believe it is a linear model. My question is: if the chosen model is linear, is the load pull simulation accurate? In the calculations I made, nonlinearities are not considered. I don’t want to take nonlinearities into account.

In short, do you have any ideas on how to verify the calculations made with the transistor’s S-parameters through a load pull simulation?

Can you recommend any transistor model that is nonlinear and also has an S-parameter file?

Thank you very much in advance.

While adding an element created from a netlist file in AWR, I am getting the error 'The element type being dropped is not compatible with the window it is being dropped into'. The netlist file in AWR has the following contents:

.subckt BFG520W base collector emitter npn
.model BFG520W NPN(IS=1.016E-15 NF=1.000 BF=220.1 IKF=510E-3 VAF=48.06
+ ISE=2.83E-13 NE=2.035 NR=0.988 BR=100.7 IKR=2.352E-3
+ VAR=1.692 ISC=24.48E-18 NC=1.022 RB=10.00 RE=0.7753
+ RC=2.21 CJC=447.6E-15 MJC=0.07 VJC=0.1892
+ CJE=1.245E-12 TF=8.616E-12 TR=5.437E-12 mfg=NXP)

I have attached screenshots of the element BFG520W2 created due to the above netlist and the error I am getting while adding this element.

Hello everyone,

For my cross-coupled oscillator design, I have a problem with stability analysis. Based on my achieved results which are attached, where is my design problem?

Best,

https://ibb.co/bgKFP4N

https://ibb.co/3FGRLmV

https://ibb.co/pwSZDSF

Hi everyone,

I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS).

In ADS, I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane.

Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing

Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have:

1. Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue?

2. Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance?

Any insights would be greatly appreciated. Thank you in advance for your help!

Hi I noticed that some figures from the old posts in the cadence blogs have been missing.

I think this problem happened before and Andrew Beckett asked the original author to fix the issue:

 Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" 

Some of these posts are quite valuable, and would be nice to have access to the figures, which are a very important part of some posts,

Thanks

Leandro

Hello Everybody

Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size

I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance

Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)

But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA

I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)

I have no idea how to solve this problem, please help me! Thank you very very much!

Sample clues

18 across: Makoto Hagiwara and David Jung both claim to have invented it (7,6)

1 down: French impressionist who rejected that term (5)

3 down: Artificial surface used for playing hockey (9)

7 down: The sequel to Iliad (7)

12 down: Adipose tissue (4,3)

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6 across: Franchise revived by Frank Miller (6)

13 across: What Keanu Reeves and Zayed Khan have in common (5)

18 across: What Frank Sinatra and George Clooney have in common (6,6)

19 across: Dosa mix, for example (6)

2 down: Green, in a non-environmental way (7)

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5 down: Torso covering (6)

7 down: Government by rogues (12)

15 across: eBay speciality (7)

18 across: Demonic (8)

20 across: Common language (6,6)

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17 across: Beckham speciality (4,4)

4 down: Havana speciality (5)

19 across: Infamous 1988 commercial against Michael Dukakis (9,4)

11 down: Precisely (2,3,3)

13 down: City infamously ransacked by the Japanese in 1937 (7)

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11 across: Chandigarh’s is 0172 (3,4)

21 across: He’s a loser, baby (4)

1 down: Garment meant to shape the torso (6)

12 down: It’s slogan: “Life, Liberty and the Pursuit” (8)

18 down: Noise made by badminton players? (6)

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Sample clues

5 across: The US president’s bird (3,5,3)

11 down: Group once known as the Quarrymen (7)

10 across: Cavalry sword (5)

19 across: Masonic ritual (5,6)

1 down: Pioneer of Ostpolitik (6)

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Sample clues

14 across: FDR’s baby (3,4)

1 down: A glitch in the Matrix? (4,2)

4 down: Slanted character (6)

5 down: New Year’s venue in New York (5,6)

16 down: Atmosphere of melancholy (5)

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Sample clues

6 across: Alejandro González Iñárritu’s breakthrough film (6,6)

19 across: Soft leather shoe (8)

7 down: Randroids, for example (12)

12 down: First American World Chess Champion (7)

17 down: Circle of influence (5)

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Sample clues

5 across: Robbie Robertson song about Richard Manuel (6,5)

2 down: F5 on a keyboard (7)

10 across: Lionel Richie hit (5)

3 down: ALTAIR, for example (5)

16 down: The problem with Florida 2000 (5)

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Sample clues

9 across: Van Morrison classic from Moondance (7)

6 down: Order beginning with ‘A’ (12)

6 across: Fatal weakness (8,4)

19 across: Rolling Stones classic (12)

4 down: Massacre tool (8)

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Read through this blog to know more about the new Reliability Report view in Virtuoso ADE Assembler and Virtuoso ADE Explorer.(read more)

Concurrent Layout Editing enables more than one designer to work in a hierarchy at the same time. Check out this blog to know more. (read more)

I am trying to figure out the most efficient workflow for adding test points. My use case involves adding ~100 or so SMT pads at the bottom for bed-of-nails ICT test that are required to be on a test point grid. A lot of the nets are on the top or from inner layers and so have to be brought to the bottom using stubs. I'm used to Xpediiton workflow of being able to set a test point padstack, set a test point grid, and then select a net, add the test point to the bottom layer on the grid with that net attached and then route the stub with gridless routing.

In Orcad, it seems I need to route the stub, switch layer pairs to be both bottom once I bring the stub to the bottom and then change the grid to be the test point grid and then add the test point on the grid. It requires a lot of clicks, very mistake prone requiring lots of oops and very slow for 100+ test points to be brought out at the bottom. 

I'm sure there is a better way that is used by folks with a lot of Orcad experience. Any suggestions?

I am using OrCAD PCB Designer Standard version 17.4-2019. I want to force update the Package_Height_Max property on the place bound top shape. The footprint library that we've created has that property set in the dra file, but I'd like to override that from capture so I can be certain that the height is correct.

This is coming from a place where we have created a very large footprint library over that past ++ years. Everyone who creates a new footprint is supposed to make sure that we add Package_Height_Max to the footprint, but of course footprints get reused for various parts, not all of which will have the same package height. What I want to do is export a list of package heights from our part database and then import the package heights into Capture and override the package height in the footprint.

I have found a post here  Using Height Property from Orcad Capture which says its not possible, but it also says its from 15 years ago, so maybe things have changed?

Loading new netlist into 23.1 Apparently it does not like many of the specified footprints or padstacks. I have to open the footprint in 231., save the pad stack then save the footprint. This is very time consuming and frustrating to say the least.

I also get the following message

WARNING(SPMHNI-194): Symbol 'SMD_SOD123_ANODE_PIN1' used by RefDes D30 for device 'DIODE_0_SMD_SOD123_ANODE_PIN1_1N4148W-7-F' not found.

The symbol either does not exist in the library path (PSMPATH) or is an old symbol from a previous release.  

Set the correct library path if not set or use dbdo

     The current version of software is unable to open design smd_sod123_anode_pin1.

The design was last saved using version 16.5 and must be updated using DB Doctor. [help]


Going to DB Doctor does nothing, no option to update a footprint?

Tom

hello:

i place a symbol into my design.

on my design, i change the symbol property by unlocking the symbol and unfixing pins so that i can move pins on the symbol.

i move some pins on my design.

but when i export the symbol from my design, the symbol is not current but has the original pin location.

is there a way to retain the pin locations after moving pins on a symbol when exporting the symbol?

regards

masa

Any tips or SKIL files to help create a thermal shaped openings for paste masks for a donut shaped pin for mics or stand-offs like below?

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Hai Community,

I have a PCB board which has multiple high speed nets and I want to perform the EMI and EMC checking.

Which Cadence tool should I use for checking the EMI and EMC coupling?

Regards,

Rohit Rohan

Dear Community,

In OrCAD X Profession, the workspace feature enables the users to store the libraries (Schematic Symbol, Footprint and PSpice Models) and Designs (Schematic and PCB layout) in the cloud workspace.

But storing these libraries and design are stored in servers in the USA, Europe, Asia and Japan Servers.

I don't want to store my designs in any of these servers instead I want to create the workspace in my local PC and store all my libraries and designs in the local workspace.

Is this possible, if possible then can anyone provide the steps/procedure or videos of how to do it?

Regards,

Rohit Rohan

Dear Community,

I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional.

Regards,

Rohit Rohan

Hai Community,

What are the differences between the Cadence OrCAD / Allegro 24.1 with the Altium Designer 24.

Can I get the grid matrix difference between these two tools?

Regards,

Rohit Rohan

Optimizing PCB thermal performance is essential in today’s high-density designs, as it ensures stability, prolongs component life, and prevents potential thermal issues. One of the first steps to achieving this is with strategic component placement. Positioning high-power components—such as regulators, power transistors, or processors—away from heat-sensitive parts can prevent thermal interference, and placing them near the edges of the PCB often helps dissipate heat more effectively. It’s also beneficial to group components by their heat generation, creating dedicated thermal zones that can manage localized heating and reduce impact on other areas of the board.

Using thermal vias is another effective technique. By placing thermal vias under components like BGAs or power ICs, heat can be transferred from the surface to internal layers or ground planes. Increasing the size and number of these vias, or using thicker plating, enhances heat conductivity and helps manage heat more evenly across layers in multilayer boards. Increasing copper thickness on the PCB also has a major impact. Opting for thicker copper layers (e.g., 2 oz or even 3 oz copper) significantly boosts the heat dissipation capabilities of power planes and traces, especially in high-current areas. Large copper planes, such as dedicated ground or power planes, are equally effective in spreading heat efficiently. Adding thermal pads directly beneath heat-generating components improves this heat distribution.

Thermal relief pads help regulate heat flow for through-hole components by controlling heat transfer, which reduces thermal stress during soldering and prevents excessive heat spread to nearby sensitive areas. Performing thermal analysis with software tools like Celsius can be invaluable, as it allows you to simulate and model heat distribution, spot potential thermal issues, and refine your design before finalizing it.

Using heat sinks and thermal pads provides a direct way to draw heat from high-power components. Heat sinks can be attached with thermal adhesives, screws, or clamps, while thermal interface materials (TIMs), such as thermal pads or conductive adhesives, further reduce thermal resistance, enhancing heat-transfer efficiency. Optimizing the PCB layer stackup is also a key factor. Dedicated ground and power layers improve heat conduction across the PCB, enabling heat transfer between layers, particularly in high-density and multilayer PCBs.

In designs with high power requirements, active cooling options like fans, blowers, or heat pipes can be essential, helping to direct airflow across the PCB and further improving heat dissipation. Adding ventilation slots around hot zones and considering passive cooling paths enhance natural airflow, making the design more thermally efficient. By combining several of these techniques, you can create a PCB that handles heat effectively, resulting in a robust, long-lasting, and reliable product.

Let us know if you’ve had any challenges with thermal management in your designs—I’d be glad to discuss further!

Training Bytes are not just short technical videos; they are particularly designed to provide comprehensive support in understanding and learning various concepts and methodologies.

These comprehensive yet small Training Bytes can be created to show various concepts and processes in a shorter pane of five to ten minutes, for example, running DFT synthesis, scanning insertion, inserting advanced testability features, test point insertion, debugging DFT violations, etc.

In this blog, we will show you the DFT Synthesis Flow with Cadence's Genus Synthesis Solution using small Training Bytes available on the Cadence Learning and Support Portal. To explore these training bytes more, log on to support.cadence.com and select the learning section to choose the training videos, as shown below.

DFT Synthesis Flow with Genus Synthesis Solution

First, we will understand the Synthesis Flow with DFT in the Genus Synthesis Solution:

Understanding a Script File that Used to Run the Synthesis Flow With DFT

Here, we will show you "How to run the Test Synthesis Flow to Insert Scan Chains and Improve the Testability of a Design" in the Genus Synthesis Solution:

Running Test Synthesis Flow to Insert Scan Chains And Improve the Testability of a Design in the Genus Synthesis Solution

Let's check the flops marked with the dft_mapped attribute for scan mapping in Genus Synthesis Solution:

How to Check Flops Marked With dft_mapped Attribute For Scan Mapping in Genus Synthesis Solution?

How to Find Non-Scan Flops of a Design in Genus? (Video)

Once the flops are mapped to scan flip flops and the scan chain inserted, we will see how to handle the flops marked with the dft_dont_scan attribute for scan mapping in Genus Synthesis Solution.

How to Handle the Flops Marked With the dft_dont_scan Attribute For Scan Mapping in Genus Synthesis Solution?

Here, we will see how to fix DFT Violations using the command fix_dft_violations:

Fixing DFT Violations (Video)

Once the design has been synthesized, let's explore the DFT design hierarchy in Genus Stylus CUI:

Exploring DFT Design Hierarchy in Genus Stylus CUI (Video)

Understand why sequential elements are not mapped to a scan flop:

Why Are Sequential Elements Not Mapped to a Scan Flop?

Explore hierarchical scan synthesis in Genus Stylus Common UI:

Understanding Hierarchical Scan Synthesis in Genus Stylus Common UI. (Video)

To understand how to resolve different warnings and errors (for example, DFT-415, DFT-512, DFT-304, etc.) in Genus Synthesis Solution, here are some videos you can refer to:

How to Resolve Warning: DFT-415 (Video)

How to Resolve Error: DFT-407 (Video)

How to Resolve Error: DFT-404 (Video)

DFT-510 Warning During Mapping (Video)

How to Resolve Warning: DFT-512 (Video)

How to Resolve Warning: DFT-511 (Video)

How to Resolve Warning: DFT-304 (Video)

How to Resolve Warning: DFT-302 (Video)

How to Resolve Error: DFT-515 (Video)

How to Resolve Error: DFT-500 (Video)

Here, we will see how we can generate SDC constraints for DFT constructs for many scan insertion techniques, such as FULLSCAN, OPCG, Boundary Scan, PMBIST, XOR Compression, SmartScan Compression, LBIST, and IEEE 1500:

How to Generate SDC Constraints for DFT Constructs in Genus Synthesis Solution? (Video)

Explore advanced testability features that can be inserted in Genus Synthesis Solution, such as Boundary Scan, Programmable Memory built-in Self-Test Logic (PMBIST), Compression Logic, Masking, and On-Product Clock Generation Logic (OPCG):

Advanced Testability Features (Video)

To understand What the IEEE 1500 Wrapper and its Insertion Flow in Genus Synthesis Solution, follow the bytes:

What Is IEEE 1500 Wrapper? (Video)

IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution (Video)

Understand the On-product Clock Generation (OPCG) insertion flow in Genus Synthesis Solution Stylus CUI with this byte:

Understanding On Product Clock Generator (OPCG) Insertion in Genus Stylus CUI (Video)

To debug DFT violations, you can use DFT Analyzer from Genus GUI and explore its features here:

Debugging Using GUI: DFT Analyzer (Video)

Exploring DFT Analyzer View of Genus Synthesis Solution GUI (Video)

To understand What is Shadow Logic, How to Insert Test Points, How to do Testability Analysis Using LBIST, and How to Deterministic Fault Analysis in Genus, follow this article:

What is Shadow Logic

To insert the Boundary Scan Logic in and control Boundary Optimization in Genus Synthesis Solution, refer to these small bytes:

How to Insert Boundary Scan Logic in Genus? Video)

Controlling Boundary Optimization in Genus Synthesis Solution Stylus CUI (Video)

Compression techniques are used during scan insertion to reduce the test data volume and test application time (TAT) while retaining the test coverage. To understand what compression and the compression techniques are, watch this article:

What is Compression Technique During Scan Insertion? (Video)

Interested to know what "Unified Compression" is? To get the concept, you can watch this small demo:

What Is Unified Compression? (Video)

To Explore More, Register for Online Training

• Log on to Cadence.com with your registered Cadence ID and password.
• Select Learning from the menu > Online Courses.
• Search for "Test Synthesis with Genus Stylus Common UI" using the search bar.
• Select the course and click "Enroll."

A more appropriate title for this blog could be “All Vehicles with ADAS Need the Midas Functional Safety Platform”.

EVs tend to have advanced driving assistance systems (ADAS) because they’re newer, but not all vehicles with ADAS are EVs!

Certifying Advanced Driver Assistance Systems (ADAS) is a multifaceted process involving rigorous testing, validation, and regulatory compliance to ensure safety and reliability.
As ADAS technologies become increasingly sophisticated, the certification process is evolving to meet these challenges.

The ISO26262 standard provides the requirements to be met to attain safety certification for digital designs.

One of the key aspects of ADAS certification is functional safety. This includes:

• Ensuring the system operates as intended under all conditions, including failures.
• Adherence to standards like ISO26262.
• Rigorous testing to identify potential hazards and mitigate risks.

The Midas Safety Platform provides early-phase exploration of functional safety architectures and leverages native chip design data to perform accurate safety analysis efficiently.

The platform is a unified solution available across Cadence products, and with its modular architecture, it supports both embedded and standalone usage with the Cadence flow.

After extracting the design information, an output Midas database file contains the isolated DUT and provides the design components and their fault tolerances to various tools in the flow.

Conformal can easily verify design transformations that include necessary components like TMR for safety.

In these videos, we explore how to create reports for both Transient and Permanent faults.

Creating Detailed FMEDA in Midas (Video)

Creating Architectural FMEDA in Midas (Video) 

Also, read this blog post for additional motivation: What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

What Next?

Join the Midas Safety Platform Introduction and the Functional Safety Implementation and Verification with Midas trainings and learn more about:

• Setting up and defining the USF file
• Using the Midas Safety Platform to create functional safety reports, and
• Midas integration with the Genus  Synthesis Solution, Innovus  Implementation System, and Conformal Equivalence Checker tools to implement functional safety

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Please don't forget to obtain your Digital Badge after completing the training. Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust, making you and your projects even more successful.

If you want to make sure you are always the first to know about anything new in training, then you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Power efficiency is a critical factor in the fast-evolving world of semiconductor design.

The IEEE 1801 standard, also known as UPF (Unified Power Format), was developed by the IEEE to address the intricate challenges associated with power management in contemporary semiconductor designs. This standard offers a uniform framework for defining power domains, power states, and power intent, ensuring consistency across diverse tools and phases of the design process. By utilizing UPF, you can precisely model and regulate power consumption, a critical aspect for battery-operated devices, high-performance computing, and energy-efficient designs.

The key concepts of IEEE 1801 are:

1. Power domains
2. Power states
3. Power gating and isolation
4. Power switches
5. Level shifters, isolation, and retention cells
6. Macro model

Based on these building blocks, you write the power intent of the design.

The power intent for the design includes identifying/implementing low-power strategies that provide a clear description of the power architecture of a design.

The power definitions can effectively manage power consumption and ensure the chip meets its power and performance requirements.

You can start by creating the Power Supply Network, which defines how power is supplied to the design's various power domains and logic cells.

What's the next step to build the file? How do you understand the various concepts related to IEEE 1801? How do you complete the rest of the power intent file?

Relax!

Gear up to attend the training class created just for you to dive deep into the entire format and explore this exciting power specification method/format with hands-on labs in one day!

Training

Fundamentals of IEEE 1801 Low-Power Specification Format Training

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various flow stages, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth, using Cadence^® tools.

Labs

We ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

Now, the exciting part is that to help you further, we have created engaging videos of the training labs. You can refer to the lab module's instructions in demo format at https://support.cadence.com.

Lab Demo: Checking Power Supply Network in IEEE 1801 format and Running IEEE 1801 Quality Checks using Conformal Low Power

Lab Demo: Checking Power Intent for The Macro Connections in IEEE 1801 Format And Running IEEE 1801 Quality Checks using Conformal Low Power 

Online Class

Here is the course link.

Get ready for the most thrilling experience with Accelerated Learning!

The more you know, the faster you go!

Grab the cycle  or hike it, based on your existing knowledge.

Take the quiz and increase your learning pace!!

What's Next?

Grab your Badge after finishing the training and flaunt the expertise you have built up. 😊

Ready to take a tour of this power specification world? Let's help you enroll in this course.

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Related Short Training Bytes/Videos

Enhance the learning experience with short videos:

Genus Synthesis Solution: Video Library

 Joules RTL Power Solution: Video Library

Related Training

 Low-Power Synthesis Flow with Genus Synthesis Solution

Genus Low-Power Synthesis Flow with IEEE 1801

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Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs) for pre- and post-mask layout and offers early ECO prototyping capabilities for driving critical project decisions.

Conformal ECO compares two designs and generates a functional patch that implements the changes between the two designs.

One major criterion for determining patch quality is whether the patch can meet timing closure. To determine this, you typically need to run the time-consuming process of incremental synthesis and place-and-route. Instead, Conformal can analyze path logic depth changes before and after ECO patch generation. This provides a faster way to evaluate timing impact in patch generation stages.

After the patch is created and applied, it is passed to Genus to optimize the patch.

During patch optimization, you can choose to do many things like:

• Keeping constants in the patch
• Allowing tie cell inversion
• Specifying tie cell types
• Preserve DFF cells and cell types in the patch
• Preserve all cells and nets in the patch
• Preserve clock buffer cell in the patch
• Turn on/off sequential constant and sequential merge in patch optimization
• Allowing phase mapping for DFFs
• Map to spare cells
• Force fix DRC before timing

What's Next?

Join the Conformal ECO course to:

• Explore the many options and capabilities of Conformal ECO
• Use Conformal Engineering Change Order (ECO) for flat and hierarchical designs
• Generate a functional ECO patch, apply it to a design, optimize it, and map it to a specified technology
• Run a hierarchical design through ECO and run a comparison to prove the ECO is equivalent
• Run a postmask ECO using Conformal ECO GXL

Make sure you have experience with Conformal Equivalence Checker or completed the Conformal Equivalence Checking course before taking this course.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Please don't forget to obtain your Digital Badge after completing the training. Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust, making you and your projects even more successful.

In this recent Training Webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow by guiding you through essential steps involved in creating integrated circuits—the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

Watch the Training Webinar recording from September 18, 2024: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

Want to Learn More?

This link gives you more information about this RTL-to-GDSII Flow, the related training course, and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

 Also, take this opportunity to register for the free Online Training related to this Webinar Topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Learning Maps

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

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What Is Logic Equivalence Checking in VLSI Design?

What Is DFT in VLSI Design?

What is Digital Implementation?

What is Power Planning?

What are DRC and LVS in Physical Verification?

What are On-Chip Variations?

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Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

Related Resources 

Related Training Bytes:

Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

Running Prototype Implementation Flow in Joules RTL Design Studio (Video)

Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Please don't forget to obtain your Digital Badge after completing the training.

Related Blogs:

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Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community

Research by fDi Intelligence reveals which countries receive more than their ‘expected share’ of FDI. 

Russia remains fDi’s most diversified commodity economy, while second ranked Brazil has displaced Ukraine into third place. Cathy Mullan reports.

A look at the results of fDi’s rankings throughout 2019 finds that Singapore and New York dominated the year’s league tables, followed by Shanghai, Tokyo and London

The chief executive of Ras Al Khaimah Economic Zone (RAKEZ), shares his views over the perks of free zones in emerging markets. 

Emerging states must re-orientate their investment efforts to increasingly target those with an outsized social impact

Egypt is well on the way to establishing a diversified economy, claims Hala El Saeed, minister of planning and economic development 

Tanzania's economy is booming and its tourism sector is thriving. However, concerns about the president's strong-arm tactics and delays in the completion of key infrastructure projects are threatening this growth.

Kenya’s cabinet secretary for the national treasury and planning, Ukur Yatani, discusses the country’s agenda of fiscal reforms and the importance of constructing an east-west Africa highway.

The UN Sustainable Development Goals aim to end global poverty, but poorer countries are struggling to hit them. More help from richer countries is crucial, writes Mazdak Rafaty.