In a driving circuit, one output circuit has a scanning signal line, a first transistor which controls electrical connection between the scanning signal line and a clock signal line which has a gate connected to a first node, the first node which is at an active potential in a first time period including a time period during which the active potential is output to the scanning signal line, a second transistor which electrically connects the first node and an inactive signal line which has a potential to open the transistor in a second time period other than the first time period, and the second transistor has a gate connected to a second node, wherein the second node has two kinds of timings to be charged for retaining the active potential.

A display panel has an amorphous silicon gate driver. A variable capacitor is formed at one end of a gate line to prevent the deterioration of display quality due to high temperature noise. A predetermined level of capacitance is provided to the variable capacitor to the reduce ripple of gate voltage and eliminate the high temperature noise.

A shift register and driving method thereof, a gate driving apparatus and a display apparatus, the shift register comprises a pulling-up unit(21), a precharging and resetting unit(22), an output signal terminal at present stage(OUTPUT), a pulling-down unit(23), an input terminal connected to an output signal terminal of a shift register at previous stage(OUTF), an input terminal connected to an output signal terminal of a shift register at next stage(OUTL), and a scan control signal input terminal(INPUT), wherein: the precharging and resetting unit(22) precharges a gate of a first thin film transistor(T1) included in the pulling-up unit(21) and resets its potential; the pulling-down unit(23) pulls down a potential at the gate of the first thin film transistor(T1) and the output signal at present stage after the precharging and resetting unit(22) resets the potential at the gate of the first thin film transistor(T1), so that the pulling-up unit(21) is turned off and the output signal at present stage is at a low level. The present shift register realizes a bidirectional gate driving scan from up to down or from down to up by a conversion control for high-low levels of input signals.

Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

Methods, systems and devices are provided for displaying monitored activity data in substantial real-time on a screen of a computing device. One example method includes capturing motion data associated with activity of a user via an activity tracking device. The motion data is quantified into a plurality of metrics associated with the activity of the user. The method includes connecting the activity tracking device with a computing device over a wireless data connection, and sending motion data from the activity tracking device to the computing device for display of one or more of the plurality of metrics on a graphical user interface of the computing device. At least one of the plurality of metrics displayed on the graphical user interface is shown to change in substantial real-time based on the motion data.

A shift register, comprising a plurality of shift register sub-units connected in cascade, each of the plurality of shift register sub-units comprising first to third TFTs, an eleventh TFT, a first capacitor and a first reset control module for controlling the second TFT to be turned on or off. Besides the shift register sub-unit at a first stage, for each of the shift register sub-units at other stages, the second TFT gate control terminal thereof is connected to the third TFT gate control terminal of the shift register sub-unit at a previous stage. Accordingly, a gate driving circuit comprising the shift register and a display comprising the gate driving circuit are provided. Compared with the prior art, reliability of the shift register is highly improved and area occupied by the shift register is smaller.

A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

The present invention provides a shift register unit, a shift register circuit, an array substrate and a display device, and relates to the area of display manufacturing. The time of the bias working on the de-noising transistor can be reduced without affecting the circuit stability, so that the operational lifespan of the device can be extended. A shift register comprises: a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a de-noising control model. The present invention is used for manufacturing displays.

A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

A reset circuit for Gate Driver on Array, an array substrate and a display is used for increasing reliability and long-term stability of a GOA circuit and thus improving performance of the GOA circuit. The GOA reset circuit includes a first electronic switch circuit (301) connected to an input terminal of a GOA unit of the Gate Driver on Array (INPUT); and a second electronic switch circuit connected to an output terminal of the GOA unit (OUTPUT), wherein the first electronic switch circuit (301) is connected to a low level signal terminal and is switched on to connect the low level signal terminal to a reset terminal of the GOA unit (RESET) when the input terminal of the GOA unit (INPUT) is at a high level; and the second electronic switch circuit (302) is connected to a high level signal terminal and is switched on to connect the high level signal terminal to the reset terminal of the GOA unit (RESET) when the output terminal of the GOA unit (OUTPUT) is at a high level.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

A stage constituent circuit of a display device drive circuit includes a first-node to a third-node, a thin-film transistor that changes a potential of a scanning signal toward a VDD potential when a potential of the first-node is in a HIGH level, a thin-film transistor that changes a potential of a different stage control signal toward a potential of a clock when a potential of the second-node is in the HIGH level, a capacitor between the first-node and the second-node, and a capacitor between the second-node and the third-node. The potential of the first-node is raised on the basis of a different stage control signal output from the stage constituent circuit in the different stage, and then the potential of the second-node and a potential of the third-node are sequentially raised. Herein, an amplitude of the clock is set to be smaller than an amplitude of the scanning signal.

Disclosed herein is a shift register circuit that is formed on an insulating substrate with thin film transistors having channels of the same conductivity type and includes shift stages, each of the shift stages including: a first thin film transistor; a second thin film transistor; a 3(1)-th thin film transistor; a 3(2)-th thin film transistor; a 4(1)-th thin film transistor; a 4(2)-th thin film transistor; a fifth thin film transistor; and a sixth thin film transistor.

An active level shift (ALS) driver circuit and a liquid crystal display apparatus including the ALS driver circuit are disclosed. The ALS driver circuit includes an input unit configured to apply a first polarity voltage to a first node and to apply a second polarity voltage to a second node, a level compensation unit configured to adjust the voltages of the first node and the second node, and an output unit configured to alternately output a first power voltage and a second power voltage according to the adjusted voltages of the first and second nodes.

A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.

An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof.

The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an LCD device including a thin film transistor (TFT) compensation circuit in an LCD device which implements a driving circuit by using an oxide TFT, the LCD device capable of compensating for degraded characteristics of a TFT due to threshold voltage shift. As the compensation circuit including a dummy TFT is formed on a non-active area of the LC panel, the degree of threshold voltage shift of the DT due to a DC voltage can be sensed. Based on the sensed result, a threshold voltage of a second TFT can be compensated. This can reduce lowering of a device characteristic.

A shift register unit comprises: a first transistor, a pulling-up close unit, a pulling-up start unit, a first pulling-up unit, a second pulling-up unit, a trigger unit, and an output unit. A shift register circuit, an array substrate and a display device are also provided. The shift register unit, the shift register circuit, the array substrate and the display device can reduce drift of a gate threshold voltage of a gate line driving transistor and improve operation stability of devices.

The present invention divides a wire supplying a scan start signal to a gate driver into two wires, so as to avoid overlapping a clock signal line. In this way the clock signal is not delayed by interference, and a gate driving margin may continue uninterrupted, thereby uniformly outputting a gate-on voltage. In particular, if the clock signal line is connected to all stages in the gate driver and the clock signal line overlaps the scan start signal line, unsightly horizontal bands appear on the image and the parallel gate lines generate a very large parasitic capacitance. In contrast, the gate drivers in the present disclosure comprise clock signal lines which do not overlap the scan start signal lines. As benefits, interference resulting in horizontal banding is minimized and the power consumption may be reduced by about 10%.

A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i−1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i−2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

A bilateral cargo strap system is provided as a means of securing a variety of different cargo within a storage area. The bilateral cargo strap system utilizes a combination of elastic straps with perpendicularly positioned stabilizing rods to improve retention of a variety of cargo within a storage area. The elastic straps extend over the retained cargo and are used as the means of engaging mounting features within the storage area. The stabilizing rods effectively distribute the tension force of the elastic straps over the retained cargo securing it in place within the storage space. The bilateral cargo strap system is versatile and may be used to secure a wide variety of cargo including, but not limited to, kayaks, coolers, bicycles, lumber, and construction equipment.

A low profile hold down assembly is mounted to the exterior surface of a sidewall of a trailer. The hold down assembly includes a cover member formed from the same material from which the sidewall of the trailer is formed and therefore is aesthetically desirable.

There is provided a transport vehicle for transporting wind power installation rotor blades and/or pylon segments. The transport vehicle has a transport support structure having a main frame, a receiving frame fixedly connected to the main frame at a first angle, and a rotary displacement unit which is fixed with one end to the receiving frame and which at its second end has a blade adaptor for receiving a rotor blade or a pylon segment. The main frame spans a main plane. The rotary displacement unit has at least one first rotary mounting, wherein there is provided a second angle between the second rotary plane of the second rotary mounting.

A transportation and storage system for a wind turbine rotor blade comprises a tip end frame assembly comprising a tip end receptacle and a tip end frame. The tip end receptacle comprises an upwardly open tip end-receiving space for receiving a portion of the tip end of the blade and having a supporting surface for supporting the blade, a lower surface allowing the tip end receptacle to rest upright on a substantially horizontal surface, such as the ground, and releasable retaining means for releasably retaining the tip end of the blade in the receiving space of the tip end receptacle. The tip end frame comprises an upwardly open receptacle-receiving space for receiving the receptacle and provided with positioning means for positioning the receptacle in the tip end frame. A base part defines a bottom surface allowing the tip end frame to rest upright on the ground.

A transport system for transporting large items wherein the large items comprise at least three through going holes and said system comprises a frame to support the items. Said frame has a substantially rectangular shape and comprises two parallel longitudinal beams connected by two parallel transverse beams and further comprises at least two transverse support bars to support the items, which transverse support bars are located between the two parallel transverse beams. The transport system further comprises a first and a second rod to be mounted in two through going holes in the items where each end of the first and second rod can be connected to the longitudinal beams to secure the items to the frame in such a way that no part of the large items extends over the rectangle defined by the two parallel longitudinal beams and the two parallel transverse beams.

Some embodiments include a novel laced strapping system that provides a plurality of attachment points by which a tie-down lace can adjust the fit of a cargo mesh webbing to secure loads of items in an open bed of a vehicle. In some embodiments, the vehicle is a pick-up truck with a cargo bed. In some embodiments, the mesh webbing comprises a first truck bed mesh, a second truck bed mesh, and the plurality of attachment points. In some embodiments, tie-down lace interconnects the attachment points to secure together the first mesh and the second mesh.

A bull ring for a vehicle comprises a top plate coupled to a rotating plate having a tie-down. Two opposing rail flanges extend from the rotating plate and a fastener selectively couples the rotating plate in a securing position relative to the top plate. The rail flanges extend beyond an outer edge of the top plate to define a clamping region with the top plate.

A blade holding apparatus for holding one end of a wind turbine blade during handling, which blade holding apparatus includes a support structure including an opening for accommodating one end of the wind turbine blade, a clamping arrangement arranged in the opening, which clamping arrangement is realized to exert a clamping force on the wind turbine blade, and a locking arrangement for locking the clamping arrangement relative to the support structure. A method of operating such a blade holding apparatus during a handling procedure of a wind turbine blade is also provided.

A side rail of a floor assembly of a trailer, such as a flatbed trailer, including a channel formed in a top wall of the side rail and an aperture formed in the top wall of the side rail at a location spaced-apart from the channel. The channel extends along a length of the side rail and is configured to receive a first cargo restraint device therein. The aperture is configured to receive a second cargo restraint device therein.

Method and apparatus for handling aerogenerator blades that provide a versatile means for handling aerogenerator blades without an unbalanced distribution of the loads in the blade. The method comprises positioning an upper mounting part (103) over the blade after the upper mold has been retracted; lifting the blade with the upper mounting part from the under mold using a lifting means; positioning the blade over an under mounting part (104) which is fixedly attached to an inferior movable support (102); attaching the upper mounting part to the under mounting part, wherein the upper and under mounting parts together have the inner surface substantially corresponding to the shape of the blade outer profile section. The invention further comprises an apparatus for handling aerogenerator blades.

A transport system for a wind turbine blade is provided. The transport system is configured for increasing a curvature of the wind turbine blade in response to an obstacle during transport of the wind turbine blade. Further, a method for transporting a wind turbine blade in order to avoid obstacles is provided.

A protective cap for a trailing edge of a rotor blade of a wind turbine for use during transportation, handling, or maintenance of the rotor blade is disclosed. The protective cap includes a body having a first leg, a second leg, and a cap member. The cap member connects the first and second legs. Further, the cap member may be configured to cover at least a portion of a trailing edge of the rotor blade and may be configured to provide a gap between an inner surface of the protective cap and the trailing edge. In addition, the first and second legs may resiliently engage the rotor blade.

A cargo rack for transferring loads between a marine vessel and an offshore marine platform provides a frame having a front, a rear, and upper and lower end portions. The lower end of the frame has a perimeter beam base, a raised floor and a pair of open-ended parallel fork tine tubes that communicate with the perimeter beam at the front and rear of the frame. The frame includes a plurality of fixed side walls extending upwardly from the perimeter beam. A plurality of gates are movably mounted on the frame, each gate being movable between open and closed positions, the gates enabling a forklift to place loads on the floor. The frame has vertically extending positioning beams that segment the floor into a plurality of load-holding positions. Each load holding position has positioning beams that laterally hold a load module in position on the floor.

An apparatus and method for applying an underlayment layer to trucking cargo are provided. The underlayment layer may be formed into a roll with a rod disposed therethrough. The roll may be supported by a frame. The roll can be configured to move vertically with respect to the ground. A trailer carrying trucking cargo can be stationed beneath the frame. The underlayment layer may unwound and dispensed from the roll. In order to drape the trucking cargo with the underlayment layer, the roll may be moved horizontally over the frame in addition to or alternatively to having the trucking cargo driven horizontally with respect to the roll.

A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.