I've redesigned a custom TO220FLAT Package

First I created a TO220shape.ssm  with PCB Editor. Then I created a surface mount T220build.pad in Padstack Editor using TO220shape.ssm. Then I created a TO220FLAT.psm in PCB Editor. I placed 3 Connect pins and 9 Mechanical pins for the TO220 TAB, using standard through-hole pads for better current handling.

Adding those Mechanical pins created many DRC errors caused by the proximity of those pads attached to the TO220shape.

Thru Pin to SMD Pin Spacing (-200.0 0.0) 5 MIL OVERLAP DEFAULT NET SPACING CONSTRAINTS Mechanical Pin "Pad50sq30d" Pin "T220build, 2"

I corrected the situation (so I though) by Waiving those DRC errors, thinking that they could not cause any problem and because that’s what I want, i.e.: 9 through-holes under the TO220 device. The idea being that when this device is mounted flat on the PCB it could carry lots of current via 9 pads that could make a good high current conductor to inner layers.

I then saved the Package and updated all related footprint schematic parts  in Capture. Created a new Netlist. Then I imported the new logic into PCB Editor to reflect that change. When the File > Import > Logic is finished I get no feedback error! (which, for me is a substantial achievement in itself)

Now, in the Design Window I see all those DRC errors popping up again, despite the fact that I waived those DRCs back in the Padstack edition. If I run a Design Rule Check (DRC) Report I will see all those DRC listed again. Now, I understand that I can go ahead and waive all those DRCs (100 in total) but I’m thinking there is got to be a better way of doing this.

Please, any advise is welcome. Thanks

Hi everybody,

I've created a symbol with custom pad shapes. Everything looks correct in the symbol editor.

And the 3d view looks correct (upside down to show placement)

But when I try to place it on the pcb the 2 "T" shaped pads aren't in the correct location.

I have the pad shape centered on the pad...

with no offset on the padstack editor.

Does anybody know how to fix this?

Thank you!

Hi,

I have a new customer that uses Allegro Design entry HDL for the schematic and have a few questions.

1. How do you get pin/gate swaps into the symbols in the schematic ?

2. How do you transfer them to the pcb editor ?

3. How do you back annotate the swaps from the pcb editor to the schematic ?

4. How do you stop the export/Import physical from updating the constraints in the pcb file ? 

Is it possible to change trace ends from round to square? Allegro PCB Designer 17.2 (basic)

Thanks

 Hi,

I'm using OVM transaction level tracing in SV. I was wondering if I can have simvision render different types of transactions with different colors e.g. based on a transaction attribute. I know how to do it at signal level using mnemonics but I haven't succeeded doing this at transaction level. Anyone?

 -Joep

Hi everybody,

The attached package is a tiny code example with a demo for an upcoming Team Specman blog post about writing macros.

Hilmar

Attached is the latest revision of the venerable Specman-Matlab package (Lead Application Engineer Jangook Lee is the latest to have refreshed it for a customer in Asia to support 64 bit mode.  Look for a guest blog post from him on this package shortly.)

There is a README file inside the package that gives a detailed overview, shows how to run a demo and/or validate it’s installed correctly, and explains the general test flow.  The test file included in the package called "test_get_cmp_mdim.e" shows all the capabilities of the package, including:

* Using Specman to initialize and tear down the Matlab engine in batch mode

* Issuing Matlab commands from e-code, using the Specman command prompt to load .m files, initializing variables, and other operational tasks.

* Transfering data to and from the Matlab engine to Specman / an e language test bench

* Comparing data of previously retrieved Matlab arrays

* Accessing Matlab arrays from e-code without converting them to e list data structure

* Convert Matlab arrays into e-lists

Happy coding!

Team Specman

Attached is the latest emacs mode for e/Specman - version 1.23

Please follow the install instructions in the top section of the actual file
(after unzipping it) to install/load this package with your emacs.

Hi all,

I am using ADE assembler.

I ran transient simulation and swept the input frequency (Fin) of the circuit. And I use Spectrum Measurement to return a value of the fundamental tone magnitude (Sig_fund) for each sweep point. 

Previously, I use "plot across design points" to plot both "Fin" and "Sig_fund", and then use "Y vs Y" to get a waveform of Sig_fund vs Fin. Measure the 1dB Bandwidth with markers. 

Can I realized above measurement with an expression in "output setup" ? And how?

I know to set the "Eval type" to "sweep" to process the data across sweep points. But here, it has to return an interpolated value from "Fin" with a criteria "(value(calcVal("Sig_fund"  0) - 1)". I am not sure whether it can be done in ADE assembler.

Thanks and regards,

Yutao

Hi,

I am currently struggling with measuring the delay between two clocks with a sufficient accuracy. The reference one is a fixed-phase clock, and the other one is a squared clock resulting of a circuit (kind of PLL) synthesis.
As I need to run a large amount of Monte-Carlo simulations in transient noise, I need to improve the simulation speed, while keeping a satisfactory delay measurement accuracy (<0.1ps), more specifically at 0V-crossings of the differential clocks. So I cannot simply set a max timestep <0.1ps as it would be far too long to simulate.
To sum up, I would need a very relaxed timestep on clock up and down levels, and a very short timestep only at rise/fall transitions.

For this purpose, I wrote a Verilog-A script
- using a timmer function to accurately emulate the reference clock 0V-crossing times (and get the related times with $abstime)
- using @(cross to get the 0V-crossing times of the synthesized clock: but this is not accurate enough (I see simulation noise around 3ps in Conservative). Indeed, the "cross" event occures at the simulation time following the effective 0V-crossing time; this could be sometimes >3ps, far not enough accurate for my purpose.
- I have tried to replace the cross with the "above" function, but it hasn't changed anything, whatever the time_tol value I put (<0.1ps for instance), the result is the same as with the "cross" function and the points are larger than >>0.1ps, weirdly.

So I have decided to give up Verilog-A to measure the delay between my two clocks.
I am currently trying to use the "delay" function of the Cadence Calculator as I guess it will "extrapolate" the time between two simulation points and therefore give a more accurate measurement of the 0V-crossing events, but when I try to compute the delay difference between the synthesized clock and the reference clock, it returns "0".

...

Could you please give me hints to dramatically improve my 0V-crossing time measurements while relaxing the simulation time?
- either by helping me in writing a more suitable Verilog-A script
- or by helping me in using the "delay" function of the calculator
- or maybe by providing me a "magic" Skill function?
Using AMS+Multithread simulator...

Thanks a lot in advance for your help and best regards.

Hi all,

Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?

Thank you.

Hi,

I am trying to characterize a D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). This is a positive edge triggered D flip flop based on true-single-phase clocking scheme. After the characterization, the measurements reported for hold constraint arcs seem to deviate significantly from its (spectre) spice simulation.

The constraint and the power settings to the liberate are as follows : 

# -------------------------------------------- Timing Constraints --------------------------------------------------------------------------------
### Input waveform ###
set_var predriver_waveform 2;# 2=use pre-driver waveform
### Capacitance ###
set_var min_capacitance_for_outputs 1;# write min_capacitance attribute for output pins
### Timing ###
set_var force_condition 4
### Constraint ###
set_var constraint_info 2
#set_var constraint_search_time_abstol 1e-12 ;# 1ps resolution for bisection search
set_var nochange_mode 1 ;# enable nochange_* constraint characterization
### min_pulse_width ###
set_var conditional_mpw 0
set_var constraint_combinational 2

#---------------------------------------------- CCS Settings ----------------------------------------------------------------------------------------
set_var ccsn_include_passgate_attr 1
set_var ccsn_model_related_node_attr 1
set_var write_library_is_unbuffered 1

set_var ccsp_min_pts 15 ;# CCSP accuracy
set_var ccsp_rel_tol 0.01 ;# CCSP accuracy
set_var ccsp_table_reduction 0 ;# CCSP accuracy
set_var ccsp_tail_tol 0.02 ;# CCSP accuracy
set_var ccsp_related_pin_mode 2 ;# use 3 for multiple input switching scnarios and Voltus only libraries

#----------------------------------------------- Power ---------------------------------------------------------------------------------------------------
### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

#set_var power_subtract_leakage 4 ;# use 4 for cells with exhaustive leakage states.
set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector [expr 2**10]
#--------------------------------------------------------------------------------------------------------------------------------------------------------------

I specifically used set_var constraint_combinational 2 in the settings, in case the Bisection pass/fail mode fails to capture the constraints. In my spice simulation, the hold_rise (D=1, CLK=R, Q=R) arc at-least requires ~250 ps for minimum CLK/D slew combination (for the  by default smallest capacitive load as per Liberate)  while Liberate reports only ~30 ps. The define_cell template to this flip flop is pretty generic, which does not have any user specified arcs. So which settings most likely affecting the constraint measurements in Liberate and how can I debug this issue ?

Thanks

Anuradha

Hello,

I am trying to import (in spectre) an spice model of a ceramic capacitor manufactured by Samsung EM. The link that includes the model is here :-

http://weblib.samsungsem.com/mlcc/mlcc-ec.do?partNumber=CL05A156MR6NWR

They proved static spice model and interactive spice model.

I had no problem while including the static model.

However, the interactive model which models voltage and temperature coefficients seems to not be an ordinary spice model. They provide HSPICE, LTSPICE, and PSPICE model files and I failed to include any of them.

Any suggestions ?

Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors. (read more)

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.(read more)

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.(read more)

A recap of the blogs published in the Library Characterization Tidbits blog series.(read more)

Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.(read more)

This blog talks about how to enable the AMS Designer flex mode.(read more)

Hello,

I'm reading the Design specification for IP6514E.

We will use the DAC mode.

It would seem to be very simple but I don't see any code sequence, i.e.

  1.Write 03(Basic Read) to this register

  2, Write start adress to this register

  3. Write "execute" to this register

  4. Read the data from this register

Thanks,

Stefan

Since the release of the Automated Device Placement and Routing solution last year, we have continued to improve and build upon it. In this blog, I’ll talk about the latest addition—the Auto Device Array form—how this is an integral piece of the new Automated Device Placement and Routing solution.(read more)

Hello everyone, today I’d like to talk to you about the recent enhancements to Die export in the Virtuoso RF Solution, most of which were released in ICADVM 18.1 ISR10. What’s the background for these enhancements? Exporting an abstract of a Die, which basically represents the outer boundary of the Die with I/O locations, as an intermediate file to exchange information between various Cadence tools (i.e., the Innovus, Virtuoso, and Allegro platforms) is not a new feature. This capability existed even prior to the Virtuoso RF Solution. However, the entire functionality was rewritten from scratch when we first started developing the Virtuoso RF Solution because the previous feature was deemed archaic, its performance and capacity needed to be enhanced, and use model needed to be modernized. This effort has been made in various phases, with the last round being completed and released in ICADVM18.1 ISR10.(read more)

ڈونالڈ ٹرمپ کی صلاح کے بعد نیویارک مں جراثیم کو مارنے والی اشیا کے پینے کے 30 سے یادہ معاملے سامنے آئے ہیں۔ شہر کے ہیلتھ ڈپارٹمینٹ کے تحت آنے والے (Poison Control Center) کے پاس اس طرح کے معاملات کی گزشتہ 18گھنٹوں میں 30 سے زیادہ کالس آئی ہیں۔ حالانکہ ان میں سے کسی بھی نہ ےو موت ہوئی ہ ہی کسی کو اسپتال(hospital admit) میں داخل کرنے کی ضرورت پڑی ہے۔ ان میں سے زیادہ تر معاملے گھر کی صاف۔صفائی کیلئے استعمال کئے جانے کیلئے استعمال کئے جانے والا (lizol) کے استعمال سے جڑے ہیں۔

ટ્રેનમાં બેસીને વતન જવા માંગતા હતા આ શ્રમિકો, કોને ખબર હતી કે તે જ ટ્રેન તેમનો કાળ બનશે!

રાજ્યમાં એસીબીની ટીમ સક્રીય બની છે, તેમાં પણ વડોદરા શહેર અને જિલ્લાની એસીબી ટીમ વધુ સક્રીય બની છે. જેના કારણે લાંચીયા અધિકારીઓમાં ફફડાટ ફેલાયો છે.

ભારતનાં પૂર્વ ચીફ statistician પ્રણવ સેને કહ્યું કે, લૉકડાઉનનાં માત્ર બે જ સપ્તાહમાં આશરે પાંચ કરોડ લોકોએ પોતાની નોકરી ગુમાવી દીધી છે

જો કે 20 એપ્રિલ પછી આ છૂટ ખાલી સેલ્ફ એમ્પલોઇડ પર્સનને જ છે.

Jio ભારતમાં જે મોટું પરિવર્તન લાવ્યું છે, તેનાથી અમે પણ ઉત્સાહિત થયા છીએઃ Facebook

હું મુકેશ અંબાણી અને સમગ્ર Jio ટીમને તેમની ભાગીદારી માટે ધન્યવાદ કરવા માંગું છું. હું નવી ડિલને લઈ ખૂબ ઉત્સાહિત છું- માર્ક ઝકરબર્ગ

મુકેશ અંબાણીએ કહ્યું કે, જિયો અને ફેસબુકના કરારથી ડિજિટલ ઈન્ડિયાનું મિશન પૂરું થશે

Jioના 38.8 કરોડ ગ્રાહકોની સાથે ફેસબુક વધુમાં વધુ દર્શકો સુધી પહોંચી શકશે.

Reliance Jio અને Facebook વચ્ચેની ડીલ અંગે દુનિયાભરની રેટિંગ એજન્સીઓએ સારી પ્રતિક્રિયા આપી છે.

Relianceની અન્ય સબ્સિડિયરી કંપનીઓના શૅરોમાં પણ જોરદાર તેજી જોવા મળી

રિલાયન્સે ગત 31મી ડિસેમ્બરના રોજ Amazon અને Flipkartને ટક્કર આપવા માટે પોતાનું નવું ઈ-કૉમર્સ સાહસ 'જિયો માર્ટ' (JioMart) લૉંચ કર્યું હતું.

મુકેશ અંબાણીએ રિલાયન્સની 42મી વાર્ષિક સામાન્ય બેઠકમાં કહ્યું હતું કે કંપનીની પાસે રોડમપ છે જેના દ્વારા 31 માર્ચ 2021 સુધી દેવામુક્ત કંપની બની શકે છે

મહિન્દ્રા ગ્રૂપના ચેરમેન આનંદ મહિન્દ્રાએ બુધવારે રિલાયન્સ ઇન્ડસ્ટ્રીઝ લિમિટેડના ચેરમેન મુકેશ અંબાણીની પ્રશંસા કરતા કહ્યું કે Facebook અને Jio ડીલ ફક્ત બે દેશો માટે નહીં પણ ભારતની અર્થવ્યવસ્થા માટે પણ સારી છે

Facebookએ Reliance Jioમાં હિસ્સો ખરીદ્યો, ટેકનોલોજી ક્ષેત્રે સૌથી મોટું FDI

રિલાયન્સ ઇન્ડસ્ટ્રીઝે (Reliance Industries) સોમવારે મોટી જાહેરાત કરતા જણાવ્યું છે કે ખાનગી ઇક્વિટી ફર્મ સિલ્વર લેક Equity Firm Silver Lake) જિયો પ્લેટફોર્મમાં 1.15% ભાગીદારી, 5,655.75 કરોડ રૂપિયામાં ખરીદશે.

Facebook પછી Jio પ્લેટફૉર્મમાં Silver Lake કરશે 5,655 કરોડ રૂપિયાનું રોકાણ

લૉકડાઉન પુરૂં થતાની સાથે જ ટેલિવિઝન અને અન્ય ડિજિટલ એપ્લાયન્સ પર આજે અનેક લોભામણા ઓફરની જાહેરાત કરી છે.

પોલીસે ફેસબુક ઉપરથી આરોપીની વધારે જાણકારીઓ ભેગી કરીને તેના ઘરેથી દબોચી લીધો હતો.

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