Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...(read more)

In my predictions for 2018 I had identified five key trends driving verification in 2018 – Security, Safety, Application Specificity, Processor Ecosystems and System Design Enablement, all centered around ecosystems. Looking back now as the yea...(read more)

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)

Iam new to Package design SIP tool.

I had created the DIE package using SIP. Kindly give the direction how to map the created DIE package in Allegro pcb editor 17.2 ver.

In Allegro design capture CIS tool we had created the schematics file. The DIE which we are using is having 100pins, We had created the DIE in SIP tool. Out of 100 Die pins, only 90 pins is getting connected others are NC pins. We had mapped the Bond fingers only for 90 Die pins in the SIP package. But in the Schematics we had created the DIE logic symbol for 100 pins. Please advice whether we can able to import the DIE package in the allegro tool. In this scenario while importing the 100 pin DIE package in allegro pcb editor will the net connectivity will be shown from the DIE pad to Bond fingers and from Bond fingers to respective components? Please suggest whether we are going in the right path or please advice what we have to proceed with.

Thanks in Advance,

Rajesh

You can't read anything about technology these days without reading about 5G. But before there was 5G, there was 4G. And before that 3G, 2G, and 1G. A 0G even. For the next few Thursdays,...

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The Linley Processor Conference always opens with a keynote by Linley Gwenapp giving an overview of processors in whatever is the hottest area. Most of the other presentations during the conference...

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The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads . SIGRITY2019 HF1 For information about supported platforms, compatibility...

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www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: EDA101 Video Tuesday: Weekend Update Wednesday: RAMAC Park and the Origin of the Disk Drive Thursday: 1G Mobile: AMPS, TOPS, C-450,...

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In last week's post, 1G Mobile: AMPS, TOPS, C-450, Radiocom 2000, and All Those Japanese Ones . I covered 1G mobile, the first analog standards. Then we went digital. 2G The Nordic countries...

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Autonomous vehicles are coming. In a statistic from the U.S. Department of Transportation, about 37,000 people died in car accidents in the United States in 2018. Having safe, fully automatic vehicles could drastically reduce that number—but the trick is figuring out how to make an autonomous vehicle safe. Internet-enabled systems in cars are more common than ever, and it’s unlikely that the use of them will slow or stop—and while they provide many conveniences to a driver, they also represent another attack surface that a potential criminal could use to disable a vehicle while driving.

So—what’s being done to combat this? Green Hills Software is on the case, and they explained the landscape of security in automotive systems in a presentation given by Max Hinson in the Cadence Theater at DAC 2019. They have software embedded [FS1] in most parts of a car, and all the major OEMs use their tech. The challenge they’ve taken on is far from a simple one—between the sheer complexity of modern automotive computer systems, safety requirements like the ISO 26262 standard, and the cost to develop and deploy software, they’ve got their work cut out for them. It’s the complexity of the systems that represents the biggest challenge, though. The autonomous cars of the future have dynamic behaviors, cognitive networks, require security certification to at least ASIL-D, require cyber security like you’d have on an important regular computer system to cover for the internet-enabled systems—and all of this comes with a caveat: under current verification abilities, it’s not possible to test every test case for the autonomous system. You’d be looking at trillions of test cases to reach full coverage—not even the strongest emulation units can cover that today.

With regular cars, you could do testing with crash-test dummies, and ramming the car into walls at high speeds in a lab and studying the results. Today, though, that won’t cut it. Testing like that doesn’t see if a car has side-channel vulnerabilities in its infotainment system, or if it can tell the difference between a stop sign and a yield sign. While driving might seem simple enough to those of us that have been doing it for a long time, to a computer, the sheer number of variables is astounding. A regular person can easily filter what’s important and what’s not, but a machine learning system would have to learn all of that from scratch. Green Hills Software posits that it would take nine billion miles of driving for a machine learning system of today’s caliber to reach an average driver’s level—and for an autonomous car, “average” isn’t good enough. It has to be perfect.

A certifier for autonomous vehicles has a herculean task, then. And if that doesn’t sound hard enough, consider this: in modern machine-vision systems, something called the “single pixel hack” can be exploited to mess them up. Let’s say you have a stop sign, and a system designed to recognize that object as a stop sign. Randomly, you change one pixel of the image to a different color, and then check to see if the system still recognizes the stop sign. To a human, who knows that a stop sign is octagonal, red, and has “STOP” written in white block letters, a stop sign that’s half blue and maybe bent a bit out of shape is still, obviously, a stop sign—plus, we can use context clues to ascertain that sign at an intersection where there’s a white line on the pavement in front of our vehicle probably means we should stop. We can do this because we can process the factors that identify a stop sign “softly”—it’s okay if it’s not quite right; we know what it’s supposed to be. Having a computer do the same is much more difficult. What if the stop sign has graffiti on it? Will the system still recognize it as a stop sign? How big of an aberration needs to be present before the system no longer acknowledges the mostly-red, mostly-octagonal object that might at one point have had “stop” written on it as a stop sign? To us, a stop sign is a stop sign, even with one pixel changed—but change it in the right spot, and the computer might disagree.

The National Institute of Security and Technology tracks vulnerabilities along those lines in all sorts of systems; by their database, a major vulnerability is found in Linux every three days. And despite all our efforts to promote security, this isn’t a battle we’re winning right now—the number of vulnerabilities is increasing all the time.

Check back next time to see the other side: what does Green Hills Software propose we do about these problems? Read part 2 now.

If you missed the first part of this series, you can find it here.

So: what does Green Hills Software propose we do?

The issue of “solving security” is, at its core, impossible—security can never be 100% assured. What we can do is make it as difficult as possible for security holes to develop. This can be done in a couple ways; one is to make small code in small packs executed by a “safing plan”—having each individual component be easier to verify goes a long way toward ensuring the security of the system. Don’t have sensors connect directly to objects—instead have them output to the safing plan first, which can establish control and ensure that nothing can be used incorrectly or in unintended ways. Make sure individual software components are sufficiently isolated to minimize the chances of a side-channel attack being viable.

What all of these practices mean, however, is that a system needs to be architected with security in mind from the very beginning. Managers need to emphasize and reward secure development right from the planning stages, or the comprehensive approach required to ensure that a system is as secure as it can be won’t come together. When something in someone else’s software breaks, pay attention—mistakes are costly, but only one person has to make it before others can learn from it and ensure it doesn’t happen again. Experts are experts for a reason—when an independent expert tells you something in your design is not secure, don’t brush them off because the fix is expensive. This is what Green Hills Software does, and it’s how they ensure that their software is secure.

Now, where does Cadence fit into all of this? Cadence has a number of certified secure offerings a user can take advantage of when planning their new designs. The Tensilica portfolio of IP is a great way to ensure basic components of your design are foolproof. As always, the Cadence Verification Suite is great for security verification in both simulation and emulation, and JasperGold platform’s formal apps are a part of that suite as well.

We are entering a new age of autonomous technology, and with that new age we have to update our security measures to match. It’s not good enough to “patch up” security at the end—security needs to beat the forefront of a verification engineer or hardware designer’s mind at all stages of development. For a lot of applications, quite literally, lives are at stake. It’s uncharted territory out there, but with Green Hills Software and Cadence’s tools and secure IP, we can ensure the safety of tomorrow.

The IEEE has announced the publication of the new 1801-2013 standard, also known as UPF 2.1, and immediate availability for free download through the IEEE 1801-2013 Get Program. Even though the standard is new to the whole world, for the people of the IEEE working group this standard is finally done and is in the past now.

There is a Chinese saying "好事多磨" which means "good things take time to happen." I forgot the exact time when I first joined the working group for the new standard -- about two and half years ago -- but I do remember long hours of meetings and many "lively" debates and discussions. Since the "hard time" has passed us, I would like to share some fun facts about the working group and the standard.

• The 1801 working group is the largest entity based ballot group in IEEE-SA history.
• The new standard was initially planned for 2012, but was delayed purely due to the large amount of work required.
• At one point, the group was debating on whether the new standard should be called UPF 2.1 or 3.0. It may sound weird now but we spent quite some time discussing this. Eventually we settled on 2.1 as it was the original plan.
• The 1801-2013 document has 358 pages which is 53% thicker than previous version (the sheer amount of changes in the new standard indicate that this is more than just a normal incremental update of the previous version as suggested by naming it 2.1)
• Around 300 real issues were reported over the previous version and a majority of them were fixed in the new release.
• This is the first release with constructs and semantics coming from Common Power Format (CPF), a sign of convergence of the two industry leading power formats.
• There are about 100 working group meetings in my Outlook calendar since 2011, with meeting times ranging from 2 hours to 8 hours.
• We extensively used Google Drive (which was called Google Docs when the working group started), a great tool for productivity. I cannot imagine how any standard could have been done before Google existed!

Personally, I had an enjoyable journey, especially from having the privilege to work with many industry experts who are all passionate about low power. I do have one more thing to share though. My older daughter went from middle school to high school during the period of the development of the new standard. Since most of the meetings took place in the early morning California time, she had to endure the pain of listening to all these discussions on power domain, power switches, etc. on her way to school.

I asked her if she learned anything. She told me that other than being able to recognize the voices of Erich, John and Joe on the line, she also learned that she would never want to become an electrical or computer engineer! She was so happy that the meetings stopped a couple of months ago. But what I did not tell her is that the meetings will resume after DAC! Well, I am sure this will be a big motivation for her to get her own driving license in the summer.

If you want to get some quick technical insights into the new standard, check out my recent EE Times article IEEE 1801-2013: A bold step towards power format convergence.

Qi Wang

Hello, i managed to extract my S-param data into vcsv file,however i need a standart S2P file

i have this table displayed, as shown bellow.
is there a way to extract s2p file in cadence virtuoso?
Thanks.

Hi , 

I am sharing with you some simple skill script that draw line in user layer :

axlCmdRegister("DrawLine" 'DrawLine)
procedure(DrawLine()
   layer_name = "substrate geometry/userlayer"
   mypopup = axlUIPopupDefine(nil '(
      ("Done" "axlDBTransactionCommit(mark), axlFinishEnterFun()")
      ("Oops" "axlDBTransactionOops(mark), when(zerop(--oopsNum)")
      ("Cancel" "axlDBTransactionRollback(mark), axlCancelEnterFun()")
      ("MENU_SEPARATOR", nil)))
   axlUIPopupSet( mypopup)
   ; Clear the dynamic buffer
   axlClearDynamics()

   if(axlLayerGet(layer_name) != nil then
      if(axlIsVisibleLayer(layer_name) == nil then
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      );End if
   else
      if(axlLayerGet("substrate geometry") == nil then
         layer_name = "board geometry/userlayer"
         axlLayerCreateNonConductor(layer_name)
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      else
         axlLayerCreateNonConductor(layer_name)
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      );End if
   );End if

   ; Clear mypath to nil, then loop gathering user picks:
   mypath = nil
   mark = axlDBTransactionStart()
   flag = t
   allP = list(nil)
   seg1 = nil
   seg2 = nil
   while( (mypath = axlEnterPath(?lastPath mypath))
      if(flag == t then
         p = axlDBCreatePath(mypath, layer_name)
         seg1 = car(car(car(p))->segments)
         seg2 = car(cdr(car(car(p))->segments))
         path = axlPathStart( list(car(seg1->startEnd)) , 0)
         axlPathLine( path , 0 , car(cdr(seg1->startEnd)))
         if(seg2 then
            axlPathLine( path , 0 , car(cdr(seg2->startEnd)))
         );end if
         flag = nil
      else
         p = axlDBCreatePath(mypath, layer_name)
         seg1 = car(car(car(p))->segments)
         seg2 = car(cdr(car(car(p))->segments))
         axlPathLine( path , 0 , car(cdr(seg1->startEnd)))
         if(seg2 then
            axlPathLine( path , 0 , car(cdr(seg2->startEnd)))
         );end if
      );end if
      allP = cons(car(car(p)) allP)
   );Loop
   axlDBCreatePath(path, layer_name)
   forall( x allP axlDeleteObject(x))
);End procedure

Is anyone can help to understand why this script can work with 16.5/16.6/17.2 and doesn't work with 17.4 ?

To be more informative in 17.4 this script behaves differently , when i am trying to draw line i can't zoom in/out ,i can't use my shortcuts to snap it on segment/middle/edge , it's like it's waiting only for next X/Y user click , all other functions just disabled .

Thanks .

I'm working on a circuit that requires the input voltage to be converted to a frequency, transmitted over an optical cable, and then converted back to a voltage. I am attempting to simulate this circuit using Eagle ngSpice simulations. The voltage to frequency converters that I am using are ADVFC32 and made by Analog Devices. However, I can't seem to find a SPICE model for this component. Analog Devices does not provide it on their website. Can anyone find a SPICE Model for this part? I'm new to working with electronics so any help/advice you can provide would be appreciated.

Hi,

I am facing this elaboration error when using Xcelium:

Command>

    xmverilog -v200x +access+r +xm64bit -f vlist -reflib plib -timescale 1ns/1ps

Log>

    xmelab: *E,CUVMUR (<name>.v,538|18): instance 'LUTP0.C GLAT3' of design unit 'tlatntscad12' is unresolved in 'worklib.LUTP0:v'.

I guess the plib was not referred to as the simulation configuration because the tlatntscad12 is included in plib.

The plib is compiled by INCISIVE 13.20 and I am using the Xcelium 19.30.

Please tell me the correct command on how to refer to the library directory compiled by different versions.

Thank you,

Sample clues

11 across: Chandigarh’s is 0172 (3,4)

21 across: He’s a loser, baby (4)

1 down: Garment meant to shape the torso (6)

12 down: It’s slogan: “Life, Liberty and the Pursuit” (8)

18 down: Noise made by badminton players? (6)

Extrowords © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

Sample clues

5 across: The US president’s bird (3,5,3)

11 down: Group once known as the Quarrymen (7)

10 across: Cavalry sword (5)

19 across: Masonic ritual (5,6)

1 down: Pioneer of Ostpolitik (6)

Extrowords © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

I'm trying to re-install ORCAD 17.2  in a PC from a DVD which I have upgraded from Win 7 to Win 10 and  now has a new 500GB SSD. While installing I got a Windows Application Error  0xc000007b. When I try to run ORCAD I get the same Error.

Looking for ways to fix this problem.

I would like to add these components to the component bank in ORCAD simulation. Even an accessible or free course that explained how to create these components.

Hello All,

Following is the einstein's puzzle solved by cadence Incisive92  (solved in less than 3 seconds -> FAST!!!!!!)

Thanks,

Vinay Honnavara

Verification engineer at Keyu Tech

vinayh@keyutech.com

 // Author: Vinay Honnavara

// Einstein formulated this problem : he said that only 2% in the world can solve this problem
// There are 5 different parameters each with 5 different attributes
// The following is the problem

// -> In a street there are five houses, painted five different colors (RED, GREEN, BLUE, YELLOW, WHITE)

// -> In each house lives a person of different nationality (GERMAN, NORWEGIAN, SWEDEN, DANISH, BRITAIN)

// -> These five homeowners each drink a different kind of beverage (TEA, WATER, MILK, COFFEE, BEER),

// -> smoke different brand of cigar (DUNHILL, PRINCE, BLUE MASTER, BLENDS, PALL MALL)

// -> and keep a different pet (BIRD, CATS, DOGS, FISH, HORSES)


///////////////////////////////////////////////////////////////////////////////////////
// *************** Einstein's riddle is: Who owns the fish? ***************************
///////////////////////////////////////////////////////////////////////////////////////

/*
Necessary clues:

1. The British man lives in a red house.
2. The Swedish man keeps dogs as pets.
3. The Danish man drinks tea.
4. The Green house is next to, and on the left of the White house.
5. The owner of the Green house drinks coffee.
6. The person who smokes Pall Mall rears birds.
7. The owner of the Yellow house smokes Dunhill.
8. The man living in the center house drinks milk.
9. The Norwegian lives in the first house.
10. The man who smokes Blends lives next to the one who keeps cats.
11. The man who keeps horses lives next to the man who smokes Dunhill.
12. The man who smokes Blue Master drinks beer.
13. The German smokes Prince.
14. The Norwegian lives next to the blue house.
15. The Blends smoker lives next to the one who drinks water.
*/




typedef enum bit [2:0]  {red, green, blue, yellow, white} house_color_type;
typedef enum bit [2:0]  {german, norwegian, brit, dane, swede} nationality_type;
typedef enum bit [2:0]  {coffee, milk, water, beer, tea} beverage_type;
typedef enum bit [2:0]  {dunhill, prince, blue_master, blends, pall_mall} cigar_type;
typedef enum bit [2:0]  {birds, cats, fish, dogs, horses} pet_type;




class Einstein_problem;

    rand house_color_type house_color[5];
    rand nationality_type nationality[5];
    rand beverage_type beverage[5];
    rand cigar_type cigar[5];
    rand pet_type pet[5];
        rand int arr[5];
    
    constraint einstein_riddle_solver {
    
        
    
        foreach (house_color[i])
            foreach (house_color[j])
               if (i != j)
                house_color[i] != house_color[j];
        foreach (nationality[i])
            foreach (nationality[j])
               if (i != j)
                nationality[i] != nationality[j];
        foreach (beverage[i])
            foreach (beverage[j])
               if (i != j)
                beverage[i] != beverage[j];
        foreach (cigar[i])
            foreach (cigar[j])
               if (i != j)
                cigar[i] != cigar[j];
        foreach (pet[i])
            foreach (pet[j])
               if (i != j)
                pet[i] != pet[j];
    
    
        //1) The British man lives in a red house.
        foreach(nationality[i])
                (nationality[i] == brit) -> (house_color[i] == red);
                
        
        //2) The Swedish man keeps dogs as pets.
        foreach(nationality[i])
                (nationality[i] == swede) -> (pet[i] == dogs);
                
                
        //3) The Danish man drinks tea.        
        foreach(nationality[i])
                (nationality[i] == dane) -> (beverage[i] == tea);
        
        
        //4) The Green house is next to, and on the left of the White house.
        foreach(house_color[i])        
                 if (i<4)
                    (house_color[i] == green) -> (house_color[i+1] == white);
        
        
        //5) The owner of the Green house drinks coffee.
        foreach(house_color[i])
                (house_color[i] == green) -> (beverage[i] == coffee);
                
        
        //6) The person who smokes Pall Mall rears birds.
        foreach(cigar[i])
                (cigar[i] == pall_mall) -> (pet[i] == birds);
        
        
        //7) The owner of the Yellow house smokes Dunhill.
        foreach(house_color[i])
                (house_color[i] == yellow) -> (cigar[i] == dunhill);
        
        
        //8) The man living in the center house drinks milk.
        foreach(house_color[i])
                if (i==2) // i==2 implies the center house (0,1,2,3,4) 2 is the center
                    beverage[i] == milk;
        
        
        
        //9) The Norwegian lives in the first house.
        foreach(nationality[i])        
                if (i==0) // i==0 is the first house
                    nationality[i] == norwegian;
        
        
        
        //10) The man who smokes Blends lives next to the one who keeps cats.
        foreach(cigar[i])        
                if (i==0) // if the man who smokes blends lives in the first house then the person with cats will be in the second
                    (cigar[i] == blends) -> (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i>0 && i<4) // if the man is not at the ends he can be on either side
                    (cigar[i] == blends) -> (pet[i-1] == cats) || (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i==4) // if the man is at the last
                    (cigar[i] == blends) -> (pet[i-1] == cats);
        
        foreach(cigar[i])        
                if (i==4)
                    (pet[i] == cats) -> (cigar[i-1] == blends);
        
        
        //11) The man who keeps horses lives next to the man who smokes Dunhill.
        foreach(pet[i])
                if (i==0) // similar to the last case
                    (pet[i] == horses) -> (cigar[i+1] == dunhill);
        
        foreach(pet[i])        
                if (i>0 & i<4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill) || (cigar[i+1] == dunhill);
                    
        foreach(pet[i])        
                if (i==4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill);
                    


        //12) The man who smokes Blue Master drinks beer.
        foreach(cigar[i])
                (cigar[i] == blue_master) -> (beverage[i] == beer);
        
        
        //13) The German smokes Prince.
        foreach(nationality[i])        
                (nationality[i] == german) -> (cigar[i] == prince);
        

        //14) The Norwegian lives next to the blue house.
        foreach(nationality[i])
                if (i==0)
                    (nationality[i] == norwegian) -> (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i>0 & i<4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue) || (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i==4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue);
        

        //15) The Blends smoker lives next to the one who drinks water.            
        foreach(cigar[i])            
                if (i==0)
                    (cigar[i] == blends) -> (beverage[i+1] == water);
        
        foreach(cigar[i])        
                if (i>0 & i<4)
                    (cigar[i] == blends) -> (beverage[i-1] == water) || (beverage[i+1] == water);
                    
        foreach(cigar[i])        
                if (i==4)
                    (cigar[i] == blends) -> (beverage[i-1] == water);
        
    } // end of the constraint block
    


    // display all the attributes
    task display ;
        foreach (house_color[i])
            begin
                $display("HOUSE : %s",house_color[i].name());
            end
        foreach (nationality[i])
            begin
                $display("NATIONALITY : %s",nationality[i].name());
            end
        foreach (beverage[i])
            begin
                $display("BEVERAGE : %s",beverage[i].name());
            end
        foreach (cigar[i])
            begin
                $display("CIGAR: %s",cigar[i].name());
            end
        foreach (pet[i])
            begin
                $display("PET : %s",pet[i].name());
            end
        foreach (pet[i])
            if (pet[i] == fish)
                $display("THE ANSWER TO THE RIDDLE : The %s has %s ", nationality[i].name(), pet[i].name());
    
    endtask // end display
    
    
endclass




program main ;

    initial
        begin
            Einstein_problem ep;
            ep = new();
            if(!ep.randomize())
                $display("ERROR");
            ep.display();
        end
endprogram // end of main

        

Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.

As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital teams that have rapidly evolved design and verification practices over the past decade. Well, I claim that is about to change. 2015 will be a watershed year for many more design teams because of the following factors:

• 85% of designs are mixed signal, and it is going to stay that way (there is no turning back)
• Advanced node drives new techniques, but they will be applied on all nodes
• Equilibrium of mixed-signal designs being challenged, complexity raises risk level
• Tipping point signs are evident and pervasive, things are going to change
• The convergence of “big A” and “big D” demands true mixed-signal practices

Reason 1: Mixed-signal is dominant

To begin the examination of what is going to change and why, let’s start with what is not changing. IBS reports that mixed signal accounts for over 85% of chip design starts in 2014, and that percentage will rise, and hold steady at 85% in the coming years. It is a mixed-signal world and there is no turning back!

Figure 1. IBS: Mixed-signal design starts as percent of total

The foundational nature of mixed-signal designs in the semiconductor industry is well established. The reason it is exciting is that a stable foundation provides a platform for driving change. (It’s hard to drive on crumbling infrastructure.  If you’re from California, you know what I mean, between the potholes on the highways and the earthquakes and everything.)

Reason 2: Innovation in many directions, mostly mixed-signal applications

While the challenges being felt at the advanced nodes, such as double patterning and adoption of FinFET devices, have slowed some from following onto to nodes past 28nm, innovation has just turned in different directions. Applications for Internet of Things, automotive, and medical all have strong mixed-signal elements in their semiconductor content value proposition. What is critical to recognize is that many of the design techniques that were initially driven by advanced-node programs have merit across the spectrum of active semiconductor process technologies. For example, digitally controlled, calibrated, and compensated analog IP, along with power-reducing mutli-supply domains, power shut-off, and state retention are being applied in many programs on “legacy” nodes.

Another graph from IBS shows that the design starts at 45nm and below will continue to grow at a healthy pace.  The data also shows that nodes from 65nm and larger will continue to comprise a strong majority of the overall starts. 

Figure 2.  IBS: Design starts per process node

TSMC made a comprehensive announcement in September related to “wearables” and the Internet of Things. From their press release:

TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.

Compared with their previous low-power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life—by 2X to 10X—when much smaller batteries are demanded in IoT/wearable applications.

The focus on power is quite evident and this means that all of the power management and reduction techniques used in advanced node designs will be coming to legacy nodes soon.

Integration and miniaturization are being pursued from the system-level in, as well as from the process side. Techniques for power reduction and system energy efficiency are central to innovations under way.  For mixed-signal program teams, this means there is an added dimension of complexity in the verification task. If this dimension is not methodologically addressed, the level of risk adds a new dimension as well.

Reason 3: Trends are pushing the limits of established design practices

Risk is the bane of every engineer, but without risk there is no progress. And, sometimes the amount of risk is not something that can be controlled. Figure 3 shows some of the forces at work that cause design teams to undertake more risk than they would ideally like. With price and form factor as primary value elements in many growing markets, integration of analog front-end (AFE) with digital processing is becoming commonplace.  

Figure 3.  Trends pushing mixed-signal out of equilibrium

The move to the sweet spot of manufacturing at 28nm enables more integration, while providing excellent power and performance parameters with the best cost per transistor. Variation becomes great and harder to control. For analog design, this means more digital assistance for calibration and compensation. For greatest flexibility and resiliency, many will opt for embedding a microcontroller to perform the analog control functions in software. Finally, the first wave of leaders have already crossed the methodology bridge into true mixed-signal design and verification; those who do not follow are destined to fall farther behind.

Reason 4: The tipping point accelerants are catching fire

The factors cited in Reason 3 all have a technical grounding that serves to create pain in the chip-development process. The more factors that are present, the harder it is to ignore the pain and get the treatment relief  afforded by adopting known best practices for truly mixed-signal design (versus divide and conquer along analog and digital lines design).

In the past design performance was measured in MHz with simple static timing and power analysis. Design flows were conveniently partitioned, literally and figuratively, along analog and digital boundaries. Today, however, there are gigahertz digital signals that interact at the package and board level in analog-like ways. New, dynamic power analysis methods enabled by advanced library characterization must be melded into new design flows. These flows comprehend the growing amount of feedback between analog and digital functions that are becoming so interlocked as to be inseparable. This interlock necessitates design flows that include metrics-driven and software-driven testbenches, cross fabric analysis, electrically aware design, and database interoperability across analog and digital design environments.

Figure 4.  Tipping point indicators

Energy efficiency is a universal driver at this point.  Be it cost of ownership in the data center or battery life in a cell phone or wearable device, using less power creates more value in end products. However, layering multiple energy management and optimization techniques on top of complex mixed-signal designs adds yet more complexity demanding adoption of “modern” mixed-signal design practices.

Reason 5: Convergence of analog and digital design

Divide and conquer is always a powerful tool for complexity management.  However, as the number of interactions across the divide increase, the sub-optimality of those frontiers becomes more evident. Convergence is the name of the game.  Just as analog and digital elements of chips are converging, so will the industry practices associated with dealing with the converged world.

Figure 5. Convergence drivers

Truly mixed-signal design is a discipline that unites the analog and digital domains. That means that there is a common/shared data set (versus forcing a single cockpit or user model on everyone). 

In verification the modern saying is “start with the end in mind”. That means creating a formal approach to the plan of what will be test, how it will be tested, and metrics for success of the tests. Organizing the mechanics of testbench development using the Unified Verification Methodology (UVM) has proven benefits. The mixed-signal elements of SoC verification are not exempted from those benefits.

Competition is growing more fierce in the world for semiconductor design teams. Not being equipped with the best-known practices creates a competitive deficit that is hard to overcome with just hard work. As the landscape of IC content drives to a more energy-efficient mixed-signal nature, the mounting risk posed by old methodologies may cause causalities in the coming year. Better to move forward with haste and create a position of strength from which differentiation and excellence in execution can be forged.

Summary

2015 is going to be a banner year for mixed-signal design and verification methodologies. Those that have forged ahead are in a position of execution advantage. Those that have not will be scrambling to catch up, but with the benefits of following a path that has been proven by many market leaders.

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نتن یاہو کے دفتر کے ذرائع کے مطابق رویکا پلچو کے رابطے میں آنے والے تمام افراد کو اب 14 دنوں کے لیے خود کو الگ تھلگ رکھنا ہوگا ۔

چین میں گزشتہ 24 گھنٹے کے دوران کورونا وائرس انفیکشن کے 48 نئے معاملے سامنے آئے جبکہ ایک شخص کی موت ہو گئی ہے۔ جن 48 لوگوں میں انفیکشن پایا گیا ان کی دوسرے ممالک میں جانے کی تاریخ رہی تھی۔ اس سے 282 متاثرہ صحت مند ہو چکے ہیں۔وپیں پاکستان میں بھی کورونا وائرس (كووڈ 19) تیزی سے پھیل رہا ہے اور منگل کے روز متاثرین کی تعداد 1872 ہو گئی اور اس سے اب تک 26 لوگوں کی موت ہو چکی ہے۔

سعودی عرب نے کورونا وائرس کی وبا کے پیش نظر رواں سال حج کے منصوبوں سے متعلق ایک بڑا بیان دیا ہے۔

عالمی وبا کورونا وائرس (کووڈ -19) سے بری طرح متاثر اٹلی میں اس وبا سے مرنے والوں کی تعداد 12 ہزار سے تجاوز کر کے 12ہزار428 ہو گئی ہے جبکہ اس سے متاثر افراد کی تعداد ایک لاکھ پانچ ہزار سات سو بانوے ہو گئی

دنیا بھر میں پھیل چکے مہلک وائرس ’كووڈ 19‘ کے قہر سے اسرائیل میں اب تک 25 افرا د ہلاک ہو گئے ہیں اور تقریباََ 6092 افراد اس وائرس کی گرفت میں آ گئے ہیں ۔

سعودی عرب کی وزارت داخلہ نے مقدس شہروں مکہ مکرمہ اور مدینہ منورہ میں کورونا وائرس کے پھیلاؤ کو محدود کرنے کے لئے جمعرات کے روز 24 گھنٹے کا کرفیو نافذ کر دیا۔

اسرائیل کی وزارت صحت نے ملک میں 2 اپریل تک 30 لوگوں کی ہلاکتوں اور 6211 کے کورونا سے متاثر ہونے کی تصدیق کی ہے۔

افریقہ میں کورونا وائرس 'كووڈ 19' کے کیسز بڑھتے ہی جا ر ہے ہیں اور اس وائرس کی زد میں آنے سے اب تک 284 افراد ہلاک جبکہ تقریبا 7028 لوگ متاثر پائے گئے ہیں۔

پاکستان میں کورونا وائرس کا خطرہ مسلسل بڑھتا جارہا ہے اور اتوار کو یہاں متاثرین کی تعداد 2934 اور مرنے والوں کی تعداد 45 کو پہنچ گئی ہے۔

اٹلی کے شہری سیکورٹی محکمہ کے سربراہ اینجیلو بوریلی نے پیر کو ٹیلی ویژن پر ایک پریس کانفرنس میں بتایا کہ گزشتہ 24 گھنٹوں کے دوران ملک میں کورونا وائرس سے 636 افراد کی موت ہوئی ہے۔

غور طلب ہےکہ لڑکی کی شادی تو کرائی جاچکی ہے لیکن 13اپریل کو اس کی وداعی کی جانی تھی۔ اس سے پہلے ہی پولیس پہنچ گئی اور وداعی سے پہلے لڑکی کے والدین، دولہااور رشتہ داروں کے خلاف مقدمہ درج کیا ہے۔ وہیں دولہے سمیت دیگر ملزمین کی تلاش جاری ہے۔

پاکستان کا صوبہ پنجاب کورونا وائرس سے سب سے زیادہ متاثر ہے۔ صوبہ سندھ اور خیبر پختونخوا میں کورونا وائرس سے 18-18لوگوں کی موت ہوئی ہے۔ یہاں متاثرین کی تعداد تقریباً 986اور 527پر پہنچ گئی ہے۔

بوریلی کے مطابق جمعرات کو اٹلی میں کورونا انفیکشن کے 4204 نئے کیس سامنے آئے ہیں جس سے اب تک کل متاثرہ مریضوں کی تعداد بڑھ کر 143626 ہو گئی ہے۔

امریکہ میں کورونا وائرس سے جمعہ کے روز 2108 افراد کی موت ہوئی ہے۔ اس سے پہلے بدھ کو سب سے زیادہ 1936 افراد کی موت ہوئی تھی۔

عالمی وبا كووڈ -19 کی وجہ سے امریکہ میں سب سے زیادہ (22020 ) افراد کی موت ہوئی ہے جبکہ اٹلی میں 19899 اور اسپین میں 17209 لوگوں نے جانیں گنوائی ہیں۔ وہیں فرانس میں کورونا وائرس سے 14000 افراد کی موت ہوئی ہے، اور 1.34 لاکھ لوگ اس سے متاثر ہوئے ہیں۔

کووڈ-19 پہلی مرتبہ گذشتہ سال دسمبر میں چین کے شہر ووہان میں سامنے آیا تھا اور دیکھتے ہی دیکھتے اس نے ملکوں اور علاقوں کو اپنی زد میں لے لیا۔

پوری دنیا میں کورونا سے امریکہ کے بعد سب سے زیادہ ہلاکتیں اٹلی میں ہی ہوئی ہیں۔

بوریلي کے مطابق بدھ کے روز اٹلی میں کورونا وائرس کے دو ہزار سے زائد نئے کیسز سامنے آئے ہیں جس سے اب تک متاثرہ مریضوں کی مجموعی تعداد بڑھ کر 165155 ہو گئی ہے ۔

جان ہاپکنز یونیورسٹی کی جانب سے جاری تازہ ترین اعداد وشمار کے مطابق دنیا بھر میں کورونا وائرس سے کل 2064115 افراد متاثر ہوئے ہیں جبکہ اس سے مرنے والوں کی تعداد بڑھ کر 137078 ہو گئی ہے۔

پروفیسر ڈاکٹر مسعود حمید نے کہا کہ دو سے ڈھائی مہینے کے درمیان کئی مملک میں بھی وائرس سے اموات ہوئی ہیں ۔ کورونا وائرس دنیا میں پچاس سے ساٹھ دنوں تک ہلکے انداز میں پھیلا ، لیکن پھر یہ دنیا میں اچانک قہر ڈھانے لگا ۔

ادھر، کورونا وائرس (کوویڈ19)کی وبا کے خطرے کے درمیان صدر ڈونلڈ ٹرمپ نے صوبائی گورنروں سے بات چیت کرنے کے بعد ملک کی معیشت کو مرحلے وار طریقے سے کھولنے کے لئے ہدایات جاری کی ہیں۔

اعجاز آہنگر عرف ابو عثمان الکشمیری سینٹرل جیل سے چھوڑے جانے کے فورا بعد ہی بنگلہ دیش چلا گیا تھا ، جہاں سے وہ پاکستان کی فلائٹ پکڑ کر وہاں چلا گیا تھا ۔

اس عالمی وبا کے مرکز چین میں اب تک 82719 افراد اس متاثر ہوئے ہیں اور 4632 اموات ہوئی ہیں ۔اسپین اس سے سب سے زیادہ متاثر ہونے والے ممالک کی فہرست میں امریکہ کے بعد دوسرے مقام پر ہے۔

پاکستان میں اب تک سرکاری طور پر کورونا کے 7400 سے زیادہ معاملے سامنےآئے ہیں اور 143 افراد کی موت ہوئی ہے۔ اب کراچی سے ایک خبر آرہی ہے جس سے حکومت پاکستان پر ایک بار پھر سوالات اٹھ رہے ہیں۔ گذشتہ 49 دنوں میں ، 3265 لاشیں کراچی (Karachi) شہر کے قبرستانوں میں دفن کی گئی ہیں۔

وزارت صحت کے بیماریوں کے کنٹرول اور روک تھام مرکز (كےسی ڈی سی) نے منگل کو بتایا کہ انفیکشن سے ایک اور شخص کی موت کے ساتھ مرنے والوں کی تعداد 237 ہو گئی جو مجموعی کیسز کا 2.22 فیصد ہے۔

دنیا کا سپر پاور مانے جانے والے امریکہ میں یہ وبا بھیانک شکل اختیار کرچکی ہے۔ یہاں پر اب تک 824147 لوگ اس سے متاثر ہوئے ہیں جبکہ 44999 افراد کی موت ہو چکی ہے۔