A tether device includes a magnetic base; a pole having a first end attached to the magnetic base; and a connector or clip attached at a second end of the pole, for removably connecting the tethering device to a user. Also, a method for tethering a user to a hull of a vessel including the steps of providing a tether device having a magnetic base, a pole having a first end attached to the magnetic base, and a connector or clip attached at a second end of the pole; connecting the connector or clip to the user; and engaging the magnetic base with the hull of the vessel.

Ladders, ladder components and related methods are provided including various embodiments of a combination ladder. In some embodiments, a platform is provided that is fixedly coupled with a rail assembly of a combination ladder. The platform may pivot between a useable position or state and a stowed or stored position or state. The platform may maintain a position relative to certain rungs of the rail assembly while being displaceable relative to other rungs of the rail assembly. A hand rail may be coupled to the rail assembly and a tray may be coupled with the hand rail. The tray and the platform may be configured to maintain a constant distance between one another while the rail assembly is adjusted for height.

Self-locking bi-foldable load bearing segments are disclosed that can be used in applications such as ladders or ramp. First and second sections of the segment are foldably coupled to transition between an open configuration and a folded configuration. The first and second sections can include rungs pivotally attached to rails that can be further transitioned from the folded configuration to a collapsed configuration, but not transitioned from the open configuration to the collapsed configuration. Openings in the side walls of the rails allow the rungs to pivot in one direction, but not an opposite direction. In the open configuration, the openings of the first and second sections may be oriented opposite, and the direction of allowed rotation of the rungs of the first section and second section are opposite, restricting compression of the rails together. In the folded configuration, the openings of the first and second sections can be oriented the same to allow rotation of the rungs and compression of the rails together.

Methods and systems are provided for enabling engine dilution control. One or more engine diluents are combined to provide a desired engine dilution, the various diluents selected based on their respective combustion stability limits. A ratio of the various diluents used is further adjusted based on engine operating limitations.

A linear alternator assembly is provided that includes a block defining a cylinder. The cylinder block has inlet ports at which fluid enters the cylinder, exhaust ports at which fluid is exhausted from the cylinder, and a fuel port. Energizable coils surround the cylinder. A first and a second magnetic or magnetizable piston are contained within the cylinder and are positionable within the cylinder in response to energization of selective ones of the coils and combustion of fuel within the cylinder to selectively establish a four-stroke working cycle having an intake stroke, a compression stroke, an expansion stroke, and an exhaust stroke, producing at least one of compressed gas and electrical energy. The four-stroke working cycle may be varied to adapt to changes in power demanded, thereby balancing required output power with efficiency considerations.

An internal combustion engine includes a first cylinder having an intake valve in fluid communication with an intake manifold, and a second cylinder having an exhaust valve in fluid communication with an exhaust manifold. A transfer passage fluidly connects the first cylinder with the second cylinder. A first fuel injector is configured to provide a first fuel to the first cylinder, and a second fuel injector is configured to provide a second fuel to the second cylinder. The first cylinder operates, at times, to push a first air/fuel mixture through the transfer passage into the second cylinder. The second fuel injector is configured to provide at least one fuel injection plume into the first air/fuel mixture.

In an internal combustion engine valve drive arrangement having cam elements which are supported on a camshaft so as to be axially displaceable and having switch gates which are coupled to the cam elements and have gate tracks with track segments and switching segments for displaceing the cam elements, the track segments and the switching segments are formed, at least in part, in partial areas of the switch gates.

A continuously variable valve lift mechanism for an internal combustion engine includes a cam, a cam follower, a valve follower, a rocker shaft, and a rocker arm. The cam follower includes a first roller driven by the cam and a second roller. The valve follower includes a driven face in contact with the second roller of the cam follower and a driving face. The rocker shaft contacts the valve follower. Rotational movement of the rocker shaft about a rocker shaft rotational axis results in movement of the driven face with respect to the second roller. The rocker arm has a pivot axis and is in contact with the driving face of the valve follower.

A method of controlling a vehicle associated micro-hybrid system. The system includes a reversible rotary electrical machine that is connected to a thermal engine of a motor vehicle. The method includes: controlling a step of pre-fluxing of a rotor of the reversible rotary electrical machine when a control module receives an instruction to start the thermal engine via the reversible rotary electrical machine; measuring a speed of the rotor of the reversible rotary electrical machine; and, demanding stoppage of the pre-fluxing step when the speed of the rotor is greater than or equal to a predetermined speed threshold value. The method avoids the generation of overvoltages in an electrical distribution network formed by an onboard network of the vehicle and by an energy storage unit of the micro-hybrid system.

Methods and systems are provided for addressing pre-ignition that may be induced in response to actions taken to mitigate a cylinder misfire. An amount of engine load limiting applied may be adjusted to reduce the likelihood pre-ignition while also addressing component over-temperature issues. By limiting an engine load while shutting off fuel in a misfiring cylinder, and while combusting a lean air-fuel mixture in the remaining cylinders, pre-ignition induced by the misfire-mitigating lean combustion conditions can be reduced.

A fuel injection adapter can include a primary cavity into which a primary fuel injector can be received and a secondary cavity into which a secondary fuel injector can be received. A channel can provide fluid communication between the primary and secondary cavity, and the primary cavity can be in fluid communication with an outlet of the fuel injection adapter.

A fuel feed device for attachment to a cylinder head of an internal combustion engine has at least one fuel distribution element extending along a longitudinal direction, and at least one connecting element extending transversely to the longitudinal direction, wherein the connecting element can be used to connect the fuel distribution element to the cylinder head. The fuel feed device further includes at least one reinforcing element which is connected, on one hand, to an outer surface of the fuel distribution element and, on the other hand, to the connecting element outside the fuel distribution element.

A vapor purge valve in an engine is provided. The vapor purge valve includes a purge valve inlet, a purge valve outlet, and a muffler including a housing at least partially enclosing a diffuser in fluidic communication with the purge valve inlet and the purge valve outlet.

An air cooler line is provided. The air cooler lines includes a first air cooler having a plurality of air flow conduits, each of the air flow conduits including an inlet, and a first air flow deflector extending across peripheral portions of the inlets and fixedly coupled to the air flow conduits and a second air cooler having a plurality of air flow conduits, each of the air flow conduits including an inlet, and a second air flow deflector extending across peripheral portions of the inlets and fixedly coupled to the air flow conduits, the second air flow deflector differing in at least one of size and geometry than the first air flow deflector.

Embodiments for an engine system are provided. One example internal combustion engine having at least one cylinder head and at least two cylinders, in which each cylinder has at least one inlet opening for the supply of combustion air into the cylinder, comprises an intake line leading to each inlet opening, an overall intake line where the intake lines of at least two cylinders merge, such that a distributor junction point is formed, and a heating device arranged in the overall intake line which has at least one strip-like heating element, a first narrow side of a cross section of which faces toward intake combustion air flow, wherein the heating device is arranged adjacent to the distributor junction point at which the intake lines merge to form the overall intake line, a spacing between the heating device and the distributor junction point being smaller than the diameter of a cylinder.

An air intake manifold for an engine includes an air inlet to receive a flow of compressed charge air, and multiple runners to deliver cooled compressed charge air to corresponding combustion cylinders of the engine. A charge air cooler is arranged within the intake manifold between the air inlet and the runners, and includes a first core section and a second core section. The first and second core sections are arranged fluidly in parallel with respect to the flow of compressed charge air, so that the charge air is divided into a first portion that is substantially directed through the first core section to a first subset of the runners, and a second portion that is substantially directed through the second core section to a second subset of the runners.

A charge air cooler includes a housing and a heat exchanger core positioned within the housing. The heat exchanger core includes a first core section, a second core section, and a centrally located section positioned between the first core section and the second core section. The charge air cooler also includes a plurality of coolant circuits. Each coolant circuit extends through at least one of the first and second core sections. The charge air cooler further includes a coolant inlet extending from the centrally located section to deliver coolant to the plurality of coolant circuits, and a coolant outlet extending from the centrally located section to receive coolant from the plurality of coolant circuits. The charge air cooler also includes a fastener extending through the centrally located section of the core to secure the core to the housing.

As one example, a fuel rail assembly for supplying pressurized fuel to a plurality of cylinders of an engine is provided. The fuel rail assembly includes a fuel rail housing defining an internal fuel rail volume having at least a first region and a second region; a fuel separation membrane element disposed within the fuel rail housing that segregates the first region from the second region. The membrane element can be configured to pass a first component of a fuel mixture such as an alcohol through the membrane element from the first region to the second region at a higher rate than a second component of the fuel mixture such as a hydrocarbon. The separated alcohol and hydrocarbon components can be provided to the engine in varying relative amounts based on operating conditions.

Embodiments of systems and methods for tuning a turbine are provided. In one embodiment, a method may include receiving at least one of a measured operating parameter or a modeled operating parameter of a turbine during operation; and tuning the turbine during operation. The turbine may be tuned during operation by applying the measured operating parameter or modeled operating parameter or parameters to at least one operational boundary model, applying the measured operating parameter or modeled operating parameter or parameters to at least one scheduling algorithm, comparing the output of the operational boundary model or models to the output of the scheduling algorithm or algorithms to determine at least one error term, and closing loop on the one error term or terms by adjusting at least one turbine control effector during operation of the turbine.

In an engine having a plurality of cylinders in which a plurality of fuel injection valves are provided respectively, fuel is injected at a predetermined injection ratio, and an abnormality of air-fuel ratio variation is detected. If a fuel injection amount of at least one of the plurality of the fuel injection valves is smaller than a predetermined reference value, the fuel injection amount is increased so as to become equal to or larger than the reference value.

Methods and systems are provided for reducing late burn induced cylinder pre-ignition events. Forced entry of residuals from a late burning cylinder into a neighboring cylinder may be detected based on engine block vibrations sensed in a window during an open exhaust valve of the late burning cylinder. In response to the entry of residuals, a pre-ignition mitigating action, such as fuel enrichment or deactivation, is performed in the neighboring cylinder.

Provided is a timing adjustment system having improved control for achieving a target rotational phase. The valve timing adjustment system includes a displacement mechanism unit that displaces a rotational phase of a camshaft relative to a crankshaft of an internal combustion engine; a locking mechanism unit that locks the rotational phase at an intermediate locked phase positioned within a displacement range of the rotational phase; a hydraulic pathway that hydraulically drives the displacement mechanism unit and the locking mechanism unit; and a control unit including a control system that controls operations of the hydraulic control valve. The control unit changes a temporal responsiveness of the control system based on a displacement force that displaces the rotational phase.

Method and system for operating a compression engine on ether containing fuel obtained by conversion of a primary fuel based on alcohol comprising the steps and means for: (a) continuously withdrawing the primary fuel based on alcohol from a fuel tank and pressurising the primary fuel based on alcohol in its liquid form to a final engine injection pressure; (b) continuously introducing the pressurized primary fuel based on alcohol into a fuel accumulation chamber; (c) continuously distributing the pressurized primary fuel based on alcohol into pipes connecting the accumulation chamber with fuel injectors of the engine; (d) prior to the fuel injectors continuously converting the pressurised primary fuel based on alcohol to an ether containing fuel by contact with an alcohol dehydration catalyst being arranged in each of the pipes upstream the fuel injectors; (e) continuously injecting the ether containing fuel at injection pressure into the engine; and (f) continuously withdrawing a part of the introduced primary fuel based on alcohol from the accumulation chamber; and (g) depressurising and recycling the withdrawn primary fuel based on alcohol to the fuel tank.

A valve timing adjusting device for and engine includes a sprocket configured to rotate by receiving drive power from a driving shaft, a vane rotor fixed to a driven shaft so as to be rotatable relative to the sprocket, a housing that includes an oil chamber housing the vane rotor and is fixed to one end in a thickness direction of the sprocket, a bolt fixing the sprocket to the housing, and a knock pin inserted into a sprocket hole formed in the sprocket at one end thereof and into a housing hole formed in the housing at the other end thereof to restrict relative relation between the sprocket and the housing. The knock pin abuts against an inner wall of the sprocket hole at one end thereof, and abuts against an inner wall of the housing hole at the other end thereof.

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. Firstly, a selected memory cell of the memory array is determined, wherein one of the plural bit lines connected with the selected memory cell is a selected bit line and the other bit lines are unselected bit lines. Then, the unselected bit lines are precharged to a precharge voltage. Then, the selected bit line is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to at least one result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

To provide a magnetic element capable of performing skyrmion transfer, a skyrmion memory to which this magnetic element is applied, and a shift register, for example, a magnetic element capable of performing skyrmion transfer is provided, the magnetic element providing a transverse transfer arrangement in which the skyrmion is transferred substantially perpendicular to a current between an upstream electrode and a downstream electrode, and including a plurality of stable positions in which the skyrmion exists more stably than in other regions of a magnet, and a skyrmion sensor that detects a position of the skyrmion.

To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a β-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter λ being generated, is such that 2λ>Wm>λ/2 and 2λ>hm>λ/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that λ≧W>λ/4 and 2λ>h>λ/2.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

An SRAM includes an SRAM array comprising a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N− well, an oxide layer deposited on the N− well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.

The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising:first and second conduction electrodes (201, 202);a channel zone (203) arranged between the first and second conduction electrodes;a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222);an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·λ>Wm≧λ, where λ denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·λ>Hm≧λ, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.