A device for injecting fuel over a cylinder head of an engine, including a tubular body, an injection nozzle forming an extension of the tubular body, a needle extending coaxially to the nozzle in a form of a rod, an end of which includes a head forming a valve on a seat supported by the injection nozzle, and an actuator configured to cause a movement of the head so as to open the valve, the needle configured to axially resonate when the same is subjected to axial pulses at a predetermined nominal frequency by the actuator. A system for mounting the device includes a spacer for bearing on the cylinder head, as well as on a front surface of the tubular body at the connection to the nozzle.

A fastening structure of a fuel delivery pipe and a cylinder head of an internal combustion engine includes three or more bosses provided on each of the cylinder head and the fuel delivery pipe, and fastening portions formed by bolting the bosses on the cylinder head to the bosses on the fuel delivery pipe. The fastening portions at both end portions of the fuel delivery pipe are less rigid than one or more fastening portions in a middle between the fastening portions positioned at both end portions of the fuel delivery pipe.

An electromagnetically actuable valve, e.g., a fuel injector for fuel-injection systems of internal combustion engines, includes an electromagnetically actuable actuating element having a solenoid coil, a fixed core, a valve jacket, and a movable armature for actuating a valve-closure element, which cooperates with a valve-seat surface provided on a valve-seat body. A sleeve-shaped guide element is introduced into an inner longitudinal bore of the armature and into an inner flow bore of the internal pole, the guide element being firmly fixed in place in the armature or the inner pole, and loosely guided in the respective other component.

A vapor purge valve in an engine is provided. The vapor purge valve includes a purge valve inlet, a purge valve outlet, and a muffler including a housing at least partially enclosing a diffuser in fluidic communication with the purge valve inlet and the purge valve outlet.

An exhaust gas recirculation device is provided. The device recirculates, from an exhaust system to an intake system, a part of exhaust gas from a plurality of cylinders of a multi-cylinder engine as EGR gas. The device includes a single EGR pipe extending from the exhaust system toward the intake system, an EGR manifold branching from a downstream end portion of the EGR pipe toward each cylinder, and an EGR valve for adjusting an EGR gas amount. The EGR manifold has one or more common EGR passages having a single pipe portion and branched pipe portions, and one or more independent EGR passages. Each shape of the common and independent EGR passages is set so that a communicating path in the EGR manifold communicating an arbitrary cylinder with a cylinder where combustion is performed subsequently thereto has the same volume for any cylinder combination having the adjacent combustion order.

A system for a cylinder head is provided. The system comprises a cam cover mounted on the cylinder head and including an oil separator and a coil on plug (COP) coupled to the oil separator via a snap-fit connection. The snap-fit connection holds the coil-on-plug in position and may provide a lower cost alternative to existing systems of retaining coil-on-plugs on a cam cover.

According to the present disclosure, a fuel supply system having a recirculation loop is provided. The fuel supply system comprises a fuel tank; a return line coupled fluidly to the fuel tank; a fuel manifold; and a recirculation loop, wherein the return line is coupled fluidly to the recirculation loop at a first node to return fuel from the recirculation loop to the fuel tank, and the recirculation loop comprises a heat exchanger positioned downstream of the fuel manifold and upstream of the first node. The recirculation loop may comprise an orifice positioned upstream of the heat exchanger and downstream of the fuel manifold. Additionally, the fuel supply system may further comprise a supply line coupled fluidly to the fuel tank and further coupled fluidly to the recirculation loop at a second node positioned upstream of the fuel manifold and downstream of the first node.

In an engine having a plurality of cylinders in which a plurality of fuel injection valves are provided respectively, fuel is injected at a predetermined injection ratio, and an abnormality of air-fuel ratio variation is detected. If a fuel injection amount of at least one of the plurality of the fuel injection valves is smaller than a predetermined reference value, the fuel injection amount is increased so as to become equal to or larger than the reference value.

A variable valve operating apparatus for an internal combustion engine includes a drive camshaft, and a driven cam lobe that is rotatably supported by the drive camshaft. The variable valve operating apparatus further includes a control sleeve that has a raceway surface, a center of which is eccentric with respect to a center of rotation of its own. The variable valve operating apparatus further includes a link mechanism that is connected to each of the drive camshaft and the driven cam lobe and has a control roller which is in contact with the raceway surface. The variable valve operating apparatus further includes an actuator that drives the control sleeve. The variable valve operating apparatus further includes a control amount of the actuator is controlled to change a moving amount of the raceway surface in the above described plane direction in accordance with an operation condition of an internal combustion engine.

Provided is a timing adjustment system having improved control for achieving a target rotational phase. The valve timing adjustment system includes a displacement mechanism unit that displaces a rotational phase of a camshaft relative to a crankshaft of an internal combustion engine; a locking mechanism unit that locks the rotational phase at an intermediate locked phase positioned within a displacement range of the rotational phase; a hydraulic pathway that hydraulically drives the displacement mechanism unit and the locking mechanism unit; and a control unit including a control system that controls operations of the hydraulic control valve. The control unit changes a temporal responsiveness of the control system based on a displacement force that displaces the rotational phase.

A valve timing adjusting device for and engine includes a sprocket configured to rotate by receiving drive power from a driving shaft, a vane rotor fixed to a driven shaft so as to be rotatable relative to the sprocket, a housing that includes an oil chamber housing the vane rotor and is fixed to one end in a thickness direction of the sprocket, a bolt fixing the sprocket to the housing, and a knock pin inserted into a sprocket hole formed in the sprocket at one end thereof and into a housing hole formed in the housing at the other end thereof to restrict relative relation between the sprocket and the housing. The knock pin abuts against an inner wall of the sprocket hole at one end thereof, and abuts against an inner wall of the housing hole at the other end thereof.

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. Firstly, a selected memory cell of the memory array is determined, wherein one of the plural bit lines connected with the selected memory cell is a selected bit line and the other bit lines are unselected bit lines. Then, the unselected bit lines are precharged to a precharge voltage. Then, the selected bit line is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to at least one result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

To provide a magnetic element capable of performing skyrmion transfer, a skyrmion memory to which this magnetic element is applied, and a shift register, for example, a magnetic element capable of performing skyrmion transfer is provided, the magnetic element providing a transverse transfer arrangement in which the skyrmion is transferred substantially perpendicular to a current between an upstream electrode and a downstream electrode, and including a plurality of stable positions in which the skyrmion exists more stably than in other regions of a magnet, and a skyrmion sensor that detects a position of the skyrmion.

To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a β-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter λ being generated, is such that 2λ>Wm>λ/2 and 2λ>hm>λ/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that λ≧W>λ/4 and 2λ>h>λ/2.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

An SRAM includes an SRAM array comprising a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·λ>Wm≧λ, where λ denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·λ>Hm≧λ, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

An electronic device includes a semiconductor memory that includes: a memory cell coupled between a first line and a second line; a first selection block configured to select the first line; a second selection block configured to select the second line; an alternate current supply block configured to supply, during a read operation, an alternate current corresponding to a resistance state of the memory cell; and a sensing block configured to sense, during the read operation, at least one of a cell current flowing through the memory cell and the alternate current.

Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

A mechanism that allows the successful decoding of MCS information of cell edge UEs while retaining the performance for the other UEs of the cell is provided. In one aspect, a UE may determine an uplink control coding rate based on an uplink signal quality. The UE may encode uplink control data based on the uplink control coding rate. The UE may apply a pattern of unused resource element locations in uplink control resource elements based on the uplink control coding rate. The UE may transmit the uplink control resource elements with the pattern of unused resource element locations. In another aspect, an eNB may receive uplink control resource elements. The eNB may determine an uplink control coding rate based on a pattern of resource element locations in the uplink control resource elements. The eNB may decode uplink control data based on the uplink control coding rate.

A VDC resource request method, user equipment, and a base station, where the VDC resource request method includes sending, by user equipment, a VDC resource request message to a base station when the user equipment needs to request a VDC resource for sending vehicle service information, where the VDC resource request message includes at least one piece of the following information: a VDC resource status list, or travel information of the user equipment, and an available VDC resource is indicated in the VDC resource status list, receiving a VDC resource allocation indication message from the base station, and sending the vehicle service information by using the VDC resource indicated by the VDC resource allocation indication message.