A fixture for attachment of an end of a member, such as a wind turbine tower section, blade or hub for a wind turbine characteristically has an end flange. To enable clamping while being able to compensate for different hole patterns in the flanges, by the invention, the fixture provides for retaining of ends of members with flanges, regardless of flange diameter and hole patterns, and which is also quickly and easily installed. Additionally, it is possible to firmly clamp the flange end to upstanding frame parts of the fixture with fastening elements, thereby providing a stable connection between a console of the fixture and the upstanding frame parts.

An apparatus and method for providing a removable anchor for use in tying down a load, or for securing a winch cable for use in recovering a disabled vehicle or other load. The anchor may be removably attached to the deck/bed of a trailer or vehicle (e.g., a car carrier or wrecker/tow truck), using one or more slots or stake pockets located on a cargo surface of the deck. The removable anchor may include: a projection member shaped and sized to fit into a slot on the cargo surface, or to protrude through a stake pocket; a crown attached to, or integrally forming a part of, the projection member, and configured to receive and anchor one or more tie down connectors; and a key attached to, or integrally forming a part of, the projection member. The key can be passed into the slot and manipulated between removable and locked positions. Alternatively, the key may be used to removably secure the anchor to the stake pocket.

A cargo rack for transferring loads between a marine vessel and an offshore marine platform provides a frame having a front, a rear, and upper and lower end portions. The lower end of the frame has a perimeter beam base, a raised floor and a pair of open-ended parallel fork tine tubes that communicate with the perimeter beam at the front and rear of the frame. The frame includes a plurality of fixed side walls extending upwardly from the perimeter beam. A plurality of gates are movably mounted on the frame, each gate being movable between open and closed positions, the gates enabling a forklift to place loads on the floor. The frame has vertically extending positioning beams that segment the floor into a plurality of load-holding positions. Each load holding position has positioning beams that laterally hold a load module in position on the floor.

Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

An intelligent current drive is disclosed that couples an active current source to a bus line to increase the rate of pull-up and decouples the active current source from the bus line prior to reaching the desired pull-up voltage.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

A circuit for a single differential-inductor oscillator with common-mode resonance may include a tank circuit formed by coupling a first inductor with a pair of first capacitors; a cross-coupled transistor pair coupled to the tank circuit; and one or more second capacitors coupled to the tank circuit and the cross-coupled transistors. The single differential-inductor oscillator may be configured such that a common mode (CM) resonance frequency (FCM) associated with the single differential-inductor oscillator is at twice a differential resonance frequency (FD) associated with the single differential-inductor oscillator.

The present disclosure relates to nanoresonator oscillators or NEMS (nanoelectromechanical system) oscillators. A circuit for measuring the oscillation frequency of a resonator is provided, comprising a first phase-locked feedback loop locking the frequency of a controlled oscillator at the resonant frequency of the resonator, this first loop comprising a first phase comparator. Furthermore, a second feedback loop is provided which searches for and stores the loop phase shift introduced by the resonator and its amplification circuit when they are locked at resonance by the first loop. The first and the second loops operate during a calibration phase. A third self-oscillation loop is set up during an operation phase. It directly links the output of the controllable phase shifter to the input of the resonator. The phase shifter receives the phase-shift control stored by the second loop.

A resonator element includes a substrate including a first principal surface and a second principal surface respectively forming an obverse surface and a reverse surface of the substrate, and vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on the first principal surface, and a second excitation electrode disposed on the second principal surface, and being larger than the first excitation electrode in a plan view, the first excitation electrode is disposed so as to fit into an outer edge of the second excitation electrode in the plan view, and the energy trap confficient M fulfills 15.5≦M≦36.7.

A resonator element includes a substrate vibrating in a thickness-shear vibration mode, a first excitation electrode disposed on one principal surface of the substrate, and has a shape obtained by cutting out four corners of a quadrangle, and a second excitation electrode disposed on the other principal surface of the substrate, and a ratio (S2/S1) between the area S1 of the quadrangle and the area S2 of the first excitation electrode fulfills 87.7%≦(S2/S1)

A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

A self-feedback random generator comprises a digital-to-analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal. The first D-type flip-flop receives the second digital oscillating signal and a clock signal, and reads the second digital oscillating signal through utilizing the clock signal so as to outputs the digital random-code signal, wherein frequency of the clock signal is smaller than frequency of the first digital oscillating signal, and random of frequency of the second digital oscillating signal corresponds to random of the digital random-code signal.

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

The invention concerns an oscillator generating a wave composed of a frequency of on the order of terahertz from a beat of two optical waves generated by a dual-frequency optical source. The oscillator includes a modulator the transfer function of which is non-linear for generating harmonics with a frequency of less than one terahertz for each of the optical waves generated by the dual-frequency optical source, an optical detector able to detect at least one harmonic for each of the optical waves generated by the dual-frequency optical source and transforming the harmonics detected into an electrical signal, a phase comparator for comparing the electrical signal with a reference electrical signal, and a module for controlling at least one element of the dual-frequency optical source with a signal obtained from the signal resulting from the comparison.

A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

The present invention discloses an Oven Controlled Crystal Oscillator and a manufacturing method thereof. The Oven Controlled Crystal Oscillator comprises a thermostatic bath, a heating device, a PCB and a signal generating element, where the signal generating element is used for generating a signal of a certain frequency, the heating device, the PCB and the signal generating element are mounted in the thermostatic bath, the signal generating element is mounted in a groove formed on one side of the PCB, while the heating device is mounted against the other side of the PCB that is opposite to the groove. The signal generating element may be a passive crystal resonator or an active crystal oscillator. The Oven Controlled Crystal Oscillator according to the invention is advantageous for a small volume and a high temperature control precision.

An atomic oscillator includes: a gas cell which includes two window portions having a light transmissive property and in which metal atoms are sealed; a light emitting portion that emits excitation light to excite the metal atoms in the gas cell; a light detecting portion that detects the excitation light transmitted through the gas cell; a heater that generates heat; and a connection member that thermally connects the heater and each window portion of the gas cell to each other.

An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

A method, an apparatus, and a computer program product are provided. The apparatus tunes a frequency provided by a VCO. The apparatus determines a relative capacitance change associated with a first frequency and a desired frequency from a look-up table. The apparatus adjusts a capacitor circuit in the VCO based on the determined relative capacitance change determined from the look-up table in order to tune from the first frequency to the desired frequency. The apparatus determines that the frequency provided by the VCO is a second frequency different than the desired frequency after adjusting the capacitor circuit. The apparatus performs an iterative search to further adjust the capacitor circuit when a difference between the second frequency and the desired frequency is greater than a threshold.

A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.

A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

The invention relates to a method for operating control equipment (1) of a resonance circuit (2), wherein the control equipment (1) comprises at least two circuit elements (8, 9) connected in series, in particular each comprising a recovery diode (13, 14) connected in parallel, between which a connection (6) of the resonance circuit (2) is connected. According to the invention, the circuit elements (8, 9) are actuated as a function of the voltage detected at the connection (6). The invention further relates to control equipment (1) of a resonance circuit (2).

Embodiments of the present invention provide a temperature compensation method and a crystal oscillator, where the crystal oscillator includes a crystal oscillation circuit unit, a temperature sensor unit, an oscillation controlling unit, a relative temperature calculating unit, and a temperature compensating unit. The temperature sensor unit measures a measured temperature of the crystal oscillation circuit unit; the relative temperature calculating unit obtains a temperature difference between the measured temperature and a reference temperature; the temperature compensating unit obtains a temperature compensation value corresponding to the temperature difference from a temperature-frequency curve; and the oscillation controlling unit generates a frequency control signal, according to a frequency tracked by a communications AFC device and the temperature compensation value, thereby controlling a frequency of the crystal oscillation circuit unit to work on the tracked frequency.

A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

The switching element is provided in a state of being electromagnetically coupled to the cavity resonator of the high frequency oscillator; the bias voltage applying terminal is connected to one electrode of the switching element; another electrode of the switching element is electrically connected to the cavity resonator (the anode shell in FIG. 1); the metal plate having a size enough for reflecting an electric wave to be transmitted before and after the switching element in a high-frequency manner is provided at any one end of the switching element; and by applying a bias voltage to the switching element and varying that, a reactance of the switching element is changed and a resonance frequency of the cavity resonator is varied. By this method, an oscillation frequency can be varied greatly relative to a small change in a bias voltage.

Arrays of resonator sensors include an active wafer array comprising a plurality of active wafers, a first end cap array coupled to a first side of the active wafer array, and a second end cap array coupled to a second side of the active wafer array. Thickness shear mode resonator sensors may include an active wafer coupled to a first end cap and a second end cap. Methods of forming a plurality of resonator sensors include forming a plurality of active wafer locations and separating the active wafer locations to form a plurality of discrete resonator sensors. Thickness shear mode resonator sensors may be produced by such methods.

A solenoid actuator comprising an armature member that engages a spool including a spool cap on an end of the spool that is axially movable relative to the spool. A bore in the spool allows fluid to flow from a control port to the spool cap, such that pressure is established in the spool cap. The pressure established in the spool cap acts on the spool with a force directly proportional to the control pressure and the fluid-contacting area inside the spool cap.

This invention relates to a novel rotary control valve with new joint methods and flow control mechanisms, inline-reparability and fully metal seals more particularly to a triple offset butterfly valve or ball valve with those features used for on-off and flow controlling under multiple extreme conditions or in severe services; such as the integrated gasification combined cycle under high temperature and pressure, Fluid Catalytic Cracking under high temperature over 1200 F with hard diamond like catalytic particles, shale fracking process under extreme high pressure and high velocity fluid with solid particles and corrosive additives and other critical applications for products life lasting 5 to 30 years like deepsea flow control systems and nuclear power plants and for the applications of millions cycles like jet or rocket turbine engine fuel delivery systems with high velocity fuel fluid mixed with highly oxidative gas under temperature 1365 F.

A solenoid valve includes a plunger, an actuating device, and an air tap assembly. The plunger is connected to the actuating device. The air tap assembly is secured to the actuating device and has a cavity. The air tap assembly includes a main body, and first and second tubes. The first tube protrudes from the main body and defines a first through hole. The main body defines a second through hole communicated with the first through hole and the cavity. The second tube defines a third through hole. The main body defines a fourth through hole extended from the third through hole and a fifth through hole extended from the fourth through hole to the cavity. The fifth and second through holes are parallel. The plunger head is used to seal the second and fifth through holes.

An assembly structure of an electronic control unit and a coil assembly of a solenoid valve for an electronic brake system connected to the electronic control unit having a printed circuit board and applying power to the solenoid valve. The coil assembly is penetrated to allow an upper portion of the solenoid valve to be fitted thereinto, and includes a cylindrical bobbin provided with a coil and a coil case. The electronic control unit is provided with a housing having an insertion groove and joined to the hydraulic control unit, the printed circuit board being disposed spaced apart from the coil assembly, and the housing is provided with an elastic member having one end contacting the printed circuit board and the other end contacting the coil case. The elastic member is configured with a coil spring to produce different elastic forces.

Pressure relief/drainage valve for a concrete pumper having a valve body with an axially extending passageway through which concrete flowing in a pumping line passes, an outlet port in a side wall of the passageway, and a valve member which prevents concrete from passing through the port when the valve is a closed position and permits concrete to discharge through the outlet port when the valve is in an open position.

Power-efficient actuator apparatus and methods. In one exemplary embodiment, the actuator assembly utilizes a shape memory alloy (SMA) filament driven by an electronic power source to induce movement in the underlying assembly to actuate a load (e.g., water valve). In addition, a circuit board is included which allows the actuator assembly to be readily incorporated or retrofit into a wide range of systems such that the signal characteristics of the supply line can, among other applications, be conditioned in order to protect the SMA filament. Furthermore, the circuit board can also readily be adapted for use with “green” power sources such as photovoltaic systems and the like. Methods for manufacturing and utilizing the aforementioned actuator assembly are also disclosed.

A direct acting solenoid actuator includes an armature and associated push pin that are suspended from certain fixed solenoid components, such as a pole piece and/or flux sleeve, by a fully floating cage of rolling elements. The fixed solenoid component may comprise a pole piece and/or a flux sleeve. The pole piece may include stops to limit movement of the cage of rolling elements in the axial direction.

A flow control valve element has a generally spherical ball. An inlet is formed in the ball. An outlet is also formed in the ball, the outlet opposing the inlet. A hollowed-out portion extends between the inlet and the outlet. A pair of opposing flats are formed in the ball, the flats each having a first flat portion formed in an external portion of the ball and an opposing second flat portion formed in the hollowed-out portion of the ball.

A method and device for the production of books, including: moving book blocks successively along a conveying section of a book production line; supplying a stack of book cases to the book production line; identifying a marking on each of the book blocks and the book cases; transmitting an identified marking on at least one book case to a machine control of the book production line; assigning a dataset stored in the machine control for a sequence of book cases to the supplied stack; determining a sequence in the machine control for book blocks positioned on the conveying section; comparing the dataset for the sequence of the book cases to the sequence of the book blocks; and removing and/or supplying at least one book block from or to the conveying section if the sequence of the book blocks deviates from the sequence of the book cases using the machine control.

A method for operating a processing system, in which product units of different formats are processed. The processing system contains a plurality of processing devices that are arranged one after the other in a processing line. In the event of a format changeover, certain component arrangements arranged in the processing system must be adapted to the new product format. In the event of an upcoming format change, a gap in the conveyed goods is generated while the conveying operation is maintained, wherein the gap in the conveyed goods runs through the processing system along the processing devices. As soon as the gap in the conveyed goods runs through a component arrangement to be adapted to the new format, the format is changed over at the component arrangement while the gap in the conveyed goods runs through the component arrangement.

In a first step, in a printed material web (1) moved in a feed direction, a first material web part (5) which is formed by a material web section (1a)is folded against the rest of the material web (6) that is formed from two material web portions (1b, 1c)).In the region of a connecting line (2b) extending between neighbouring material web sections (1b, 1c) the two material web parts (5,6) are connected to one another by a means of a bonding adhesive. In a subsequent step the material web (1) is folded again along a line (2b) extending between two neighbouring material web sections. (1b, 1c)All material web sections (1a, 1b, 1c) lie above one another. Subsequently, multi-page sub-products (11), the pages (12a, 12b, 12c) of which are connected to one another in the region of the spine (13) of the sub-product, are separated from the twice-folded material web (1). Finally, the sub-products (11) are placed on top of one another to form a stack (16) and are connected to one another in the region of the spine (13) thereof by means of a bonding adhesive.