A method for operating a thread stitching machine for processing printed sheets to form book blocks includes providing at least one sewing station with an active connection to at least one stitching saddle and providing the at least one stitching saddle with an active connection to at least one transporting system. The printed sheets are supplied to the at least one stitching saddle, using the at least one transporting system, in at least one of a substantially vertical and a substantially horizontal plane relative to the at least one stitching saddle. At least the printed sheets in the substantially vertical plane are supplied directly onto the at least one stitching saddle or to a region of the at least one stitching saddle. The printed sheets are supplied to the at least one sewing station resting astride the at least one stitching saddle.

In an embodiment, a processor-readable medium stores code representing instructions that when executed by a processor cause the processor to receive sheet length data for two paper sheets of a same standard dimension passing consecutively through a printing device. The processor calculates a length difference between the two paper sheets, and when the length difference exceeds a two-sheet threshold, it initiates an alignment correction cycle in a paper finishing device.

This invention provides a technique of preventing a collision between an original document and a printing material on a conveyance path when an image forming apparatus executes both additional printing on the original document and printing on the printing material. In a case where both additional printing on an original document and printing on a printing material are executed, the image forming apparatus according to one aspect of the invention conveys a read original document to a transfer unit through a conveyance path commonly used for an original document and sheet, and prints an image to be added on the original document. After the original document is conveyed to the transfer unit through the conveyance path, the image forming apparatus feeds a sheet from a sheet feeding unit to the conveyance path, and performs copying on the sheet in the transfer unit.

A printing control apparatus according to one aspect of this invention controls to print images on sheets based on image data of a plurality of pages, generate a bookbinding product by executing folding processing for the image-printed sheets, and output the bookbinding product. The printing control apparatus further accepts the position of an insertion sheet to be inserted into the sheets for which the folding processing is executed, and controls to output a plurality of bookbinding products by using, as a reference, the accepted position of the insertion sheet.

A creasing device forms a crease in a to-be-folded portion of a sheet. The creasing device includes a sheet-information reading unit that reads any one of sheet information and binding information; a determining unit that determines a surface, on which the crease is to be formed, of the sheet according to the one of the sheet information and the binding information read by the sheet-information reading unit; and a creasing unit that forms the crease on the surface determined by the determining unit.

Disclosed is an image forming system including: the relay apparatus; the image forming device which is connected to the first communication control unit of the relay apparatus and which acquires the sheet interval information of the downstream post-processing device through the first communication system; and the second post-processing device which is connected to the second communication control unit of the relay apparatus, the second post-processing device being compliant with the second communication system.

An image recording apparatus includes: a recording unit for recording an image on a recording medium; a tray for supporting the recording medium recorded by the recording unit; a conveyor mechanism for conveying the recorded medium to the tray; and an alignment mechanism for aligning a plurality of recording media stacked on the tray, by application of an external force. In a period from a start to an end of recording based on one recording job, the alignment mechanism aligns the plurality of recording media stacked on the tray in a period in which image recording is not performed, and the alignment mechanism does not align the plurality of recording media stacked on the tray in a period in which image recording is being performed.

Disclosed is an image forming system including: an image forming device to notify a downstream post-processing device of sheet information relating to a sheet on which an image is formed, before the sheet is discharged, and to notify the downstream post-processing device of set separation information indicating a final sheet of each set of document in synchronization with the sheet information relating to the final sheet of each set in case that a plurality of sets of document are printed, the image forming device being compliant with a first communication system; a post-processing device which is connected to a downstream of the image forming device and is compliant with a second communication system which is different from the first communication system; and the relay apparatus which is connected to the image forming device through the first communication system and is connected to the post-processing device through the second communication system.

An apparatus for processing sheets of different formats, the apparatus including a feeding device that feed sheets of different formats in a feeding direction one behind the other, and at a certain conveying speed, at least two collecting drums disposed downstream of the feeding device, the at least two collecting drums having cylindrical lateral surfaces that rotate about an axis of rotation, securing means for temporarily securing the fed sheets on a circumference of the at least two collecting drums, a drive device that drives the collecting drums in rotation at a circumferential speed that corresponds to the conveying speed of the feeding device, and a sensing device for sensing the sheets of different formats moving past is arranged along the conveying path and senses the leading edge of the sheets of different formats, as seen in the feeding direction, or markings applied to the sheets of different formats.

The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width.

An apparatus including a die including a dielectric material on a device side, an insulating layer surrounding a die area and embedding a thickness dimension of the die; and a carrier including a plurality of layers of conductive material disposed on the device side of the die, a first one of the layers of conductive materials being formed on the insulating layer and patterned into traces at least a portion of which are connected to respective contact points on the die. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; disposing a mold on the sacrificial substrate around; introducing an insulating material into a chase of the mold; removing the mold; forming a carrier on the insulating material adjacent a device side of a die; and separating the die and the carrier from the sacrificial substrate.

In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first nickel-containing layer and a second nickel-containing layer, a first copper-containing layer between the first nickel-containing layer and the solder joint portion, and a second copper-containing layer between the second nickel-containing layer and the solder joint portion.

Described herein are methods and systems for providing corrective maintenance using global knowledge sharing. A method to provide corrective maintenance with a CM system includes performing a query to generate a ranking of fixable causes based on factors (e.g., symptoms, configuration, test). The ranking may be determined based on a fixable cause percent match with the factors. The ranking of fixable causes may be associated with one or more solutions for each fixable cause. The ranking can be updated based on performing tests or solutions.

Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

An opposed substrate (9') comprises: a substrate (1); a static electricity protective electrode (2), a bridging electrode (4) and a touch induction electrode (6) comprising a plurality of sub-units sequentially formed on the substrate (1), wherein the distribution of the static electricity protective electrode (2) on the substrate (1) corresponds to dummy regions between sub-units, and the static electricity protective electrode (2), the bridging electrode (4) and the touch induction electrode (6) are insulated from each other. The opposed substrate (9') has a good touching effect. A method for manufacturing the opposed substrate, and a liquid crystal display touch panel are also disclosed.

Provided is a back plate component having reflective sheet reinforcing structure. The back plate component includes: a frame, a reflective sheet and a plurality of supporting film sheets. The frame includes a plurality of lateral beams and vertical beams, and at least one hollow part is included between the lateral beams and the vertical beams. The reflective sheet is attached to the frame, and includes a reflective surface and a back surface corresponding to the reflective surface. A portion of the back surface covers the whole hollow part. The plurality of supporting film sheets is attached to the back surface at a region corresponding to the hollow part, and includes a material the same as that of the reflective sheet. A liquid crystal display device is further disclosed herein.

A liquid crystal display device includes a liquid crystal display element including a first alignment film and a second alignment film and a liquid crystal layer that is provided between the first alignment film and the second alignment film, wherein the first alignment film includes a compound in which a polymer compound that includes a cross-linked functional group or a polymerized functional group as a side chain is cross-linked or polymerized, the second alignment film includes the same compound as the compound that configures the first alignment film, and the formation and processing of the second alignment film is different from the formation and processing of the first alignment film and when a pretilt angle of the liquid crystal molecules which is conferred by the first alignment film is θ1 and a pretilt angle of the liquid crystal molecules which is conferred by the second alignment film is θ2, θ1>θ2.

A pixel structure comprises a plurality of pixel regions, and each of the pixel regions includes first and second electrodes that are overlapped with each other, the first electrode is disposed above the second electrode, and each of the pixel regions is divided at least into a first to fourth domain display regions; strip-shaped first electrodes in the first to fourth domain display regions make first to fourth angles with a reference direction; the sum of the first angle and the second angle is 180 degrees, the sum of the third angle and the fourth angle is 180 degrees, and the first, the second, the third and the fourth angles are different from one another.

The present invention discloses a tape substrate for chip on film structure of a liquid crystal panel. The tape substrate is provided with plural package units of chip on film structures arranged along its longitudinal direction, and the package unit has a driver chip, input leads and output leads. The longitudinal direction of the driver chip is parallel to the longitudinal direction of the tape substrate, and the input leads and the output leads are located at the two opposite sides of the driver chip. Each package unit is set up with a short side and a long side, and the input leads are formed at the short side, while the output leads are formed at the long side. In the package units adjacent to each other, the short side of one package unit joins the long side of a next package unit. This invention further discloses a liquid crystal panel having the tape substrate.

A display apparatus includes a lower substrate, an upper substrate, a spacer and an image display layer. The spacer includes a main spacer, a first sub-spacer and a second sub-spacer. The main spacer has a height greater than that of the first and second sub-spacers. The second sub-spacer has an area wider than that of the main spacer and the first sub-spacer.

An optical element includes at least two stacked birefringent layers having respective local optical axes that are rotated by respective twist angles over respective thicknesses of the at least two layers, and are aligned along respective interfaces between the at least two layers. The respective twist angles and/or the respective thicknesses are different. The at least two stacked birefringent layers may be liquid crystal polymer optical retarder layers. Related devices and fabrication methods are also discussed.

A multilayered cell culture apparatus for the culturing of cells is disclosed. The cell culture apparatus is defined as an integral structure having a plurality of cell culture chambers in combination with tracheal space(s). The body of the apparatus has imparted therein gas permeable membranes in combination with tracheal spaces that will allow the free flow of gases between the cell culture chambers and the external environment. The flask body also includes an aperture that will allow access to the cell growth chambers by means of a needle or cannula. The size of the apparatus, and location of an optional neck and cap section, allows for its manipulation by standard automated assay equipment, further making the apparatus ideal for high throughput applications.

Constant-temperature equipment wherein mechanical and electrical structures are eliminated from the inside of a temperature-controlled chamber (15) by using a non-contact magnetic arrangement as a drive transmission for a sample table (5) and a sample table drive mechanism (6), thus reducing failure and enhancing maintainability. In addition, a conveyance mechanism (11) is provided with a pass box adjacent which sliding shielding plates (9) are stacked vertically, and the shielding plates (9) are linked with the conveyance mechanism (11) by an engaging mechanism provided in the conveyance mechanism (11) to allow the plates to be opened and closed by a travel mechanism (12), thus simplifying the structure and minimizing change in atmosphere during conveying. The sample table drive mechanism (6) and the conveyance mechanism (11) can be attached removably to the temperature-controlled chamber (15) to permit sterilization at high temperature.

Provided is constant-temperature equipment wherein maintenance is facilitated with the least failure, and highly reliable culturing and testing can be carried out. Mechanical and electrical structures are eliminated from the inside of a temperature-controlled chamber (15) by using a non-contact magnetic arrangement as a drive transmission for a sample table (5) and a sample table drive (6), thus reducing failure and enhancing maintainability. In addition, a conveyor (11) is provided with a pass box to minimize change in atmosphere during conveying. The sample table drive (6) and the conveyor (11) can be attached removably to the temperature-controlled chamber (15) to permit sterilization at high temperature.

The present invention relates to an anti-human α9 integrin antibody. More particularly, the present invention relates to: a monoclonal antibody, a chimeric antibody, a humanized antibody and a human antibody that specifically recognize human α9 integrin; a hybridoma cell that produces the monoclonal antibody; a method for producing the monoclonal antibody; a method for producing the hybridoma cell; a therapeutic agent comprising the anti-human α9 integrin antibody; a diagnostic agent comprising the human α9 integrin antibody; and a method for screening for a compound that inhibits the activity of human α9 integrin.

A method of expanding and maintaining human embryonic stem cells (ESCs) in an undifferentiated state by culturing the ESCs in a suspension culture under culturing conditions devoid of substrate adherence is provided. Also provided are a method of deriving ESC lines in the suspension culture and methods of generating lineage-specific cells from ESCs which were expanded in the suspension culture of the present invention.

Thrombospondin 1 (TSP-1), TSP-2, interleukin 17B receptor (IL-17BR) and heparin-binding epidermal growth factor-like growth factor (HB-EGF) associated with stem cell activity and use thereof.

Methods of washing adherent cells, capable of effectively suppressing cell death due to proteolytic enzyme treatment for detaching the adherent cell from a culture vessel and subsequent cell treatment; cell-washing solutions used for the washing method; methods of producing cell suspensions for transplantation using the cell-washing solution; and kits comprising the cell-washing solution. Trehalose or its derivative or a salt thereof is added to physiological aqueous solutions to prepare cell-washing solutions containing trehalose or its derivative or a salt thereof as an active ingredient. The cell-washing solutions can be used to wash adherent cells before detaching the adherent cells from a culture vessel by proteolytic enzyme treatment to suppress cell death due to the proteolytic enzyme treatment. The concentration of trehalose applied to the cell-washing solution may be a concentration capable of suppressing the cell death due to the proteolytic enzyme treatment, such as 0.1 to 20 (w/v) %.

Methods and compositions for targeted delivery of biotherapeutics are provided. The compositions comprise bile-sensitive St. thermophilus bacteria modified to release a biotherapeutic agent following bile exposure. Biotherapeutic agents released by the St. thermophilus bacteria disclosed herein include AQ and AQR rich peptides. Methods of the invention comprise administering to a subject a St. thermophilus bacterium modified to release a biotherapeutic agent following bile exposure. Administration of the St. thermophilus bacterium promotes a desired therapeutic response. The bacterium may be modified to express and release AQ or AQR rich peptides which subsequently inhibit cellular apoptosis or reduce mucosal damage. Thus, methods of the invention find use in treating or preventing a variety of gastrointestinal disorders including C. difficile infection and antibiotic-associated diarrhea.

The invention provides an improved design for the construction of extensible nucleic acid-based, ligand-controlled regulatory systems, and the nucleic acid regulatory systems resulting therefrom. The invention contemplates improving the design of the switches (ligand-controlled regulatory systems) through the design of an information transmission domain (ITD). The improved ITD eliminates free-floating ends of the switching and the competing strands, and localizes competitive hybridization events to a contiguous strand of competing and switching strands in a strand-displacement mechanism-based switch, thereby improving the kinetics of strand-displacement. The improved regulatory systems have many uses in various biological systems, including gene expression control or ligand-concentration sensing.

Disclosed are new members of a class of non-lipid small molecule inhibitors which interfere with the interaction between phosphoinositol-3,4,5-triphosphate (PIP3) and pleckstrin homology (PH) domains. These molecules target a broad range of PIP3-dependent signaling events in vitro and exert significant anti-tumor activity in vivo, with improved activity and selectivity toward particular PH domains. The small molecule inhibitors of the invention can be used alone or together with tumor necrosis factor (TNF)-related apoptosis-inducing ligand (TRAIL) or other cancer medicament to treat cancer. Small molecule inhibitors of the invention act synergistically in combination with TRAIL and with other Akt inhibitors in treating cancer. Pharmaceutical compositions and methods for treating cancer are provided.