NA

Mirroring your smartphone’s screen onto a Windows/Mac PC is fairly simple with these apps.

Need more space on your Google Account? Here are a few tips to help you free up more space in your Google Account. We've listed down six different methods to help you free up more space

Microsoft Ads on File Explorer were subject to widespread criticism and the company claimed it was “experimental” and “turned off”. But, there are other Windows 10 or Windows 11 ads you may want to get rid of.

Any State Bank of India account holder in order to activate their ATM card or a debit card can go to the online portal of SBI and do so by clicking on the e-services tab.

Always wanted to edit your PDF files for free on mobile or laptop, but don’t know how? Here’s a guide to follow.

You can now port from Airtel to Jio and vice versa through these easy 4 steps.

With containers, you can build once, run anywhere – no worries about underlying dependencies.

The post How containers have moved us to next-gen virtualization appeared first on The Data Roundtable.

A man climbed an electric tower in Uttar Pradesh's Noida Sector 76 on Sunday afternoon. After nearly two hours, he was brought down by the police and fire department officials.

Power discoms have provided electricity connections to 6,791 of the 10,802 applicants living in Delhi's unauthorised colonies following Lieutenant Governor V K Saxena's intervention, the Raj Niwas said on Tuesday.

Born in a poor village, Algerian boxer Imane Khelif has overcome numerous obstacles throughout her life to win a controversial Paris Olympics gold on Friday.

Backed by Iran and hated by Israel, Hezbollah chief Hassan Nasrallah is Lebanon's most powerful man. He enjoys cult status among his Shiite supporters and holds sway over the country's institutions.

Founded in 1868, Tatas have become one of largest and most diverse global conglomerates. It is a name heard in almost every home in India and tens of millions overseas.

1. Inflation in nearly half of major states outgrows India's Oct CPI; price pressure steepest in Chhattisgarh  Moneycontrol
2. Retail inflation surges to a 14-month high of 6.2% in October  The Times of India
3. If we exclude vegetable prices, CPI inflation remains in RBI's range: UBI research  The Economic Times
4. Rising food prices are likely to push back beginning of rate cutting cycle  The Indian Express
5. India confident of reaching USD 100 billion trade volume with Russia ahead of 2030 timeline: S Jaishankar  Telegraph India

1. Has AIMIM’s Owaisi, the dark horse in Maharashtra elections, played a winning move?  Hindustan Times
2. Video | Maharashtra Election Will Throw Up Fractured Mandate: A Owaisi's Party Leader  NDTV
3. Owaisi backs Maratha reservation ahead of Maharashtra Assembly polls  India Today
4. Need to fight unitedly by Muslims, Maratha and Dalits: Barrister Owaisi.  Etemaad
5. No one can say Uddhav Thackrey won't go back to BJP: AIMIM  The Times of India

The upcoming Moto G Power 5G (2025) recently made a pit stop at the FCC where the charging speed and battery size of the phone was revealed.

The post The Moto G Power 5G (2025) was spotted at the FCC appeared first on Phandroid.

Google has seemingly launched the Quick Share app for Windows on ARM PCs, something that was not previously available.

The post Google Quick Share now available for Windows on ARM appeared first on Phandroid.

If you hate having your SIM locked to your carrier, then we’ll show you how to SIM unlock your iPhone 16 Pro for free!

The post How to SIM unlock the iPhone 16 Pro for FREE! appeared first on Phandroid.

Kapil Sharma wasted no time in diving into their personal stories, focusing on how Deepinder met his Mexican wife.

Zomato witnesses approximately 400,000 cancelled orders monthly which prompted it to launch the initiative.

Owlet, a connected-baby care company raised a $24 million Series B investment from Trilogy Equity Partners, with participation from existing investors, including Eclipse Ventures, Broadway Angels, and Enfield Ventures, and the addition Pelion Venture Partners.

Owlet’s core product is a baby sock that contains a smart sensor. The sensor monitors pulse oximetry, a technology used in hospitals to measure an infant's heart rate and blood oxygen levels. The vital signs are communicated to parents’ smartphone via Bluetooth connection. The product retails for $299 and parents can also choose from monthly payment plans.

Other IoT-health startups using sensors to monitor vital signs include Aifloo, a company selling wrist-bands for elders and Air by Propeller, a smart health company that provides an API to predict local asthma conditions.

A complete product package of Owlet monitor includes three fabric socks, smart sock sensor, a base station (which rings an alarm if a baby’s vital signs are abnormal), and charging cords.

Before the company raised the latest round, it closed a $15 million Series B round in late 2016. The recent investment brought Owlet’s total equity funding to $46M. Owlet plans to use the growth capital to launch more baby care products.

[SAPS] - Polokwane based Hawks Serious Commercial Crime Investigation in collaboration with National Traffic Anti-corruption Unit arrested 11 suspects between the ages of 27 and 57 for alleged fraud at various Provinces during operation "SISFIKILE".

[SAPS] - Gqeberha Flying Squad members clamped down on criminals involved in illegal abalone activities and robbery suspects in two unrelated incidents.

[allAfrica] We are excited to share the momentous news that Cape Town Pride has officially won the bid to host WorldPride 2028. This significant event is a global celebration of LGBTQ+ pride and rights, marking a pivotal milestone not only for the LGBTQ+ community in the city but also for the entire African continent. This victory positions Cape Town as a leading symbol of inclusivity and diversity, showcasing its commitment to advancing a welcoming environment for all.

[Daily Maverick] Water and Sanitation Minister Pemmy Majodina held an urgent meeting on Sunday with Gauteng Premier Panyaza Lesufi and Johannesburg Mayor Dada Morero to address severe water shortages affecting Johannesburg communities.

[allAfrica]

[DA] It is a national embarrassment that the inability of the City of Johannesburg to supply water to its residents, business and public sector offices, has now led to the shutdown of operations at the Constitutional Court, on Constitution Hill in Braamfontein.

The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence.  However, designing and signing off chiplets and packages individually is time-...(read more)

PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low-latency, non-retimed, linear optics connector. We achieved and maintained a consistent, impressive pre-FEC BER of ~3E-8 (PCIe spec requires 1E-6) for the entire duration of the event, spanning over two full days with no breaks. This provides an ample margin for RS FEC. As seen in the picture below, the receiver Eye PAM4 histograms have good linearity and margin. This is the world’s first stable demonstration of 128 GT/s TX and RX over off-the-shelf optical connectors—by far the main attraction of DevCon this year.

Cadence 128 GT/s TX and RX capability over optics

Block diagram of Cadence PHY for PCIe 7.0 128 GT/s demo setup with linear pluggable optics

As a leader in PCIe, our PCIe controller architect Anish Mathew shared his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Anish Mathew presenting “Impact of UIO ECN on PCIe Controller Design and Performance”

In summary, Cadence had a dominating presence on the demo floor with a record number of PCIe demos:

• PCIe 7.0 over optics
• PCIe 7.0 electrical
• PCIe 6.0 RP/EP interop back-to back
• PCIe 6.0 protocol in FLIT mode with Lecroy Exerciser (at Cadence booth)
• PCIe 6.0 protocol in FLIT mode (at the Lecroy booth)
• PCIe 6.0 JTOL with Anritsu and Tektronix equipment (at Tektronix booth)
• PCIe 6.0 protocol with Viavi Protocol Analyzer (at Viavi booth)
• PCIe 6.0 System Level Interop Demo with Gen5 platform (at SerialTek booth)

The Cadence team and its partners did a great job in coordinating and setting up the demos that worked flawlessly. This was the culmination of many weeks of hard work and dedication. Four different vendors featured our IP for PCIe 6.0. They attracted a lot of attention and drove traffic back to us.

Highlights of Cadence demos for PCIe 7.0 and 6.0

Cadence team at the PCI-SIG Developers Conference 2024

Thanks to everyone who attended the 32nd PCI-SIG DevCon. We really appreciate your interest in Cadence IP, and a big thanks to our partners and customers for all the positive feedback and for creating so much buzz for the Cadence brand.

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

The automotive industry is currently on the cusp of a radical evolution, steering towards a future where cars are not just vehicles but sophisticated, software-defined vehicles (SDV). This shift is marked by an increased reliance on automation and a significant increase in the use of sensors to improve safety and reliability. However, the increasing number of sensors has led to higher compute demands and poses challenges in managing a wide variety of data. The traditional method of using separate processors to manage each sensor's data is becoming obsolete. The current trends necessitate a unified processing system that can deal with multimodal sensor data, utilizing traditional Digital Signal Processing (DSP) and AI-driven algorithms. This approach allows for more efficient and reliable sensor fusion, significantly enhancing vehicle perception. Developers often face difficulties adhering to stringent power, performance, area, and cost (PPAC) and timing constraints while designing automotive SoCs.

Cadence, with its groundbreaking products and AI-powered processors, is enabling designers and automotive manufacturers to meet the future sensor fusion demands within the automotive sector. At the recent CadenceLive Silicon Valley 2024, Amol Borkar, product marketing director at Cadence, showcased the company's dedication and forward-thinking solutions in a captivating presentation titled "Addressing Tomorrow’s Sensor Fusion Needs in Automotive Computing with Cadence." This blog aims to encapsulate the pivotal takeaways from the presentation. If you missed the chance to watch this presentation live, please click here to watch it.

Significant Trends in the Automotive Market – Industry Landscape

We are witnessing a revolution in automotive technology. Innovations like occupant and driver monitoring systems (OMS, DMS), 4D radar imaging, LiDAR technology, and 360-degree view are pushing the boundaries of what's possible, leading us into an era of remarkable autonomy levels—ranging from no feet or hands required to eventually no eyes needed on the road.

Sensor Fusion and Increasing Processing Demands—Sensor fusion effectively integrates data from different sensors to help vehicles understand their surroundings better. Its main benefit is in overcoming the limitations of individual sensors. For example, cameras provide detailed visual information but struggle in low-light or lousy weather. On the other hand, radar is excellent at detecting objects in these conditions but lacks the detail that cameras provide. By combining the data from multiple sensors, automotive computing can take advantage of their strengths while compensating for their weaknesses, resulting in a more reliable and robust system overall.

One thing to note is that the increased number of sensors produces various data types, leading to more pre-processing.

On-Device Processing—As the industry moves towards autonomy, there is an increasing need for on-device data processing instead of cloud computing to enable vehicles to make informed decisions. Embracing on-device processing is a significant advancement for facilitating real-time decisions and avoiding round-trip latency.

AI Adoption—AI has become integral to automotive applications, driving safety, efficiency, and user experience advancements. AI models offer superior performance and adaptability, making future-proofing a crucial consideration for automotive manufacturers. AI significantly enhances sensor fusion algorithms, offering scalability and adaptability beyond traditional rule-based approaches. Neural networks enable various fusion techniques, such as early fusion, late fusion, and mid-fusion, to optimize the integration and processing of sensor data.

Future Sensor Fusion Needs

Automotive architectures are continually evolving. With current trends and AI integration into radar and sensor fusion applications, SoCs should be modular, flexible, and programmable to meet market demands.

Heterogeneous Architecture- Today's vehicles are loaded with various sensors, each with a unique processing requirement. Running the application on the most suitable processor is essential to achieve the best PPA. To meet such requirements, modern automotive solutions require a heterogeneous compute approach, integrating domain-specific digital signal processors (DSPs), neural processing units (NPUs), central processing unit (CPU) clusters, graphics processing unit (GPU) clusters, and hardware accelerator blocks. A balanced heterogeneous architecture gives the best PPA solution.

Flexibility and Programmability- The industry has come a long way from using computer vision algorithms such as HOG (Histogram Oriented Gradient) to detect people and objects, HAR classifier to detect faces, etc., to CNN and LSTM-based AI to Transformer models and graphical neural networks (GNN). AI has evolved tremendously over the last ten years and continues to evolve. To keep up with the evolving rate of AI, SoC design must be flexible and programmable for updates if needed in the future.

Addressing the Sensor Fusion Needs with Cadence

Cadence offers a complete suite of hardware and software products to address the increasing compute requirements in automotive. The comprehensive portfolio of Tensilica products built on the robust 32-bit RISC architecture caters to various automotive CPU and AI needs. What makes them particularly appealing is their scalability, flexibility, and configurability, offering many options to meet diverse needs.

The Xtensa family of products offers high-quality, power-efficient CPUs. Tensilica family also includes AI processors like Neo NPUs for the best power, performance, and area (PPA) for AI inference on devices or more extensive applications. Cadence also offers domain-specific products for DSPs such as HIFI DSPs, specialized DSPs and accelerators for radar and vision-based processing, and a general-purpose family of products for floating point applications.

The ConnX family offers a wide range of DSPs, from compact and low-power to high-performance, optimized for radar, lidar, and communications applications in ADAS, autonomous driving, V2X, 5G/LTE/4G, wireless communications, drones, and robotics. Tensilica's ISO26262 certification ensures compliance with automotive safety standards, making it a trusted partner for advanced automotive solutions. The Cadence NeuroWeave Software Development Kit (SDK) provides customers with a uniform, scalable, and configurable ML interface and tooling that significantly improves time to market and better prepares them for a continuously evolving AI market. Cadence Tensilica offers an entire ecosystem of software frameworks and compilers for all programming styles.

Tensilica's comprehensive software stack supports programming for DSPs, NPUs, and accelerators using C++, OpenCL, Halide, and various neural network approaches. Middleware libraries facilitate applications such as SLAM, radar processing, and Eigen libraries, providing robust support for automotive software development.

Conclusion

Cadence’s Tensilica products offer a development toolchain and various IPs tailored for the automotive industry, covering audio, vision, radar, unified DSPs, and NPUs. With ISO certification and a robust partner ecosystem, Tensilica solutions are designed to meet the future needs of automotive computing, ensuring safety, efficiency, and innovation.

Learn More

• Cadence Automotive Solutions
• Cadence Automotive IP
• Sensor Fusion and ADAS in TSMC Automotive Processes
• Revolution on the Road: How Cadence is Driving the Future of Automotive Design!
• Taming Design Complexity in Chiplet-Based Automotive Electronics
• UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

The demand for higher-performance computing is greater than ever. Cutting-edge applications in artificial intelligence (AI), big data analytics, and databases require high-speed memory systems to handle the ever-increasing volumes and complexities of data. Advancements in cloud computing and machine virtualization are stretching the limits of current capabilities. AI applications hosted in the cloud rely on fast access and reduced latency in memory systems, which is amplified by an increasing number of CPU and GPU cores.

Introducing the DDR5 Multiplexed Rank DIMM (MRDIMM), the next-generation memory module technology designed to meet the needs of high-performance computing (HPC) and AI in cloud applications. By leveraging existing DDR5 DRAM memory devices, MRDIMM modules not only double the DRAM data rate but also maintain the RAS capabilities of the industry-proven RDIMM modules, setting a new precedent for memory module performance.

Let’s compare RDIMM and MRDIMM modules using the same DRAM parts. Today, high-speed production DDR5 RDIMM modules run at 5600Mbps. Those modules use DDR5 DRAM parts, which also run at 5600Mbps. An MRDIMM module using the same DDR5 5600Mbps DRAM parts will run at a blazing 11.2Gbps.

One key metric for best-in-class performance, low bit error rate (BER), and ease of adoption is the eye diagram. The eye diagram illustrates at-speed system margin and accurately represents DDR system quality when captured with a pseudo-random binary sequence (PRBS)-like pattern. The diagram below illustrates Cadence’s 3nm silicon write eye diagram for DDR5 MRDIMM IP running at 12.8Gbps.

Cadence 3nm DDR5 MRDIMM 12.8Gbps test chip write eye diagram, design kit is available today

The eye diagram is captured using a PRBS-like pattern, incorporating a package and system board representative of a typical MRDIMM channel. Using PRBS-like patterns is crucial for capturing accurate eye diagrams. Repetitive clock-like data patterns create deceptively “open eyes” that do not reflect the real system performance. Effects like intersymbol interference, simultaneous switching, reflections, and crosstalk are not accurately reflected in the eye diagrams for parallel interfaces like DDR using non-random data streams. Relying on improperly captured eye diagrams inevitably leads to a significantly worse real system BER than conveyed by that eye diagram.

Doubling the DDR5 RDIMM data rate is challenging. Achieving high performance while optimizing for area and power requires multiple design techniques. Feed-forward equalization (FFE), decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and T-coils are required to reach 12.8Gbps MRDIMM data rates in multi-channel systems. Building a production-worthy 12.8Gbps DDR5 MRDIMM IP requires engineering expertise that comes from many generations of memory interface design and production experience. Cadence has developed this expertise through multiple DDR5/4, LPDDR5X/5, and GDDR6 designs in different technology nodes and foundries. For instance, Cadence’s GDDR6 IP is available in three foundries and ten process nodes, with mass production at speeds exceeding 22Gbps.

For your next project, consider DDR5 12.8Gbps MRDIMM, a technology that not only doubles the bandwidth of DDR5 RDIMM but also promises rapid proliferation into next-generation AI, data center, HPC, and enterprise applications. With its cutting-edge capabilities, the Cadence DDR5 12.8Gbps MRDIMM IP is ready to power the future of computing.

As vehicles transition into interconnected ecosystems, artificial intelligence and advanced technologies become increasingly crucial. Infotainment systems have evolved beyond mere music players to become central hubs for connectivity, entertainment, and navigation. With global demand for comfort, convenience, and safety rising, the automotive infotainment market is experiencing significant growth. Valued at USD14.99 billion in 2023, it is projected to grow at a compound annual growth rate (CAGR) of 9.9% from 2024 to 2030.

To keep pace with this evolution, infotainment systems must accommodate a range of workloads, including audio, voice, AI, and vision technologies. This requires a flexible, scalable Digital Signal Processor (DSP) solution that acts as an offload engine for the main application processor. Integrating a single DSP for varied functions offers a cost-effective solution for high-performance, low-power processing, which aligns well with the needs of Electric Vehicles (EVs).

If you missed the detailed presentation by Casey Ng, Product Marketing Director at Cadence at CadenceLIVE 2024, register at the CadenceLIVE On-Demand site to access it and other insightful presentations. Stay ahead of the curve and explore the future of innovative electronics with us.

Cadence Infotainment Solution: Leading the Charge

Cadence Tensilica HiFi DSPs play a crucial role in enhancing audio capabilities in vehicle infotainment systems. They support applications like voice recognition, hands-free calling, and deliver immersive audio experiences. This technology is also paramount for features such as active noise control, which reduces road and cabin noise, and acoustic event detection for identifying unusual sounds like broken glass. One notable innovation is the "audio bubble," enabling personalized audio zones within the vehicle, ensuring passengers enjoy distinct audio settings.

Cadence HiFi DSP technology enriches the driving experience for electric vehicles by mimicking traditional engine sounds, while its advanced audio processing ensures optimal performance across various digital radio standards. It significantly contributes to noise reduction, hence improving the cabin experience. Integrating a Double Precision Floating Point Unit (FPU) stands out, as it upgrades audio performance and Signal-to-Noise Ratio (SNR) through efficient 64-bit processing, allowing control over numerous speakers without hitches.

These advancements distinguish the DSP as an essential tool in evolving infotainment systems, offering unmatched performance and adaptability. Tensilica HiFi processors, crucial to advanced infotainment SoCs, serve as efficient offload processors, augmenting real-time execution and energy efficiency. Cadence’s ecosystem, with over 200 codecs and software partnerships, propels the evolution of innovative infotainment systems. Introducing the HiFi 5s DSP marks a new era in connected car experiences, setting the stage for groundbreaking advancements.

Exploring Tomorrow with HiFi 5s DSP Technology

The HiFi 5s represents the apex of audio and AI digital signal processing performance. Built on the Xtensa LX8 platform, it introduces capabilities like auto-vectorization, which allows standard C code to be automatically optimized for performance. This synergy of hardware and software co-design marks a significant step forward in DSP technology. By leveraging its extended Single Instruction, Multiple Data (SIMD) capabilities alongside features like a double-precision floating-point unit (DP_FPU), the HiFi 5s delivers unparalleled precision and speed improvements in signal and audio processing tasks. Equally notable are its branch prediction and L2 cache enhancements, which optimize system performance by refining the control code execution and recognizing codec efficiency. The application of such enhancements are particularly beneficial in real-world scenarios.

AI-Powered Audio

Cadence's focus on AI integration with the HiFi 5s demonstrates significant improvements in audio clarity through AI-powered solutions.

• AI models learn from real-world data and adapt dynamically, while classic DSP algorithms rely on fixed rules.
• AI can be fine-tuned for specific scenarios, whereas classic DSP lacks flexibility.
• AI handles extreme and marginal noise patterns better, generalizes well across different environments, and is robust against varying noise characteristics.

Cadence's dedication to artificial intelligence marks a pivotal shift in audio processing. Traditional DSP algorithms, bound by rigid rules, are eclipsed by AI's ability to learn dynamically from real-world data. This adaptability equips AI models to tackle challenging noise patterns and offer unmatched clarity even in noisy environments, making them ideal for automotive and consumer audio applications.

Realtime AI-Optimized Speech Enhancements by OmniSpeech and ai|coustics

OmniSpeech

Our partner, OmniSpeech, has advanced AI-based audio processing that enhances the performance of audio software, specifically for omnidirectional and dipole microphones. Impressively, their technology operates with less than 32MHz and requires only 418kB of memory.

Test results show that background noise is significantly reduced when AI employs a single omnidirectional microphone, outperforming non-AI solutions. Additionally, when using a dipole microphone with AI, there is a 3.5X improvement in the weighted Signal-to-Noise Ratio (SNR) and more than a 28% increase in the Global Mean Opinion Score (GMOS) across various background noise.

ai|coustics

ai|coustics, a Cadence partner specializing in advanced audio technologies, utilizes real-time AI-optimized speech enhancement algorithms. They leverage an extensive speech-quality dataset containing thousands of hours and 100 languages to transform low-quality audio into studio-grade audio. Their process includes:

• De-reverb, which eliminates room resonances, echoes, and reflections

• Removing artifacts from downsampling and codec compression

• Dynamic and adaptive background noise removal

• Reviving audio materials with analog and digital distortions

• Providing support for all languages, accents, and a variety of speakers

Applications include:

• Automotive: Enhances clarity of navigation commands and communication for driver safety

• Consumer audio: Improves voice clarity for better dialogue understanding in TV programs. Optimizes speech intelligibility in communication for both uplink and downlink audio streams

• Smart IoT: Boosts voice command detection and response quality

Performance Enhancements

The advancements in branch prediction and L2 cache integration have significantly boosted performance metrics across various systems. With HiFi 5s, branch prediction increases codec efficiency by an average of 5%, reaching up to 16% in optimal conditions. L2 cache improvements have drastically enhanced system-level performance, evidenced by a 2.3X boost in EVS decoder efficiency. Adding MACs and imaging ISA in imaging use cases has led to substantial advancements. When comparing HiFi 5s to HiFi 5, imaging ISA performance improvements range with >60% average performance improvements.

The Crescendo of the Future

As Cadence continues to blaze trails in DSP technology, the HiFi 5s emerges as the quintessential solution for consumer and automotive audio use cases. With a robust framework for auto-vectorization, an unmatched double-precision FPU, AI-driven audio solutions, and comprehensive system enhancements, Cadence is orchestrating the next era of audio processing, where every note is clearer, every sound richer, and every experience more engaging. It is not just the future of audio—it's the future of how we experience the world around us.

 Discover how Cadence Automotive Solutions can transform your business today!

LEF allows the same port with multiple shape definitions. Does anybody know if innovus can create multiple duplicate shapes associated with the same port? Assume they are connected outside the block with perfect timing synchronization. Thank you!

I am working with innovus on a huge design. I found some cells are placed far away from both timing start points and timing end points. I suspect some other timing paths may be near-critical that results in this sub-optimal cell placement; or innovus has to place the cell far away due to congestion of placement or routing.

Is there a way to see why innovus places/moves the cell during place_opt_design or ccopt_design?

Also, is there a way to highlight all timing start points or timing end points that go through a cell? There may be thousands of timing paths through this cell. I tried using report_timing and timing debugger but it is very painful to click the highlight box and highlight the timing paths one by one.

Thank you for your help!

Hi there, 

we've encountered some strange behavior when trying to run the "check_litho" command from within INNOVUS 22.14. We set the required files and configuration files according to our PDK documentation. The command, without the absolute file paths, is:

check_litho -sign_off -cpu 96 -run_mode fg -create_guides -map_file <map file path> -config <config file path> -techfile <tech file path> -dir <output dir path> -write_stream_options "-mode ALL -merge <list of gds files>" -apply squishHints

We are currently using PEGASUSDFM 23.20 for this command but tested previous PEGASUSDFM and MVS versions as-well. After we issued the previous command, we see INNOVUS launching the PEGASUSDFM/MVS and trying to run the command. After some time, the command crashes with the error "mdb_load_with_extra: failed to pre-open extra input file './preproc/INTERMEDIATE.oas' for read". We have tested a similar setup with INNOVUS 19.10 where we did not have this issues. Did something change with the new INNOVUS version? Does anyone have an idea what we are missing? 

Thanks in advance.

Best regards,

PS

Hi all,

I have been following the tutorial "Innovus Block Implementation with Stylus Common UI", version 23.1.

While I was doing the clock tree synthesis, the tutorial calls for a command

clock_opt_design

But my tool tells me this is a beta feature which needs to be enabled.

Warning: clock_opt_design requires beta feature innovusClockOptFlow enabled.

Can I ask how do I enable this beta feature?

My version of Innovus is v21.35-s114_1, is it because of the version incompatibility?

Many thanks

for debug I use suspend in my tcl script to debug，here is the code

after that the innovus command screen become 

how to quit the SUSPEND status？ thanks

Hi everyone. 

I'm very a new cadence user. I'm not good at using it and quite lost in finding a way to get the results. With the topic, I would like to ask you for some suggestions to improve my cadence skills.

I have some digital decision logic. Some are combinational logic, some are sequential logic that I would like to import or generate random input combination to the inputs of my decision logic to get the maximum, minimum, and average delay power dissipation and area when feeding the different input combination.

My logic has 8-bit, 16-bit, and 32-bit input. The imported data tends to be decimal numbers.

I would like to ask you:

- which tool(s) are the most appropriate to import and feed the different combination to my decision logic?

- which tool is the most appropriate to synthesis with different number of input? - I have used Genus Synthesis Solution so far. However with my skill right now I can only let Genus synthesize my Verilog code one setup at a time. I'm not sure if I there is anyway I can feed a lot of input at a time and get those results (min, max, average of delay, power dissipation and area)

- which language or scripts I should pick up to use and achieve these results?

-where can I find information to solve my problem? which information shall I look for?

Thank you so much for your time!!

Best Regards

I have a 2-dimensional input in my design - input [2:0] data_in [15:0]. After synthesis with genus, I got a netlist where the inputs are like data[15], data[14],...,data[0]. And furthermore it has definitions like input [2:0] data[15], .... So how can I define the pin locations of each of the bits for this input? Can I define data[15]'s inner bits like data[15][0]? Is it possible to define this with def files?

Hi! I've made some 1-point waveform "markers" that I want to overlay in my plots to aid visualization (with the added advantage, w.r.t. normal Viva markers, that they update location automatically upon refreshing simulation data).

For example, the plot below shows an spectrum along with two of these markers, which I create with the function "singlePointWave", and the Assembler output definitions also as shown below.

The problem is: as currently created and defined, Assembler is unable to plot these elements. I can send their expressions to the calculator and plotting works from there, BUT ONLY after first enabling the "Allow Any Units" in the target Viva subwindow.

Thus, I suspect Assembler is failing to plot my markers because they "lack" other information like axes units and so on. How could I add whatever is missing, so that these markers can plot automatically from Assembler?

Thanks in advance for any help!

Jorge.

P.S. I also don't know why, but nothing works without those "ymax()" in the output definitions--I suspect they are somehow converting the arguments to the right data type expected by singlePointWave(). Ideas how to fix that are also welcome! ^^

procedure( singlePointWave(xVal yVal)
    let( (xVect yVect wave)
        xVect = drCreateVec('double list(xVal));
        yVect = drCreateVec('double list(yVal));
        wave = drCreateWaveform(xVect yVect);
    );
);

I want to create sub tree of sub trees how can i do that?

I want to create another tree for the Sub parameter also.

I am attempting to use dbGetNeighbor() function inside the dynamic display HUD so that the distance to the next metal on that layer could be viewed. Think of another line in this dynamic table here... 

My SKILL code is essentially the following:

procedure(getNearestNeighborOnMetal(cv)
let((direction tmpBoundingBox)
direction = internal_function()
tmpBoundingBox = dbCreateRect(geGetEditCellView() "tmp" list(hiGetCommandPoint() hiGetCommandPoint()))
car(dbGetNeighbor(geGetEditCellView() tmpBoundingBox direction))
)
)

this returns the distance to the closest metal based on some tests.

Next, I try to register this function to work in the Dynamic Display / Info Balloon world by executing odcRegisterCustomFunc() for each and every object type (I know, absurd, but trying to debug)

In the dynamic display menu, I toggle the "Custom SKILL Function" check in layoutXL, then hit apply, then OK.

After this I find I am unable to view the changes reflected in any info balloons or in the drawing HUD (above) for this wire. I have tried replacing my function with the sample "customFunc" from the odcRegisterCustomFunc() documentation and was still unable to produce any new output.

Any help diagnosing the use of this feature would be very much appreciated