A pallet system includes a pallet upon which cargo or other payloads may be carried. The pallet has a plurality of tie-down locations at which the pallet may be tied-down on a base, and at least one tie-down device for tying down the pallet on the base at any of the tie-down locations. The pallet further includes structure for mounting the tie-down device on the pallet at any of the tie-down locations.

Some embodiments of the invention relate to function elements for fixing in seat rails of aircraft. The function element according to the invention may include: a fixing rail with a web running in the x direction and a multiplicity of extensions which protrude beyond the web in a y direction to form a T profile, wherein the fixing rail is formed corresponding to the seat rail such that the fixing rail can be inserted in the seat rail and moved along the x direction into a holding position in which the extensions sit between the holes below the slots, at least one fixing peg which is arranged mobile on the fixing rail and can be brought into a blocking position in which the fixing peg engages in a hole of the seat rail so that the function element is fixed in the x direction.

An improved captive beam decking system is disclosed for use in a cargo trailer. The system includes a beam assembly and a foot assembly that is selectively engagable to a vertical sliding track system. The sliding track system is attached to the sidewall of a trailer vertically. The beam can be easily moved at different heights that are selected based upon the configuration of the cargo trailer.

Stake pocket formations are secured to a cargo bed frame of a land vehicle such as trailers and flatbed trucks for removably supporting sidewall supporting members. The formations include sidewalls secured to and projecting from the frame and an end wall extending between the sidewalls. An opening extends through the end wall and is adapted to receive the terminal end of a J-hook therethrough. The J-hook is secured to the formation by inserting the terminal end thereof into the pocket placing an upper edge of the end wall into the J-hook gap and rolling/rotating the J-hook thereby inserting the terminal end into the opening. The J-hook cannot be removed from the pocket unless it is rolled/rotated in the opposite direction. While within the stake pocket and without strap tension, the J-hook abuts the trailer frame and formation end wall and is, thereby, maintained within the pocket.

A side rail of a floor assembly of a trailer, such as a flatbed trailer, including a channel formed in a top wall of the side rail and an aperture formed in the top wall of the side rail at a location spaced-apart from the channel. The channel extends along a length of the side rail and is configured to receive a first cargo restraint device therein. The aperture is configured to receive a second cargo restraint device therein.

A fixture for attachment of an end of a member, such as a wind turbine tower section, blade or hub for a wind turbine characteristically has an end flange. To enable clamping while being able to compensate for different hole patterns in the flanges, by the invention, the fixture provides for retaining of ends of members with flanges, regardless of flange diameter and hole patterns, and which is also quickly and easily installed. Additionally, it is possible to firmly clamp the flange end to upstanding frame parts of the fixture with fastening elements, thereby providing a stable connection between a console of the fixture and the upstanding frame parts.

Method and apparatus for handling aerogenerator blades that provide a versatile means for handling aerogenerator blades without an unbalanced distribution of the loads in the blade. The method comprises positioning an upper mounting part (103) over the blade after the upper mold has been retracted; lifting the blade with the upper mounting part from the under mold using a lifting means; positioning the blade over an under mounting part (104) which is fixedly attached to an inferior movable support (102); attaching the upper mounting part to the under mounting part, wherein the upper and under mounting parts together have the inner surface substantially corresponding to the shape of the blade outer profile section. The invention further comprises an apparatus for handling aerogenerator blades.

A transport system for a wind turbine blade is provided. The transport system is configured for increasing a curvature of the wind turbine blade in response to an obstacle during transport of the wind turbine blade. Further, a method for transporting a wind turbine blade in order to avoid obstacles is provided.

An automatic lock affixed to a cargo container for interconnecting two stacked containers, and for automatically locking and unlocking without reliance upon the overcoming of a friction force to release the device.

A box stop device includes a base member and a raised member attached to the base member. The base member has a top surface and a bottom surface. The top surface may be flat. The bottom surface may be adapted to attach to a desired surface. The raised member may be attached to the base member and may extend approximately vertically from the top surface. The raised member may include a first side and a second side. The first side and the second side may be attached together at an angle of approximately 90 degrees.

A protective cap for a trailing edge of a rotor blade of a wind turbine for use during transportation, handling, or maintenance of the rotor blade is disclosed. The protective cap includes a body having a first leg, a second leg, and a cap member. The cap member connects the first and second legs. Further, the cap member may be configured to cover at least a portion of a trailing edge of the rotor blade and may be configured to provide a gap between an inner surface of the protective cap and the trailing edge. In addition, the first and second legs may resiliently engage the rotor blade.

An apparatus and method for providing a removable anchor for use in tying down a load, or for securing a winch cable for use in recovering a disabled vehicle or other load. The anchor may be removably attached to the deck/bed of a trailer or vehicle (e.g., a car carrier or wrecker/tow truck), using one or more slots or stake pockets located on a cargo surface of the deck. The removable anchor may include: a projection member shaped and sized to fit into a slot on the cargo surface, or to protrude through a stake pocket; a crown attached to, or integrally forming a part of, the projection member, and configured to receive and anchor one or more tie down connectors; and a key attached to, or integrally forming a part of, the projection member. The key can be passed into the slot and manipulated between removable and locked positions. Alternatively, the key may be used to removably secure the anchor to the stake pocket.

A module in the form of a pallet or a closed container includes a grouping together of the electrical devices in an avionics bay, in which the electrical devices are interconnected and attached so as to facilitate the mounting and thus limit the time it takes to mount the electrical devices in the avionics bay.

A fastening system includes an energy absorbing or impact indicator and at least one or more of the following: (1) a fastening base for mounting in an emergency vehicle, (2) a patient support engageable with a base, (3) a patient securement mechanism for securing a patient on a patient support, (4) a patient securement mechanism for securing a patient to a vehicle, (5) a patient support securement mechanism operable to secure a patient support in an emergency vehicle, or (6) a patient support securement mechanism operable to secure a patient support to a base, wherein the energy absorbing or impact indicator is located (1) at the patient securement mechanism, or (2) at the patient support securement mechanism, or wherein the energy absorbing or impact indicator is between (1) the base and the vehicle, (2) the patient support and the base, (3) the patient securement mechanism and the patient support, (4) the patient support and the emergency vehicle, (5) the patient and the emergency vehicle, or (6) the patient securement mechanism and the emergency vehicle, wherein the energy absorbing device or impact indicator has at least an energy absorbing state and a rigid state or indicates a level of impact at or between any of the respective component or components.

A cargo rack for transferring loads between a marine vessel and an offshore marine platform provides a frame having a front, a rear, and upper and lower end portions. The lower end of the frame has a perimeter beam base, a raised floor and a pair of open-ended parallel fork tine tubes that communicate with the perimeter beam at the front and rear of the frame. The frame includes a plurality of fixed side walls extending upwardly from the perimeter beam. A plurality of gates are movably mounted on the frame, each gate being movable between open and closed positions, the gates enabling a forklift to place loads on the floor. The frame has vertically extending positioning beams that segment the floor into a plurality of load-holding positions. Each load holding position has positioning beams that laterally hold a load module in position on the floor.

A seat fixing device for fixing an air passenger seat to a floor of an aircraft includes at least one fastening rail (10) in the form or a hollow profile, which is provided with a longitudinal channel (14) delimiting the free flanks (16) of the profile on the top part thereof (12) oriented to the seat. The channel includes through openings (18) located in a predetermined modular dimension, which enlarge the free input section and are used for inserting at least one snap-locking part (24) of a locking body (26). The looking body (26) is movable to a clamping position with the profile (16) of the hollow profile (14) by the relative displacement of each snap-locking part (24) in a perpendicular direction with respect to the longitudinal axis (28) of the fastening rail (10). The fixing device provides an eccentric drive (30) of the locking body (26) for carrying out relative displacement, which reduces assembly costs.

An apparatus for selectively securing a boat to a trailer may include a hull contact structure for abutting against the boat hull, and a releasable gripping structure positioned adjacent the hull contact structure to engage the boat's securing loop and selectively lock onto the loop to hold the boat to the trailer.

An apparatus and method for applying an underlayment layer to trucking cargo are provided. The underlayment layer may be formed into a roll with a rod disposed therethrough. The roll may be supported by a frame. The roll can be configured to move vertically with respect to the ground. A trailer carrying trucking cargo can be stationed beneath the frame. The underlayment layer may unwound and dispensed from the roll. In order to drape the trucking cargo with the underlayment layer, the roll may be moved horizontally over the frame in addition to or alternatively to having the trucking cargo driven horizontally with respect to the roll.

An edge protector for insertion between a load to be lifted and a lifting member which facilitates the lifting of the load, preventing damage to either the load or the lifting member. The edge protector has a pair of flanges which extend from a radiused or curved center portion. Each flange has an inner surface and an outer surface. A portion of each respective outer surface of each flange is spaced from and is essentially parallel to the inner surface of the respective flange.

A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.

An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled.

Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different.

An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.

Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior.

Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.

There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters.

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

An intelligent current drive is disclosed that couples an active current source to a bus line to increase the rate of pull-up and decouples the active current source from the bus line prior to reaching the desired pull-up voltage.

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.

A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

The present invention relates to a method for downloading a binary configuration file in a programmable circuit implemented in a device. The device comprises at least one central processing unit, a plurality of connectors, and a programmable circuit enabling all or a part of the signals received by said connectors to be processed and transmitted to at least one other circuit of the device. The device analyzes the signals present on the connectors in order to define what other devices are connected and whether the connections are operational. Then, a configuration file is selected from among a set of configuration files according to the operational connections and is downloaded from a memory of the device into the programmable circuit. The invention also relates to a device having a component programmed according to the method previously described.

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.

Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus.