Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)

Hi, I want to add values to components in my SiP design such as 1nF or 15nH. There is already in existence a COMP_VALUE property reserved for this as shown during BOM generation. This property is not visible under the Edit/Properties dialog for component or symbol find filters. We have already created user properties called COMP_MFG and COMP_MFG_PN that it editable at a component level. When we try to add COMP_VALUE it is reported as a reserved name in Cadence but this name is not listed in the properties dialog. Is there a way to turn on the visibility and editablility of this or other hidden reserved Cadence property names? How can I assign a string value to the COMP_VALUE property?

Thanks

I have created a die and other components as symbols in sip and placed the symbols in sip through logic import capture netlist. It shows net connectivity but i couldn't add bond finger from the die pins. Please help on this. 

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain...

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Today, we are living in the era where whatever we think of as an idea is not far from being implemented…thanks to machine learning (ML) and artificial intelligence (AI) entering into the...

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You can't read anything about technology these days without reading about 5G. But before there was 5G, there was 4G. And before that 3G, 2G, and 1G. A 0G even. For the next few Thursdays,...

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Recently, I read an article about how failure is the stepping stone to success in life. It instantly struck a chord and a thought came zinging from nowhere about what happens to the failed arcs of a...

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The Linley Processor Conference always opens with a keynote by Linley Gwenapp giving an overview of processors in whatever is the hottest area. Most of the other presentations during the conference...

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I recently attended a webinar presented by Wally Rhines about his new book, Predicting Semiconductor Business Trends After Moore's Law . Wally was the CEO of Mentor, as you probably know. Now he...

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Cadence has a new white paper out on Computational Software . I've written on these topics in Breakfast Bytes, most recently in the posts: Computational Software System Analysis: Computational...

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Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

In the former blog about Python and Specman: Specman: Python Is here!, we described the technical information around Specman-Python integration. Since Python provides so many easy to use existing libraries in various fields, it is very tempting to leverage these cool Python apps.

Coverage has always been the center of the verification methodology, however in the last few years it gets even more focus as people develop advanced utilities, usually using Machine Learning aids. Anyhow, any attempt to leverage your coverage usually starts with some analysis of the behavior and trends of some typical tests. Visualizing the data makes it easier to understand, analyze, and communicate. Fortunately, Python has many Visualization libraries.

In this blog, we show an example of how you can use the plotting Python library (matplotlib) to easily display coverage information during a run. In this blog, we use the Specman Coverage API to extract coverage data, and a Python module to display coverage grades interactively during a single run and the way to connect both.

Before we look at the example, if you have read the former blog about Specman and Python and were concerned about the fact that python3 is not supported, we are glad to update that in Specman 19.09, Python3 is now supported (in addition to Python2).

The Testcase
Let’s say I have a stable verification environment and I want to make it more efficient. For example: I want to check whether I can make the tests shorter while hardly harming the coverage. I am not sure exactly how to attack this task, so a good place to start is to visually analyze the behavior of the coverage on some typical test I chose. The first thing we need to do is to extract the coverage information of the interesting entities. This can be done using the old Coverage API. 

Coverage API
Coverage API is a simple interface to extract coverage information at a certain point. It is implemented through a predefined struct type named user_cover_struct. To use it, you need to do the following:

1. Define a child of user_cover_structusing like inheritance (my_cover_struct below).
2. Extend its relevant methods (in our example we extend only the end_group() method) and access the relevant members (you can read about the other available methods and members in cdnshelp).
3. Create an instance of the user_cover_structchild and call the predefined scan_cover() method whenever you want to query the data (even in every cycle). Calling this method will result in calling the methods you extended in step 2.  

 The code example below demonstrates these three steps. We chose to extend the end_group() method and we keep the group grade in some local variable. Note that we divide it by 100,000,000 to get a number between 0 to 1 since the grade in this API is an integer from 0 to 100,000,000. 

Pass the Data to a Python Module
After we have extracted the group grade, we need to pass the grade along with the cycle and the coverage group name (assuming there are a few) to a Python module. We will take a look at the Python module itself later. For now, we will first take a look at how to pass the information from the e code to Python. Note that in addition to passing the grade at certain points (addVal method), we need an initialization method (init_plot) with the number of cycles, so that the X axis can be drawn at the beginning, and end_plot() to mark interesting points on the plot at the end. But to begin with, let’s have empty methods on the Python side and make sure we can just call them from the e code.

 # plot_i.py
def init_plot(numCycles):
    print (numCycles)
def addVal(groupName,cycle,grade):
    print (groupName,cycle,grade)
def end_plot():
    print ("end_plot") 

And add the calls from e code:

 Before running this, note that you need to ensure that Specman finds the Python include and lib directories, and Python finds our Python module. To do this, you need to define a few environment variables: SPECMAN_PYTHON_INCLUDE_DIR, SPECMAN_PYTHON_LIB_DIR, and PYTHONPATH. 

 The Python Module to Draw the Plot
After we extracted the coverage information and ensured that we can pass it to a Python module, we need to display this data in the Python module. There are many code examples out there for drawing a graph with Python, especially with matplotlib. You can either accumulate the data and draw a graph at the end of the run or draw a graph interactively during the run itself- which is very useful especially for long runs.

Below is a code that draws the coverage grade of multiple groups interactively during the run and at the end of the run it prints circles around the maximum point and adds some text to it. I am new to Python so there might be better or simpler ways to do so, but it does the work. The cool thing is that there are so many examples to rely on that you can produce this kind of code very fast.

 In the example we used, we had two interesting entities: packet and state_machine, thus we had two equivalent coverage groups. When running our example connecting to the Python module, we get the following graph which is displayed interactively during the run.

When analyzing this specific example, we can see two things. First, packet gets to a high coverage quite fast and significant part of the run does not contribute to its coverage. On the other hand, something interesting happens relating to state_machine around cycle 700 which suddenly boosts its coverage. The next step would be to try to dump graphic information relating to other entities and see if something noticeable happens around cycle 700.

To run a complete example, you can download the files from: https://github.com/okirsh/Specman-Python/

Do you feel like analyzing the coverage behavior in your environment? We will be happy to hear about your outcomes and other usages of the Python interface.

Orit Kirshenberg
Specman team

Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online now!

1) Indago 19.09 Better Driver Tracing and More

Are you new to Indago and not sure where to start? Luckily, there’s a new Rapid Adoption Kit for you: the Indago 19.09 Overview RAK! This neat package contains everything you need to get your debugging started through Indago. In four short labs, plus a brief introductory lab, you’ll have all the basics of Indago 19.09 down—the Indago working environment, the SmartLog, how Indago interacts with the rest of the Cadence Verification Suite, and how Indago uses HDL driver tracing.

Lab 1 discusses the various debugging tools included in Indago and teaches you how to customize your Indago windows and environment settings. Lab 2 covers the SmartLog feature and talks about analyzing and filtering its messages to suit your needs, as well as how to interact with the waveform marker. Lab 3 is an interactive Indago debugging experience—it’ll walk you through how to use Indago and its features in an actual working environment: setting breakpoints, using simulator commands in the Indago console, toolbars, switches, and more. Lab 4 is all things HDL tracing—recording debug data, an introduction to debug assertions, waveform visualizations, driving expression analysis, and single-step driver tracing, among other things.

Interested? Check out the RAK here.

2) IXCOM MSIE: Faster Palladium Build Time

Got several testbenches you want to compile with the same DUT and tests and you want to do it fast? With IXCOM, all you have to do to compile those different testbenches is use the xrun command for each after compiling your DUT. But what exactly is IXCOM, and how does one start using it? This quick RAK can help—here, you’ll learn the basics of using MSIE features with IXCOM, complete with an example to get you started. Using MSIE can vastly improve your build times with Palladium and using IXCOM is the best way to shrink that tedious rebuild time as small as it can get. Check out this RAK here.

3)  JasperGold Control and Status Register Verification App Automates UVM Register Map Verification

New to the JasperGold Control and Status Register (CSR) Verification App for your UVM testbenches? Don’t worry; there’s a RAK for that! This eponymous RAK can get you up and running with this in no time, helping you automate your checks from UVM register map specs. With this RAK, you’ll learn the basics of the JasperGold CSR, how to use JasperGold CSR’s Proof Accelerator, and more. CSR features a model-based approach to predicting a register’s expected value, supports pipeline interfaces, all IP-XACT access policies, and it can fully model any expected register value. It also supports register aliases, read and write semantics, and separate read/write data latencies in any given field.

If this functionality sounds up your alley, you can take a look at this RAK here.

Curious about what’s going on behind the scenes with verification? Bernard Murphy, Jim Hogan, and our own Paul Cunningham are on the case with the “Innovation in Verification” blog stream over at semiwiki.com. Every month, this trio reviews a newly-published paper in academia that pertains to verification and discusses its implications. Be sure to stop by—it’s a great place to see what might be coming down the pipeline someday.

This month, they discuss the implications of metamorphic testing. The purpose of metamorphic testing is to define a verification approach where is there is no “golden reference.” This situation comes up a lot now as designs grow in complexity, and it begs the question: “how does one know the design is verified if there is no standard to compare to?”. Metamorphic testing addresses the problem of not having a “gold standard” to compare to by comparing the results of related tests instead. The paper reviewed by this team used metamorphic testing to study methods of managing JavaScript tags.

Paul saw this as a valuable new class of coverage. Metamorphic testing represents a way to create better distribution analyses through understanding the relationships among tests. This can reveal critical-but-complex issues that traditional verification methods may overlook. He saw this as an emerging class of coverage that new verification tools could be built around. Paul asserted that a future metamorphic-testing-based tool’s main contribution to the field of verification would be to better analyze noisy performance results where the noise is multi-modal. It could be useful in detecting race conditions and similar hard-to-debug anomalies. Paul also sees metamorphic testing as ripe for ML techniques. Overall—Paul sees a bright future for metamorphic testing in verification.

Jim is reminded of Solido and Spice—these metamorphic testing capabilities are “more than just a feature”—they might be a product. Maybe even a whole new class of verification tools, as Paul said.

Bernard says that this topic is “too rich to address in one blog”, so be sure to head over to the post to see more of what the future has in store for verification.

Longfellow's metaphorical footprints on the sands of time is more profound and eternal no doubt but a footprint for silicon (a form of sand isn't it?) is as important for PCB designers. So, here we will list the steps to create a fo...(read more)

All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through Conformal Low Power (CLP) to perform a low power structural check.  

The power structure integrity of a mixed-signal, low-power block is verified via Conformal Low Power integrated into the Virtuoso Schematic Editor Power Intent Export Assistant (VSE-PIEA). Here is the flow.

Applying the flow iteratively from lower to higher levels can verify the power structure.

Cadence customers can learn more in a Rapid Adoption Kit (RAK) titled IC 6.1.5 Virtuoso Schematic Editor XL PIEA, Conformal Low Power: Mixed-Signal Low Power Structural Verification.

• To read the overview presentation, click on following link: PIEA Overview
• To download this PIEA RAK click on following link: PIEA RAK Download

The RAK includes Rapid Adoption Kit with demo design (instructions are provided on how to setup the user environment). It Introduces the Power Intent Export Assistant (PIEA) feature that has been implemented in the Virtuoso IC615 release.  The power intent extracted is then verified by calling Conformal Low Power (CLP) inside the Virtuoso environment.

• Last Update: 11/15/2012.
• Validated with IC 6.1.5 and CLP 11.1

The RAK uses a sample test case to go through PIEA + CLP flow as follows:

• Setup for PIEA
• Perform power intent extraction
• CPF Import: It is recommended to Import macro CPF, as oppose to designing CPF for sub-blocks. If you choose to import design CPF files please make sure the design CPF file has power domain information for all the top level boundary ports
• Generate macro CPF and design CPF
• Perform low power verification by running CLP

It is also recommended to go through older RAKs as prerequisites.

• Conformal Low Power, RTL Compiler and Incisive: Low Power Verification for Beginners
• Conformal Low Power: CPF Macro Models
• Conformal Low Power and RTL Compiler: Low Power Verification for Advanced Users

To access all these RAKs, visit our RAK Home Page to access Synthesis, Test and Verification flow

Note: To access above docs, use your Cadence credentials to logon to the Cadence Online Support (COS) web site. Cadence Online Support website https://support.cadence.com/ is your 24/7 partner for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you can receive new solutions, Application Notes (Technical Papers), Videos, Manuals, and more.

You can send us your feedback by adding a comment below or using the feedback box on Cadence Online Support.

Sumeet Aggarwal

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release.  Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release.

When we talk about low-power verification its easy to equate it with simulation.  For certain, simulation is the heart of a low-power verification solution. Simulation enables engineers to run their design in the context of power intent.  The challenge is that a simulation-only approach is inadequate. For example, if engineers could achieve SoC quality by verifying the individual function of each power control module (PCM), then simulation could be enough.  For a single power domain, simulation can be enough. 

However, when the SoC has multiple power domains -- and we have seen SoCs with hundreds of them -- engineers have to check the PCMs and all of the arcs between the power modes.  These SoCs often synchronize some of the domain switching to reduce overall complexity, creating the potential for signal skew errors on the control signals for the connected domains.  Managing these complexities requires verification methodologies including advanced debug, verification planning, assertion-based verification, Universal Verification Methodology - Low Power (UVM-LP), and more (see Figure 1).

Figure 1:  Comprehensive Low-Power Verification 

But even advanced verification methodologies on top of simulation aren't enough.  For example, the state machine that defines the legal and illegal power mode transitions is often written in software. The speed and capacity of the Palladium emulation platform is ideal to verify in this context, and it is integrated with simulation sharing debug, UVM acceleration, and static checks for low-power. And, it reports verification progress into a holistic plan for the SoC.  Another example is the ability to compare the design in the implementation flow with the design running in simulation to make sure that what we verify is what we intend to build.

Taken together, verification across multiple engines provides the comprehensive low-power verification needed for today's advanced node SoCs.  That's the heart of this low-power verification announcement. 

Another point you may have noticed is the extension of the Common Power Format (CPF) based power-aware support in the Incisive Enterprise Simulator to IEEE 1801.  We chose to bring IEEE 1801 to simulation first because users like you sometimes need to mix vendors for regression flows.  Over time, Cadence will extend the low-power capabilities throughout its product suite to IEEE 1801.

If you are using CPF today, you already have the best low-power solution. The evidence is clear:  the upcoming IEEE 1801-2013 update includes many of the CPF features contributed to 1801/UPF to enable methodology convergence.  Since you already have those features in the CPF flow, any migration before you have a mature IEEE 1801-2013 tool flow would reduce the functionality you have today.

If you are using Unified Power Format (UPF) 1.0 today, you want to start planning your move toward the IEEE 1801-2013 standard.  A good first step would be to move to the IEEE 1801-2009 standard.  It fills holes in the earlier UPF 1.0 definition.  While it does lack key features in -2013, it is an improvement that will make the migration to -2013 easier. The Incisive 13.1 release will run both UPF 1.0 and IEEE 1801-2009 power intent today.

Over the next few weeks you'll see more technical blogs about the low-power capabilities coming in the Incisive 13.1 release.  You can also join us on June 19 for a webinar that will introduce those capabilities using the reference design supplied with the Incisive Enterprise Simulator release.

=Adam "The Jouler" Sherer

(Yes, "Sherilog" is still here.  :-) )

There is no better way other than a self-help training kit -- (rapid adoption kit, or RAK) -- to demonstrate the Incisive Enterprise Simulator's IEEE 1801 / UPF low-power features and its usage. The features include:

• Unique SimVision debugging 
• Patent-pending power supply network visualization and debugging
• Tcl extensions for LP debugging
• Support for Liberty file power description
• Standby mode support
• Support for Verilog, VHDL, and mixed language
• Automatic understanding of complex feedthroughs
• Replay of initial blocks
• ‘x' corruption for integers and enumerated types
• Automatic understanding of loop variables
• Automatic support for analog interconnections

Mickey Rodriguez, AVS Staff Solutions Engineer has developed a low power UPF-based RAK, which is now available on Cadence Online Support for you to download.

• This rapid adoption kit illustrates Incisive Enterprise Simulator (IES) support for the IEEE 1801 power intent standard. 

Patent-Pending Power Supply Network Browser. (Only available with the LP option to IES)

• In addition to an overview of IES features, SimVision and Tcl debug features, a lab is provided to give the user an opportunity to try these out.

The complete RAK and associated overview presentation can be downloaded from our SoC and Functional Verification RAK page:

We are covering the following technologies through our RAKs at this moment:

Synthesis, Test and Verification flow
Encounter Digital Implementation (EDI) System and Sign-off Flow
Virtuoso Custom IC and Sign-off Flow
Silicon-Package-Board Design
Verification IP
SOC and IP level Functional Verification
System level verification and validation with Palladium XP

Please visit https://support.cadence.com/raks to download your copy of RAK.

We will continue to provide self-help content on Cadence Online Support, your 24/7 partner for learning more about Cadence tools, technologies, and methodologies as well as getting help in resolving issues related to Cadence software. If you are signed up for e-mail notifications, you're likely to notice new solutions, application notes (technical papers), videos, manuals, etc.

Note: To access the above documents, click a link and use your Cadence credentials to log on to the Cadence Online Support https://support.cadence.com/ website.

Happy Learning!

Sumeet Aggarwal and Adam Sherer

ST Microelectronics reported their success with IEEE 1801 / UPF low-power simulation using Incisive Enterprise Simulator at CDNLive India in November 2013. We were able to meet with Mohit Jain just after his presentation and recorded this video that explains the key points in his paper.

With eight years of experience and pioneering technology in native low-power simulation, Mohit was able to apply Incisive Enterprise Simulator to a low-power demonstrator in preparation for use with a production set-top box chip.  Mohit was impressed with the ease in which he was able to reuse his existing IEEE 1801 / UPF code successfully, including the power format files and the macro models coded in his Liberty files. Mohit also discusses how he used the power-aware Cadence SimVision debugger.

The Cadence low-power verification solution for IEEE 1801 / UPF also incorporates the patent-pending Power Supply Network visualization in the SimVision debugger.  You can learn more about that in the Incisive low-power verification Rapid Adoption Kit for IEEE 1801 / UPF here in Cadence Online Support.

Just another happy Cadence low-power verification user!

Regards,

 Adam "The Jouler" Sherer 

Freescale was a successful Incisive® simulation CPF low-power user when they decided to step up their game. In November 2013, at CDNLive India, they presented a paper explaining how they improved their ability to find power-related bugs using a more sophisticated verification flow.  We were able to catch up with Abhinav Nawal just after his presentation to capture this video explaining the key points in his paper.

Abhinav had already established a low-power simulation process using directed tests for a design with power intent captured in CPF. While that is a sound approach, it tends to focus on the states associated with each power control module and at least some of the critical power mode changes.  Since the full system can potentially exercise unforeseen combinations of power states, the directed test approach may be insufficient. Abhinav built a more complete low-power verification approach rooted in a low-power verification plan captured in Cadence® Incisive Enterprise Manager.  He still used Incisive Enterprise Simulator and the SimVision debugger to execute and debug his design, but he also added Incisive Metric Center to analyze coverage from his low-power tests and connect that data back to the low-power verification plan.  As a result, he was able to find many critical system-level corner case issues, which, left undetected, would have been catastrophic for his SoC.  In the paper, Abhinav presents some of the key problems this approach was able to find.

You can achieve results similar to Abhinav. Incisive Enterprise Simulator can generate a low-power verification plan from the power format, power-aware assertions, and it can collect power-aware knowledge.  To get started, you can use the Incisive Low-Power Simulation Rapid Adoption Kit (RAK) for CPF available on Cadence Online Support.

Just another happy Cadence low-power verification user!

Regards,

Adam "The Jouler" Sherer  

Key findings: 5X to 32X faster low-power verification using Palladium XP emulation

It’s hot in July in Korea, and not just the temperature; the ideas, too. The ideas that flowed at CDNLive Korea were exciting, and that includes a very interesting talk by Jiyeon Park from the System LSI division of Samsung Electronics.  His talk, titled “Enabling Low-Power Verification using Cadence Palladium XP,” struck a chord with the audience and the highlights bear sharing in this forum. This blog captures some of the highlights from the public talk in Seoul this summer.

Motivation

If you are familiar with the breadth of the product lines at Samsung Electronics, you will appreciate the diversity of the end-market requirements that they must fulfill. These markets and products include:

Mobile/Handheld

• Smartphones
• Tablets
• Laptops

Consumer/Digital Home

• High-definition/ultra-high-definition TV
• Gaming consoles
• Computers 

Networking/Data Center

• Servers
• Switches
• Communications

What all of these markets have in common is that energy efficiency is now an integral and leading part of the value equation. For design teams, a good knowledge of power helps the evaluation and use of a host of critical decisions. From design architecture, IP make-versus-buy decisions, and manufacturing process selection, to the use of low-power design techniques, all are critically influenced by power.

Using simulation for low-power verification

Once the decision to overlay power reduction design techniques, such as power shutdown, has been made, new dimensions have been added to the already complex SoC verification task. The RTL verification environment is first augmented with a power intent file; in this case, IEEE 1801 was the format.  The inclusion of this power intent information enables the examination of power domain shutdown, isolation operations, proper retention, and level shifting.

Figure 1: Incisive SimVision power verification elements example

Low-power verification using emulation

Simulation for low-power verification works well, so why emulation? One word—complexity!  It is easy to forget that “design complexity” (usually measured in gates or transistors) is not that same as “verification complexity” (which is really hard to measure). Consider a design with four power domains, three of which are switchable and one that is switchable but also has high- and low-voltage states. That yields nine basic states, and 24 modes of operation to test. Although some of those modes may not be consequential, when paired with hundreds or even thousands of functional tests, you can begin to understand the impact of overlaying low power on the verification problem. Thus, it becomes very desirable to enlist the raw computational power of emulation.

Power off/on scenario on Palladium XP platform

A typical functional test would be augmented to include the power control signals. For power shutoff verification, for instance, the cycles for asserting isolation begin the sequence, followed by state retention, and then finally a power shutdown of the domain must be asserted to verify operation. The figure below calls out a number of checks that ought to be performed.

Figure 2: Power shutoff sequence and associated checks to make

IEEE 1801 support in Palladium XP platform

The IEEE 1801 support found in the Palladium PX platform includes some noteworthy capabilities, as well as some implications to the user. First is a patented memory randomization provided by the Palladium XP platform. This capability includes randomization of memory during shutdown and power up, control over read value during the power-off state, non-volatile memory state retention, and freezing of data on retention. The user should be aware there is about a 10%-20% capacity overhead associated with IEEE 1801-driven low-power verification.

Figure 3: Palladium low-power verification enables schedule improvement

Palladium low-power verification flow

The great thing about the emulation work flow for IEEE 1801 power verification is that the only change is to include that IEEE 1801 power intent file during the compilation stage!

Considerations for emulation environment bring-up

A Universal Verification Methodology (UVM) approach was taken by the Samsung team. This provides a unique structure to the testbench environment that is very conducive to a metric-driven methodology.  Using a testbench acceleration interface, teams can run the testbench on a software simulator and the design on the emulator. In addition, the formalism allows for the case of incomplete designs that do not hinder the verification of the parts that are completed.

Experimental results

The most exciting part of the paper was the results that were obtained. For a minor overhead cost in compile time and capacity, the team was able to improve runtimes of their tests by 5X to 32X. Being able run tests in a fraction of the time, or many more tests in the same time, has always been a benefit for emulation users. Now low-power verification is a proven part of the value provided to Palladium XP platform users.

Figure 4: Samsung low-power verification emulation results

Conclusions

The key conclusions found were:

• No modification was needed for IEEE 1801
• There is a small capacity and compile time overhead
• The emulation and simulation match
• The longer the test, the more the net speed up versus software simulation
• Run times improved from 5X to 32X!

With this flow in place, the teams has begun power-aware testing that includes firmware and software verification to go along with the hardware testing. This expansion enables more capability in optimization of the power architecture. In addition, they are seeing faster silicon bring-up in the context of an applied low-power strategy.

Steve Carlson

Hello, i have a realy mistick thing going with copying libraries in cadence virtuoso,

When i copy straight forwart the whole library it gives me a warning that accsess was denied,but when i go into the library and copy it as a single file, then it goes fine.

another problem is it doesnt show in the massage console  ALL the files which could not be copied.(which is the much bigger problem,becuase i would have to pass threw all the subdirectories to verify if all files are there)

Is there a way to see which files wasnt able to be copied?

Thanks. 

Hello , i am trying to extract netlist from a circuit  in assembler

I have found the manual shown bellow , however there is no such option in tools in assembler.

how do i view the NETLIST of this circuit?

Thanks.

ASSEMBLER VIEW menu

Hello,

Would anyone know how to setup a PSS or QPSS simulation with 25% dutycycle clock sources or if such a thing is possible with QPSS.

Fig1 (below) is a snapshot of the circuit I am trying to characterize. This has 4 clock ports each with 25%duty cycle in the ON state. Fig2 below shows two of these clocks.

Each path in the circuit consists of two switches with a low pass RC sandwiched in between. The Input is a 50Ohm port sine wave and the output is a 1K resistor. The output nets of all paths are connected together.

I am trying to determine the swept frequency response from input to output (voltage) when the input is from 500Mhz to  510MHz. The Period (T=1/Fp) of each of the pulses is such that Fp=500MHz. The first pulse source has a delay=0, second has delay=T/4, third delay=2T/4, etc...

I am currently getting it working and seeing the correct result (bandpass response) with Transient but the problem is doing a dft at 500MHz with 10KHz spacings needs at least 100us and takes up a lot of time and disk space.

Many Thanks,
Chris.

Fig1

Fig2

Hello

The document I referenced is https://filebox.ece.vt.edu/~symort/rfworkshop/Mixer_workshop_instruction.pdf. (This is cadence workshop document)

While following the pxf simulation in the above article, the results are different and I have a question.

My result picture is shown below.

<my result error>

<document result>

<my direct plot>

<document direct plot>

The difference with the documentation is that in the direct plot screen after the pxf simulation,

1.output harmonics-> input sideband

2.Frequency axis: out-> frequency axis: absin

3.The results for port0 (RF port) are also different (see photo below).

4.The frequency values in the box are different.

My screen shows 5G, 10G, 1K ~ 10M, but the document is the same as 1K ~ 10M.

Ask for a solution. Thank you.

Hello, I am trying to use two inductors in my LNA as shown bellow to have a S-PARAM response so i will have S11 with lowerst possible values and tweak them for matching network. However when i ran EXPLORER live tuning with SParam as shown bellow i get no change in the response.

I know that Cgs and Cgd with the inductors having a resonance so by Varying L value i should have seen the change in resonance location,

But there is no change.Where did i go wrong?

Thanks. 

Hello, I looking for reaching minimal NOISE FIRUGE by peaking a combination of the RLC on the output load as shown bellow.
I tried to do it with PNOISE  but it gives me an error on the |f(in)| i am not sure regarding the sidebands in my case(its not a mixer)

How can i show Noise Figure and optimize it using my output RLC?

Thanks

Hello, i have made a power gain circle for 30dB,for setting a GAIN we need to set a matching network for input and output inpedance.

but in this Gain circles it shows me only one complex number instead of two.(As shown bellow)

Where did i go wrong with using it to find the input and output impedancies needed to be matched in order to have 30dB gain?
Thanks.

Hi, all

Recently, I meet the simulation error as the picture shows when I simulate my circuit with transient.  how can I solve this problem?

thank you~

Hello, i need to test the  parameter Kf under some conditions in subthreshold.i cannot just plot the OP param,becasue i need to derive it under certain conditions.

Spectre(of Cadence) like BSIM(of Berkley) has developed a method for deriving each parameter in their model.

Is there a way to help me with such manual where i can test in cadence virtuoso the Kf parameter shown in the formula bellow?

Thanks.

Hi All,

I saw the cadence tutorial on measuring IIP3 with 3 tones test (Lets say I have a mixer in the test so two tones are entered in the RF port and one is the LO).

Now, I would like to verify if my receiver meets the bluetooth standard. In the standard it says to enter a signal at -64dBm and two additional signals (interference) 

at -39dBm each which placed one k (lets say k equals to one for the example) channels apart and the other 2k channels apart (so 3 signals enter the RF port). These signals cause an intermodulation product to fall

at the frequency of the desired signal. I would like to measure the IIP3 in this case. 

Now, I need to enter 4 tones and the IIP3 is measured (based on cadence tutorial) using sweep in the hb.

I do not want to sweep power since I need to enter exact power. I tried to use multi sinusoidal option in the port with exact power but it does not work.

How in general am I be able to check communication standard in this way using virtuoso and measure IIP3?

Can someone please help me?

Thanks in advance! 

Hi,

i am designing a broadband (100 MHz -6 GHz BW) receiver chain for  radar/rcs measurement tester. i will put Low noise amplifier after antenna input followed by mixed(10 MHz IF BW and digitizer.

I am facing problem regarding LAN. bandwidth of LAN is  approx 6 GHz(100 MHz-6GHz), gain 25-35 dB, with NF less than 2. I am uncertain about noise floor at the output of LNA.  I dont know exact SNR at the input of LNA but it shall be good.System operation will be on stepped CW waveform so receiver input signal will sweep over the BW and some step size.

so LNA output r noise floor will be? i assume, we can neglect thr role of input noise because it will be lesser than internal noise of LNA.

will it be LNA internal noise (Thermal noise due to BW) only ?

will it be LNA internal noise (Thermal noise due to BW)  + LAN Gain ? -78+25 =-53 dB? internal noise shall be lesser because NF is less than 3 . 

i have practically observed that that output noise floor is much lesser then even thermal noise( over LNA BW). i have gone through some tutorial where  formula says( internal noise+input noise)+gain. in  my case input noise shall be much less than theoretical internal noise. 

Thanks

Hi, when I applied a voltage divider implemented by two 100-ohm resistors to a 2Vpp 5GHz vsin source, the phase noise simulation using pnoise/fullspectrum with different types, jitter and source have different results. The simulated output noise results are 165.76aV2/Hz for pmjitter case, and 828.79zV2/Hz for source case. The source case result equals to the output noise calculation.

For my application, the output will be applied to driven circuits and thus pm jitter is concerned. As the pmjitter is based on the noise sampling at the threshold crossings, I was wondering how spectre gets the pmjitter resullts since sampling white noise with infinite bandwidth is impossible to my knowledge?

Interestingly, the Jee result by integration from 10kHz to 2.5GHz is ~41fs and is closed to Jee,rms from the transient noise simulation. I am also not sure how these results come and match each other. If applying the voltage divider output to drive next stages, I was wondering to what extent I can trust the input jitter from these simulations? Thank you.

Hi,

i'm using spectre HB simulation on PA (Power Amplifier) test_bench to perform large signal analysis (i want to plot Output power vs intput power, PAE and Gain)

Although the simulation returns no error, i still can't plot anything. seem like there is an issue with the ports i'm using. (analoglib ports)

i attach an image of my configuration so maybe you can find something helpful in it. 

thank you all for your help

best regards

hi everyone, 

i'm trying to create a netlist for aging simulation. i would like to simulate how power, Gain and PAE (efficiency) are inlfuenced after 3 hours

i would be grateful if someone can correct my syntax in the netlist since i'm trying to make a sweep HB  simulation where the input power is the parameter.

i did it without any error for the sp (S parameters)  simulation.

you can see the images for both sp and hb simulation netlists. (from left to right: sp aging netlist; hb aging netlist)

i will be grateful if someone can provide me some syntax advices.

thanks,

best regards

I have a script to handle many polys in memory in allegro. 

But after the completion of the script, 

I run the axlPolyMemUse(), it reports (31922 0 0 55076 252482)

Seems too many polys are still in the memory，and they are not being used. 

So how to delete these polys from the memory? And reclaim the memory?

BTW. I have no skill dev license. So gc() function doesn't work. 

Thanks.

Hi,

I wanted to find the location of a pin in the design using skill program. pin_dbids = axlDBGetDesign()->pins, this gives me all the dbids of the pins that are present in my design. But when im entering that dbid, pad = axlDBGetPad("000001EA8FD8B9F8" "package geometry/assembly_top" "regular") it is throwing an error stating "This dbid is not user defined. Please enter the user defined". So please provide me a snippet so that I can get the exact pin location in the design using skill script.

Hi guys,

eDave,

I need to call (replay) a skill to combine some skills to ONE UI for more convenience and using as more easier.

Please help me to find the command to execute this.(code for example as more good)

HT,

Hi 

I'm trying to find the location of the assembly line in the design automatically without using "Show Element". And also I want to find the end points of that line. The line exists in "Package Geometry/Assembly_Top" Layer. So is there any code snippet to find the location of assembly line?

For a project, we depend on capturing warnings. This works fine in Virtuoso but behaves differently in Allegro.

In our observations

Virtuoso:

>>> warn("Hello")

*WARNING* Hello

Allegro:

>>> warn("Hello")

*WARNING* Hello

But when we capture the warning:

Virtuoso:

>>> warn("Hello") getWarn()

"Hello"

Allegro:

>>> warn("Hello") getWarn()

"*WARNING* Hello"

This is a Problem for because we put an empty String in the warn and depend on the fact that no Warning results in an empty String but on Allegro the output always begins with *WARNING*

Is there a way to make the behavior consistent in both versions?

This is the 15th installment of The Rationalist, my column for the Times of India.

It’s election season, and promises are raining down on voters like rose petals on naïve newlyweds. Earlier this week, the Congress party announced a minimum income guarantee for the poor. This Friday, the Modi government released a budget full of sops. As the days go by, the promises will get bolder, and you might feel important that so much attention is being given to you. Well, the joke is on you.

Every election, HL Mencken once said, is “an advance auction sale of stolen goods.” A bunch of competing mafias fight to rule over you for the next five years. You decide who wins, on the basis of who can bribe you better with your own money. This is an absurd situation, which I tried to express in a limerick I wrote for this page a couple of years ago:

POLITICS: A neta who loves currency notes/ Told me what his line of work denotes./ ‘It is kind of funny./ We steal people’s money/And use some of it to buy their votes.’

We’re the dupes here, and we pay far more to keep this circus going than this circus costs. It would be okay if the parties, once they came to power, provided good governance. But voters have given up on that, and now only want patronage and handouts. That leads to one of the biggest problems in Indian politics: We are stuck in an equilibrium where all good politics is bad economics, and vice versa.

For example, the minimum guarantee for the poor is good politics, because the optics are great. It’s basically Garibi Hatao: that slogan made Indira Gandhi a political juggernaut in the 1970s, at the same time that she unleashed a series of economic policies that kept millions of people in garibi for decades longer than they should have been.

This time, the Congress has released no details, and keeping it vague makes sense because I find it hard to see how it can make economic sense. Depending on how they define ‘poor’, how much income they offer and what the cost is, the plan will either be ineffective or unworkable.

The Modi government’s interim budget announced a handout for poor farmers that seemed rather pointless. Given our agricultural distress, offering a poor farmer 500 bucks a month seems almost like mockery.

Such condescending handouts solve nothing. The poor want jobs and opportunities. Those come with growth, which requires structural reforms. Structural reforms don’t sound sexy as election promises. Handouts do.

A classic example is farm loan waivers. We have reached a stage in our politics where every party has to promise them to assuage farmers, who are a strong vote bank everywhere. You can’t blame farmers for wanting them – they are a necessary anaesthetic. But no government has yet made a serious attempt at tackling the root causes of our agricultural crisis.

Why is it that Good Politics in India is always Bad Economics? Let me put forth some possible reasons. One, voters tend to think in zero-sum ways, as if the pie is fixed, and the only way to bring people out of poverty is to redistribute. The truth is that trade is a positive-sum game, and nations can only be lifted out of poverty when the whole pie grows. But this is unintuitive.

Two, Indian politics revolves around identity and patronage. The spoils of power are limited – that is indeed a zero-sum game – so you’re likely to vote for whoever can look after the interests of your in-group rather than care about the economy as a whole.

Three, voters tend to stay uninformed for good reasons, because of what Public Choice economists call Rational Ignorance. A single vote is unlikely to make a difference in an election, so why put in the effort to understand the nuances of economics and governance? Just ask, what is in it for me, and go with whatever seems to be the best answer.

Four, Politicians have a short-term horizon, geared towards winning the next election. A good policy that may take years to play out is unattractive. A policy that will win them votes in the short term is preferable.

Sadly, no Indian party has shown a willingness to aim for the long term. The Congress has produced new Gandhis, but not new ideas. And while the BJP did make some solid promises in 2014, they did not walk that talk, and have proved to be, as Arun Shourie once called them, UPA + Cow. Even the Congress is adopting the cow, in fact, so maybe the BJP will add Temple to that mix?

Benjamin Franklin once said, “Democracy is two wolves and a lamb voting on what to have for lunch.” This election season, my friends, the people of India are on the menu. You have been deveined and deboned, marinated with rhetoric, seasoned with narrative – now enter the oven and vote.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 18th installment of The Rationalist, my column for the Times of India.

The man who gave us our national anthem, Rabindranath Tagore, once wrote that nationalism was “a great menace.” He went on to say, “It is the particular thing which for years has been at the bottom of India’s troubles.”

Not just India’s, but the world’s: In his book The Open Society and its Enemies, published in 1945 as Adolf Hitler was defeated, Karl Popper ripped into nationalism, with all its “appeals to our tribal instincts, to passion and to prejudice, and to our nostalgic desire to be relieved from the strain of individual responsibility which it attempts to replace by a collective or group responsibility.”

Nationalism is resurgent today, stomping across the globe hand-in-hand with populism. In India, too, it is tearing us apart. But must nationalism always be a bad thing? A provocative new book by the Israeli thinker Yael Tamir argues otherwise.

In her book Why Nationalism, Tamir makes the following arguments. One, nation-states are here to stay. Two, the state needs the nation to be viable. Three, people need nationalism for the sense of community and belonging it gives them. Four, therefore, we need to build a better nationalism, which brings people together instead of driving them apart.

The first point needs no elaboration. We are a globalised world, but we are also trapped by geography and circumstance. “Only 3.3 percent of the world’s population,” Tamir points out, “lives outside their country of birth.” Nutopia, the borderless state dreamed up by John Lennon and Yoko Ono, is not happening anytime soon.

If the only thing that citizens of a state have in common is geographical circumstance, it is not enough. If the state is a necessary construct, a nation is its necessary justification. “Political institutions crave to form long-term political bonding,” writes Tamir, “and for that matter they must create a community that is neither momentary nor meaningless.” Nationalism, she says, “endows the state with intimate feelings linking the past, the present, and the future.”

More pertinently, Tamir argues, people need nationalism. I am a humanist with a belief in individual rights, but Tamir says that this is not enough. “The term ‘human’ is a far too thin mode of delineation,” she writes. “Individuals need to rely on ‘thick identities’ to make their lives meaningful.” This involves a shared past, a common culture and distinctive values.

Tamir also points out that there is a “strong correlation between social class and political preferences.” The privileged elites can afford to be globalists, but those less well off are inevitably drawn to other narratives that enrich their lives. “Rather than seeing nationalism as the last refuge of the scoundrel,” writes Tamir, “we should start thinking of nationalism as the last hope of the needy.”

Tamir’s book bases its arguments on the West, but the argument holds in India as well. In a country with so much poverty, is it any wonder that nationalism is on the rise? The cosmopolitan, globe-trotting elites don’t have daily realities to escape, but how are those less fortunate to find meaning in their lives?

I have one question, though. Why is our nationalism so exclusionary when our nation is so inclusive?

In the nationalism that our ruling party promotes, there are some communities who belong here, and others who don’t. (And even among those who ‘belong’, they exploit divisions.) In their us-vs-them vision of the world, some religions are foreign, some values are foreign, even some culinary traditions are foreign – and therefore frowned upon. But the India I know and love is just the opposite of that.

We embrace influences from all over. Our language, our food, our clothes, our music, our cinema have absorbed so many diverse influences that to pretend they come from a single legit source is absurd. (Even the elegant churidar-kurtas our prime minister wears have an Islamic origin.) As an example, take the recent film Gully Boy: its style of music, the clothes its protagonists wear, even the attitudes in the film would have seemed alien to us a few decades ago. And yet, could there be a truer portrait of young India?

This inclusiveness, this joyous khichdi that we are, is what makes our nation a model for the rest of the world. No nation embraces all other nations as ours does. My India celebrates differences, and I do as well. I wear my kurta with jeans, I listen to ghazals, I eat dhansak and kababs, and I dream in the Indian language called English. This is my nationalism.

Those who try to divide us, therefore, are the true anti-nationals. We must reclaim nationalism from them.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 19th installment of The Rationalist, my column for the Times of India.

A friend of mine was very impressed by the interview Narendra Modi granted last week to Akshay Kumar. ‘Such a charming man, such great work ethic,’ he gushed. ‘He is the kind of uncle I would want my kids to have.’ And then, in the same breath, he asked, ‘How can such a good man be such a bad prime minister?”

I don’t want to be uncharitable and suggest that Modi’s image is entirely manufactured, so let’s take the interview at face value. Let’s also grant Modi his claims about the purity of his neeyat (intentions), and reframe the question this way: when it comes to public policy, why do good intentions often lead to bad outcomes? To attempt an answer, I’ll refer to a story a friend of mine, who knows Modi well, once told me about him. 

Modi was chilling with his friends at home more than a decade ago, and told them an incident from his childhood. His mother was ill once, and the young Narendra was tending to her. The heat was enervating, so the boy went to the switchboard to switch on the fan. But there was no electricity. My friend said that as he told this story, Modi’s eyes filled with tears. Even after all these years, he was moved by the memory.

My friend used this story to make the point that Modi’s vision of the world is experiential. If he experiences something, he understands it. When he became chief minister of Gujarat, he made it his stated mission to get reliable electricity to every part of Gujarat. No doubt this was shaped by the time he flicked a switch as a young boy and the fan did not budge. Similarly, he has given importance to things like roads and cleanliness, since he would have experienced the impact of those as a young man.

My term for him, inspired by Rajat Kapoor’s 2014 film, is ‘the ankhon dekhi prime minister’. At one level, this is a good thing. He sees a problem and works for the rest of his life to solve it. But what of things he cannot experience?

The economy is a complex beast, as is society itself, and beyond a certain level, you need to grasp abstract concepts to understand how the world works. You cannot experience them. For example, spontaneous order, or the idea that society and markets, like language, cannot be centrally directed or planned. Or the positive-sum nature of things, which is the engine of our prosperity: the idea that every transaction is a win-win game, and that for one person to win, another does not have to lose. Or, indeed, respect for individual rights and free speech.

One understands abstract concepts by reading about them, understanding them, applying them to the real world. Modi is not known to be a reader, and this is not his fault. Given his background, it is a near-miracle that he has made it this far. He wasn’t born into a home with a reading culture, and did not have either the resources or the time when he was young to devote to reading. The only way he could learn about the world, thus, was by experiencing it.

There are two lessons here, one for Modi himself and others in his position, and another for everyone.

The lesson in this for Modi is a lesson for anyone who rises to such an important position, even if he is the smartest person in the world. That lesson is to have humility about the bounds of your knowledge, and to surround yourself with experts who can advise you well. Be driven by values and not confidence in your own knowledge. Gather intellectual giants around you, and stand on their shoulders.

Modi did not do this in the case of demonetisation, which he carried out against the advice of every expert he consulted. We all know the damage it caused to the economy.

The other learning from this is for all of us. How do we make sense of the world? By connecting dots. An ankhon-dekhi approach will get us very few dots, and our view of the world will be blurred and incomplete. The best way to gather more dots is reading. The more we read, the better we understand the world, and the better the decisions we take. When we can experience a thousand lives through books, why restrict ourselves to one?

A good man with noble intentions can make bad decisions with horrible consequences. The only way to hedge against this is by staying humble and reading more. So when you finish reading this piece, think of an unread book that you’d like to read today – and read it!

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

This is the 21st installment of The Rationalist, my column for the Times of India.

When all political parties agree on something, you know you might have a problem. Giriraj Singh, a minister in Narendra Modi’s new cabinet, tweeted this week that our population control law should become a “movement.” This is something that would find bipartisan support – we are taught from school onwards that India’s population is a big problem, and we need to control it.

This is wrong. Contrary to popular belief, our population is not a problem. It is our greatest strength.

The notion that we should worry about a growing population is an intuitive one. The world has limited resources. People keep increasing. Something’s gotta give.

Robert Malthus made just this point in his 1798 book, An Essay on the Principle of Population. He was worried that our population would grow exponentially while resources would grow arithmetically. As more people entered the workforce, wages would fall and goods would become scarce. Calamity was inevitable.

Malthus’s rationale was so influential that this mode of thinking was soon called ‘Malthusian.’ (It is a pejorative today.) A 20th-century follower of his, Harrison Brown, came up with one of my favourite images on this subject, arguing that a growing population would lead to the earth being “covered completely and to a considerable depth with a writhing mass of human beings, much as a dead cow is covered with a pulsating mass of maggots.”

Another Malthusian, Paul Ehrlich, published a book called The Population Bomb in 1968, which began with the stirring lines, “The battle to feed all of humanity is over. In the 1970s hundreds of millions of people will starve to death in spite of any crash programs embarked upon now.” Ehrlich was, as you’d guess, a big supporter of India’s coercive family planning programs. ““I don’t see,” he wrote, “how India could possibly feed two hundred million more people by 1980.”

None of these fears have come true. A 2007 study by Nicholas Eberstadt called ‘Too Many People?’ found no correlation between population density and poverty. The greater the density of people, the more you’d expect them to fight for resources – and yet, Monaco, which has 40 times the population density of Bangladesh, is doing well for itself. So is Bahrain, which has three times the population density of India.

Not only does population not cause poverty, it makes us more prosperous. The economist Julian Simon pointed out in a 1981 book that through history, whenever there has been a spurt in population, it has coincided with a spurt in productivity. Such as, for example, between Malthus’s time and now. There were around a billion people on earth in 1798, and there are around 7.7 billion today. As you read these words, consider that you are better off than the richest person on the planet then.

Why is this? The answer lies in the title of Simon’s book: The Ultimate Resource. When we speak of resources, we forget that human beings are the finest resource of all. There is no limit to our ingenuity. And we interact with each other in positive-sum ways – every voluntary interactions leaves both people better off, and the amount of value in the world goes up. This is why we want to be part of economic networks that are as large, and as dense, as possible. This is why most people migrate to cities rather than away from them – and why cities are so much richer than towns or villages.

If Malthusians were right, essential commodities like wheat, maize and rice would become relatively scarcer over time, and thus more expensive – but they have actually become much cheaper in real terms. This is thanks to the productivity and creativity of humans, who, in Eberstadt’s words, are “in practice always renewable and in theory entirely inexhaustible.”

The error made by Malthus, Brown and Ehrlich is the same error that our politicians make today, and not just in the context of population: zero-sum thinking. If our population grows and resources stays the same, of course there will be scarcity. But this is never the case. All we need to do to learn this lesson is look at our cities!

This mistaken thinking has had savage humanitarian consequences in India. Think of the unborn millions over the decades because of our brutal family planning policies. How many Tendulkars, Rahmans and Satyajit Rays have we lost? Think of the immoral coercion still carried out on poor people across the country. And finally, think of the condescension of our politicians, asserting that people are India’s problem – but always other people, never themselves.

This arrogance is India’s greatest problem, not our people.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Hello,
I'm exploring VManager tool capabilities.

I launched a simulation with xrun, which terminates with a fatal error (`uvm_fatal actually).

Then I imported the flow session, through VManager -> Regression -> Collect Runs, linking the directory with ucm and ucd of just failed run.

VManager imports the test with following attributes:

Total Runs =1

#Passed =1

#Failed =0

What I'm missing here? It should be imported as failed test.

If I right click on flow name and choose Analyze All Runs, VManager brings me to Analysis tab and I can see only a PASSED tag in Runs subwindow.

Thank you for any help

Hi all,

I would like to understand if it is possible from Simvision to get the information regarding the view of a block. In principle using the Schematic Tracer Simvision is able to find the information about the config of that particular model, but I did not found a command for describing the nature of the module (for example if it is schematic or rtl or real model...)

Any functions that I can use for this purpose?

Many thanks

I'm sending encrypted HDL to a customer who will use Cadence IES for simulation and was wondering how I should go about the encryption.

Does IES support the IEEE's P1735 and if so, where can I find Cadence's public key for performing the encryption?

Or is there an alternative solution that I can use for encryption?

Hi All,

I'm trying to understand checkpoint concept. When I found save and restart concept in cdnshelp, There is just describing about "$save" and "xrun -r "~~~".

and I found also the below link about save restart and it saves your time.

But I can't find any benefits from my experiment from save&restart article( I fully agree..the article)

Ok, So I'v got some experiment  Here.

1. I declared $save and got the below result as I expected within the simple UVM code.

In UVM code...

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST3");
$display("TEST4");

And I restart at "SAVE_TEST" point by xrun -r "SAVE_TEST", I've got the below log

xcelium> run
TEST3
TEST4

Ok, It's Good what I expected.(The concept of Save and Restore is simple: instead of re-initializing your simulation every time you want to run a test, only initialize it once. Then you can save the simulation as a “snapshot” and re-run it from that point to avoid hours of initialization times. It used to be inconvenient. I agree..)

2. But The Problem is that I can't restart with modified code. Let's see the below example.

I just modified TEST5 instead of "TEST3"

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST5"); //$display("TEST3");
$display("TEST4");

and I rerun with xrun -r "SAVE_TEST", then I've got the same log

xcelium> run
TEST3
TEST4

There is no "TEST5". Actually I expected "TEST5" in the log.From here We know $save can't support partially modified code after $save. 

Actually, through this, we can approach to our goal about saving developing time. 

So I want to know Is there any possible way that instead of re-initializing our simulation every time we want to run a test, only initialize it once and keep developing(debugging) our code ?

If we do, Could you let me know the simple example?

Hi all,

         I want to know how to run a regressive test in cadence and merge all ncsim .trn file of each test case into a single file to view all waveform in simvision. I am using Makefile to invoke the test case.

         eg:-

               test0:

                     irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test0

             test1:

                   irun -uvm -sv -access +rwc $(RTL) $(INTER) $(PKG) $(TOP) $(probe) +UVM_VERBOSITY=UVM_MEDIUM +UVM_TESTNAME=test1

          I just to call test0 followed by test1 or parallel both test and view the waveform for both tests case.

        I new to this tool and help me with it

xmsim is not exiting the simulation for this error. It is unusual for the simulator to not exit for an error. I have just started using uvm and this is occurring during the randomization step for a sequencer item.

xmsim: *E,RNDCNSTE

I am using -EXIT on the command line.

I am using Xcelium 19.03-s013.

Any insights are appreciated. Thanks.

-Jim