Hello folks,

Greetings.

One of my customer claims that he is using Cadence IES version 18.09.011 with Vivado 2019.2. The version of IES that we officially support with Vivado 2019.2 is 15.20.073. Though the tool is forward compatible, I am not sure what are the versions of IES that are released after 15.20.073. Could you please give me a list of the versions of Cadence IES released after 15.20.073 and which is the latest version as of now ?

Best regards,

Chinmay

I am importing sessions which are run by other people to analyse and I would like to remove them from my vManager Regressions tab as they become obsolete. As I am not the original person who run the sims, I cannot "delete" sessions. What are my options? Thanks.

hi,

due to technical problem i am running simulation through terminal. Therefore, I have a Verilog file, a test bench and i have also exported from Genus synthesized netlist and sdf file. Now, how can i annotate sdf in my post-synthesis simulation using XCELIUM while using command line?

thank you

When I run simulation with irun, it may use may license features. How can I know which feature(s) a product use? I get below message in cdnshelp:

-------------------------------------------------------------

Which Products Are in the License File?

One Cadence product can require more than one license (FEATURE). The product to feature mapping in the license file lists the licenses each product needs.

For example, if the license file lists these features for the NC-VHDL Simulator:

Product Name: Cadence(R) NC-VHDL Simulator
#
Type: Floating Exp Date: 31-jul-2006 Qty: 1
#
Feature: NC_VHDL_Simulator [Version: 9999.999]
#
Feature: Affirma_sim_analysis_env [Version: 9999.999]

-------------------------------------------------------------------

But, in my license file, I can't find such info. There is only "FEATURE" lines in my license file. How can I get product to feature mapping info?

Thanks!

We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go – items at the grocery store, advertisements and posters, even on websites. Did you know that, with the productivity toolbox in Allegro Package Designe...(read more)

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in th...(read more)

If you design wire bond packages, you’re familiar with the need for the bond fingers and rings on the package substrate layers to be exposed through the solder mask layer. If they aren’t, it becomes… rather difficult… to bon...(read more)

Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...(read more)

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...(read more)

Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack revision. a new NETLIST generation have been done after some corrections made in Capture. I have imported the new Logic. I revised my Layout Cross Section as such: TOP, GND, VCC, BOTTOM. Both VCC and GND shapes have been assigned to their respective logical GND and VCC Nets (verified). Yet, I still have the Autorouter to systematically use extra vias to make GND and VCC connections to the VCC and GND planes. Where a simple utilisation of the part padstack inner layer would have been indicated. What Im I missing ?

Is anyone else using Constraint Manager within Capture? This is my first time using it. I'm finding that it is occasionally changing some of my constraint values in Allegro. It seems random. 

Picture 1 show a Shape created in Allegro PCB Editor 16.6, file LTshape.ssm      The Shape Origin is dead center of the outline 565X400 mils.    This Shape is utilized in the PadStack Editor to create a special Pin for a custom Footprint.
Picture 2 show the PadStack Editor first page with drill size and offset. File  LTshape16.pad         Picture 3 show the PadStack Editor page 2 with that LTshape utilized as the BEGIN LAYER for copper area. Picture 4 show the actual Package (footprint) finished with Outline, padstacks for pin 1,2,4,5 and that special Pin 3 LTshape. Its origin is also dead center, same as LTshape.ssm

Notice the round dot at the bottom of Pin 3. It only appear in the Package drawing, not in the original Picture 1, the actual LTshape.ssm or LTshape.dra

Picture 5 shows that same Footprint in the final board in PCB Editor. That same dot, now pink, is still there and cannot be selected separately. When using the Find Option and selecting each object separately, the only way to select Pin 3 is when Option > Pin is selected. Then I can hover on the dot near Pin 3 and the whole LTshape lights up as pin 3, but not the pink dot. There is absolutely no way I can select that dot as an object. There is no way to know the existence of that dot except by looking at it. Cannot be deleted, cannot be selected, can only be invisible if I use the Color Visibility manager and disable all 4 layers, TOP GND VCC BOTTOM. If I turn On TOP then the dot becomes pink. With GND On the dot is green, VCC On will get a Red dot, BOTTOM On will not show the dot but Pin 3 turn On since LTshape is the actual Net connected. This Net is not GND nor VCC, it is N357726.

Where is this dot coming from and why is it not a selectable object ? Why can I not delete it ?

Hi, I am in the middle of a design and had no problem going back and forth between schematics and layout. Now I am getting the error message below. I am using Cadence 17.2.

ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.

The basecopy file generated by the last back-to-front flow not found.

ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.

The basecopy file generated by the last back-to-front flow not found.

Error: CMFBC-1: The schematic and the layout constraints were not synchronized as the changes done since the last sync up could not be reconciled. Syncing the current version of the schematic or layout databases with a previous version would result in this issue. The  constraint difference report is displayed.

Continuing with "changes-only" processing may result in incorrect constraint updates.

Thanks for your input

Claudia

Hello all,

We are designing a backplane and in the design we are using some custom prefixes using the Advance Annotation tool. When annotating the occurances I get the following error:

ERROR(ORDBDLL-1224): The total number of components for prefix J0C exceeds the range supplied for it.
Increase the End value of the range.

Thanks in advance for the help

--Tom

I would like to add these components to the component bank in ORCAD simulation. Even an accessible or free course that explained how to create these components.

When in Constraint Manager, Physical Domain, one can create a new Physical Constraint Class defining specific attributes for a custom rule set. One can then assing this new rule set to a set of nets. To do that it is instructed to create a new Net Class with menu Objects > Create > Net Class. Also on that same menu is available Net Group. Both options create a group that appear in the Constraint Manager Objects Name Column. I have triied both  options and cant really see the difference. 

The Question: What is the difference between creating a Net Class and a Net Group ?  What are the implications ?

Thanks for your help.

Hi everybody,

I've created a symbol with custom pad shapes. Everything looks correct in the symbol editor.

And the 3d view looks correct (upside down to show placement)

But when I try to place it on the pcb the 2 "T" shaped pads aren't in the correct location.

I have the pad shape centered on the pad...

with no offset on the padstack editor.

Does anybody know how to fix this?

Thank you!

Hi,

I have a new customer that uses Allegro Design entry HDL for the schematic and have a few questions.

1. How do you get pin/gate swaps into the symbols in the schematic ?

2. How do you transfer them to the pcb editor ?

3. How do you back annotate the swaps from the pcb editor to the schematic ?

4. How do you stop the export/Import physical from updating the constraints in the pcb file ? 

Hi

i have generated a BOM of my design and one of the parts is showing wrong information than what I specified in the database. I can see that in CIS database that part has been specified a correct information  but when I exported it to bom it shows wrong values.

Hello All,

starting with version 8.1 the contents of the ce_tools directory will no longer
be shipped with Specman. The directory contains some unsupported AE/R&D
ware and has not been updated for several releases (i.e. most of those old
packages don't work with the latest release).
 
Attached is the contents of this directory. Please read the README before
using any of the packages.


Regards,
-hannes

Hi All.

I put together a small Perl script to generate vr_ad register definitions from SPIRIT (IP-XACT) XML.
If you've got not idea what IP-XACT is, have a look here http://www.spiritconsortium.org/, then start pestering your design manager to use it :-)

The script can filter out registers and override R/W access types if needed.

An example XML file is included with the package so that you can play with it, and there's a detailed README.txt as well.

Here's an example of the generated e code:

// Automatically generated from xdmac.xml
// DO NOT EDIT, or your changes may be lost
<'

import vr_ad/e/vr_ad_top;

// Component = XDMAC
// memoryMap = xdmac
extend vr_ad_map_kind : [XDMAC];

// addressBlock = dma_eth
extend vr_ad_reg_file_kind : [DMA_ETH];

extend DMA_ETH vr_ad_reg_file {
  keep size == 20;
  keep addressing_width_in_bytes == 4;
};

// Register = command
// Reset    = 0x00
reg_def COMMAND DMA_ETH 0x0 {
  // Field resv3 = command[31:29]
  reg_fld resv3 : uint(bits:3) : R : 0 : cov ;
  // Field transfer_size = command[28:19]
  reg_fld transfer_size : uint(bits:10) : RW : 0 : cov ;
  // Field dma_transfer_target = command[18:14]
  reg_fld dma_transfer_target : uint(bits:5) : RW : 0 : cov ;
  // Field resv2 = command[13:10]
  reg_fld resv2 : uint(bits:4) : R : 0 : cov ;
  // Field transmit_receive = command[9:9]
  reg_fld transmit_receive : uint(bits:1) : RW : 0 : cov ;
  // Field resv1 = command[8:5]
  reg_fld resv1 : uint(bits:4) : R : 0 : cov ;
  // Field dest_address_enable = command[4:4]
  reg_fld dest_address_enable : uint(bits:1) : RW : 0 : cov ;
  // Field source_address_enable = command[3:3]
  reg_fld source_address_enable : uint(bits:1) : RW : 0 : cov ;
  // Field word_size = command[2:0]
  reg_fld word_size : uint(bits:3) : R : 0 : cov ;
};

// Register = queue_exec
// Reset    = 0x00
reg_def QUEUE_EXEC DMA_ETH 0x10 {
  // Field resv = queue_exec[31:1]
  reg_fld resv : uint(bits:31) : R : 0 : cov ;
  // Field exec = queue_exec[0:0]
  reg_fld exec : uint(bits:1) : RW : 0 : cov ;
};

extend XDMAC vr_ad_map {
  dma_eth : DMA_ETH vr_ad_reg_file;

  post_generate() is also {
    add_with_offset(0x00, dma_eth);
    dma_eth.reset();
  };
}
'>

Any comments, please feed them back to me so I can enhance the script.
Note that this forum forces me to post a .zip file rather than .tgz, please be careful to unpack the file under Linux, not Windows, else the DOS linefeeds will corrupt the Perl and XML files.

Steve

 Hi,

I'm using OVM transaction level tracing in SV. I was wondering if I can have simvision render different types of transactions with different colors e.g. based on a transaction attribute. I know how to do it at signal level using mnemonics but I haven't succeeded doing this at transaction level. Anyone?

 -Joep

As noted in white papers, posts on the Team Specman Blog, and the Specman documentation, IntelliGen is a totally new stimulus generator than the original "Pgen" and, as a result, there is some amount of effort needed to migrate an existing verification environment to fully leverage the power of IntelliGen.  One of the main steps in migrating code is running the linters on your code and adressing the issues highlighted. 

Included below is a simple utility you can include in your environment that allows you to collect some valuable statistics about your code base to allow you to better gauge the amount of work that might be required to migrate from Pgen to IntelliGen.  The ICFS statistics reported are of particular benefit as the utility not only identifies the approximate number of ICFSs in the environment, it also breaks the total number down according to generation contexts (structs/units and gen-on-the-fly statements) allowing you to better focus your migration efforts. 

IMPORTANT: Sometimes a given environment can trigger a large number of IntelliGen linting messages right off the bat.  Don't let this freak you out!  This does not mean that migration will be a long effort as quite often some slight changes to an environment remove a large number of identified issues.  I recently encountered a situation where a simple change to three locations in the environment, removed 500+ ICFSs!

The methods included in the utility can be used to report information on the following:
- Number of e modules
- Number of lines in the environment (including blanks and comments)
- Number and type of IntelliGen Guidelines linting messages
- Number of Inconsistently Connected Field Sets (ICFSs)
- Number of ICFS contexts and how many ICFSs per context
- Number of soft..select overlays found in the envioronment
- Number of Laces identified in the environment

To use the code below, simply load it before/after loading e-code and then
you can execute any of the following methods:

- sys.print_file_stats()             : prints # of lines and files
- sys.print_constraint_stats()   : prints # of constraints in the environment
- sys.print_guideline_stats()    : prints # of each type of linting message
- sys.print_icfs_stats()            : prints # of ICFSs, contexts and #ICFS/context
- sys.print_soft_select_stats() : prints # of soft select overlay issues
- sys.print_lace_stats()           : *Only works for SPMNv6.2s4 and later* prints # of laces identified in the environment

Each of the above calls to methods produces it's own log files (stored in the current working directory) containing relevant information for more detailed analysis.
- file_stats_log.elog : Output of "show modules" command
- constraint_log.elog : Output of the "show constraint" command
- guidelines_log.elog : Output of "gen lint -g" (with notification set to MAX_INT in order to get all warnings)
- icfs_log.elog       : Output of "gen lint -i" command
- soft_select_log.elog: Output of the "gen lint -s" command
- lace_log.elog       : Output of the "show lace" command

Happy generating!

Corey Goss

Just in time for the holidays, inside the posted tar ball is some code to solve 9x9 Sudoku puzzles with the Assertion-Driven Simulation (ADS) capability of Incisive Enterprise Verifier (IEV). Enjoy! Joerg Mueller Solutions Engineer for Team Verify

Hi all 

Good day.

Can anyone tell me whether it is possible to view the signals once it is modified from its previous values without closing the simvision window. If possible kindly let me know the command for it(Linux).

 Is it possible to view the schematic for the code written?? Kindly instruct me.

 Thanks all.

S K S 

Hello,

 I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit for the synthesis but I have a clean design at SOC Encounter, i.e., clean DRC and clean timing reports "no setup/hold violations". However, when I perform simulation using the exported net-list from SOC Encounter together with SDF exported from the same tool, I got a lot of hold violations. Consequently, the design is not funcitioning.

Why and how I can overcome or trobleshoot this issue?

In waiting for your feedback and comments.

Regards.

I want to write a transition coverage on an enumeration. One of the parts of that transition is a queue of the enum. I construct this queue in my constructor. Considering the example below, how would one go about it.

In my coverage bin I can create a range like this A => [queue1Enum[0]:queue1Enum[$]] => [queue2Enum[0]:queue2Enum[$]]. But I only get first and last element then.

typedef enum { red, d_green, d_blue, e_yellow, e_white, e_black } Colors;
 Colors dColors[$];
 Colors eColors[$];
 Lcolors = Colors.first();
 do begin
  if (Lcolors[0].name=='d') begin
   dColors.push_back(Lcolors);
  end
  if (Lcolors[0].name=='e') begin
   eColors.push_back(Lcolors);
  end
 end while(Lcolors != Lcolors.first())

 covergroup cgTest with function sample(Colors c);
   cpTran : coverpoint c{
      bins t[] = (red => dColors =>eColors);   
   }
 endgroup

i had encountered error message like this before. 

but in liberate, i did not find the entry to input section info. 

Hi all,

Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?

Thank you.

Hi ,

     I have designed analog IP in cadence ADE and simulated in spectre. All corner results looks good. when i run monte carlo 1000 runs have high current in 125C two runs. Simulated with same setup in different user, all clean.Need to know what type sampling method used and why its not clean with my setup.

Thanks,

Anbarasu

Hello,

I am running a transient simulation on my circuit and usually my simulation time took me more than a day (The circuit is quite big). I am usually saving specific nodes to decrease the simulation time. My problem is, since it usually took me one day to finish I need to save my trans simulation just in case something bad happens. I am aware that the transient simulation have the options for save/restore. But, when I tried to use it I have some problem. Whenever I restore the save file, it starts where it ends before (expected function) but my data is incomplete. It doesn't save the previous data. Its kind of my data is incomplete. What I did is set the saveperiod and savefile. I hope someone can help me. Thank you!

Regards,

Kiel

Hello,

I am trying to use calcVal for creating a spec condition from a simulated parameter and although this works perfectly fine in corner simulations, I am having some difficulties in Monte-Carlo (and I will explain).

(I have also read "Using calcVal() and its arguments with ADE Assembler" in Resources > Rapid Adoption Kits but couldn't find any relevant information that would help me address the "issue").

In the above example I am performing a MC simulation which has 2 corners of 10 runs each. I would like to get the minimum value of variable "OC_limit_thres" out of those 10 runs and pass it as my upper limit to a range argument for variable "OC_flag_thres", so the CPK can be calculated.

So the range statement should in reality be like this:

range 32m 44.34m (for corner 0)

range 32m 43.14m (for corner 1)

If I open the Detail - Transpose view in the Results tab, the calcVal("OC_limit_thres" "Currlim_TurnOn_C11") is calculated perfectly fine for each run but here I need one single value out of those 10 runs - in this case the minimum - in order for calcVal to evalute on multiple runs of 1 corner.

How can this be done please?

Thank you in advance for your time.

Hi,

I want to convert ircx file(which from TSMC) to ict or emDataFile for Voltus-fi.

I tried many way, but I can not make it.

and I  do not installed QRC.

below is some tools installed my server. 

IC617-64b.500.21 is used.

Hi, 

I want my layout verified by Quantus QRC. But, I can't find the tool bar on the option list ( as show in the picture)

I have tried to install EXT182 and configured it with iscape already, and also make some path settings on .bashrc, .cshrc. But, when I re-source .cshrc and run virtuoso again, I just can't find the toolbar. 

If you have some methods, please let me know.

Thanks a lot!

Appreciated

My virtuoso version is: ICADV12.3

Hi,

I am trying to characterize a D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). This is a positive edge triggered D flip flop based on true-single-phase clocking scheme. After the characterization, the measurements reported for hold constraint arcs seem to deviate significantly from its (spectre) spice simulation.

The constraint and the power settings to the liberate are as follows : 

# -------------------------------------------- Timing Constraints --------------------------------------------------------------------------------
### Input waveform ###
set_var predriver_waveform 2;# 2=use pre-driver waveform
### Capacitance ###
set_var min_capacitance_for_outputs 1;# write min_capacitance attribute for output pins
### Timing ###
set_var force_condition 4
### Constraint ###
set_var constraint_info 2
#set_var constraint_search_time_abstol 1e-12 ;# 1ps resolution for bisection search
set_var nochange_mode 1 ;# enable nochange_* constraint characterization
### min_pulse_width ###
set_var conditional_mpw 0
set_var constraint_combinational 2

#---------------------------------------------- CCS Settings ----------------------------------------------------------------------------------------
set_var ccsn_include_passgate_attr 1
set_var ccsn_model_related_node_attr 1
set_var write_library_is_unbuffered 1

set_var ccsp_min_pts 15 ;# CCSP accuracy
set_var ccsp_rel_tol 0.01 ;# CCSP accuracy
set_var ccsp_table_reduction 0 ;# CCSP accuracy
set_var ccsp_tail_tol 0.02 ;# CCSP accuracy
set_var ccsp_related_pin_mode 2 ;# use 3 for multiple input switching scnarios and Voltus only libraries

#----------------------------------------------- Power ---------------------------------------------------------------------------------------------------
### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

#set_var power_subtract_leakage 4 ;# use 4 for cells with exhaustive leakage states.
set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector [expr 2**10]
#--------------------------------------------------------------------------------------------------------------------------------------------------------------

I specifically used set_var constraint_combinational 2 in the settings, in case the Bisection pass/fail mode fails to capture the constraints. In my spice simulation, the hold_rise (D=1, CLK=R, Q=R) arc at-least requires ~250 ps for minimum CLK/D slew combination (for the  by default smallest capacitive load as per Liberate)  while Liberate reports only ~30 ps. The define_cell template to this flip flop is pretty generic, which does not have any user specified arcs. So which settings most likely affecting the constraint measurements in Liberate and how can I debug this issue ?

Thanks

Anuradha

Dear All,
When I want to start simulation with spectre the error says:
Fatal error: Illegal library definition found in netlist
I set the model file correctly, but I don't know why it errors!
I opened the ADE>>Setup>>Model library
and I tried to modify the path of models file (SCS files)
It gives me "Illegal library definition found in netlist"
Thanks.

Hello,

I am using ultrasim Version 18.1.0.314.isr5  64bit 03/26/2019 06:33 (csvcm20c-2).

When I run my netlist, ultrasim is blocked in the first DC stage and takes forever. Then it will fail or never progress. I am using a 22nm BSIMBULK model. I tried to tune different accuracy and convergence aids options but noting works.

 When I run the same netlist with spectre it works fine with no problem.

Also, If I use another model (not BULKSIM), ultrasim will work and converge with no problem.

My first feeling is that ultrasim has a problem with using BSIMBULK model.

Could you please advice,

Thank you,

Kotb

I put some stimulus in the simulation file section : 

_vpd_data_enb (pu_data_enb 0) vsource wave=[0 0 1n 0 1.015n vcchbm 3n vcchbm] dc=0 type=pwl
_vpu_data_enb (pd_data_enb 0) vsource dc=pu_enb type=dc

I get the following error. 

ERROR (OSSGLD-18): The command character after '[' in the NLP expression '[0 0 1n 0 1.015n vcchbm 3n vcchbm] dc=0 type=pwl

' is not a valid

character. The command character is the first character after '[' in the NLP

expression. It must be '?', '!', '#', '$', 'n', '@', '.', '~' or '+'. Enter a

valid character as the command character.

si: simin did not complete successfully.

I dont see anything wrong with the stimulus syntax

Hi,

This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). 

When the "define_arcs" are not explicitly specified in the settings for the circuit (but the input/outputs are indeed correct in define_cell), the inside view seems to probe an internal node (i.e. master latch output)  for constraint measurements instead of the Q output of the flip flop. So to force the tool to probe Q output I added following coder in constraint arcs :

# constraint arcs from CK => D
define_arc
-type hold
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type hold
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

with -probe Q liberate identifies Q as the output, but uses Glitch-Peak criteria instead of delay degradation method. So what could be the exact reason for this unintended behavior ? In my external (spectre) spice simulation, the Flip-Flop works well and it does not show any issues in the output delay degradation when the input sweeps.

Thanks

Anuradha

Before I ask this, I am aware that I can output an s-parameter file from an SP analysis.

I'm wondering if there is a simple way of creating an s-parameter model of a component.

As an example, if I have an S-parameter model that has 200 ports and 150 of those ports are to be connected to passive components and the remaining 50 ports are to be connected to active components, I can simplify the model by connecting the 150 passive components, running an SP analysis, and generating a 50 port S-parameter file.

The problem is that this is cumbersome. You've got to wire up 50 PORT components and then after generating the s50p file, create a new cellview with an nport component and connect the 50 ports with 50 new pins.

Wiring up all of those port components takes quite a lot of time to do, especially as the "choosing analyses" form adds arrays in reverse (e.g. if you click on an array of PORT components called X<0:2> it will add X<2>, X<1>, X<0> instead of in ascending order) so you have to add all of them to the analyses form manually.

Is any way of taking a schematic and running some magic "generate S-Parameter cellview from schematic cellview"  function that automates the whole process?

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors. (read more)

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.(read more)

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.(read more)

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning! (read more)

Hi Everyone,

Many of you would have heard about the Cadence Stylus Common UI and are wondering what it is and what the advantages might be to use it versus legacy UI.

The webinar answers the following questions:

• Why did Cadence develop Stylus UI and what is Stylus Common UI?
• How does someone invoke and use the Stylus Common UI?
• What are some of the important and useful features of the Stylus Common UI?
• What are the key ways in which the Stylus Common UI is different from the default UI?​

If you want to learn more about Stylus UI in the context of implementation, view the 45-minute recorded webinar on the Cadence support site.

Related Resource

Innovus Block Implementation with Stylus Common UI

Vinita Nelson

The Cadence® Genus  Synthesis Solution, Innovus  Implementation System, and Tempus  Timing Signoff Solution have a lot of shared functionality, but in the past, the separate legacy user interfaces (UIs) created a lot of differences.

A new common user interface that the Genus solution shares with the Innovus and Tempus solutions streamlines flow development and simplifies usability across the complete Cadence digital flow. The Stylus Common UI provides a next-generation synthesis-to-signoff flow with unified database access, MMMC timing configuration and reporting, and low-power design initialization.

This webinar answers the following questions:

• What is the Stylus Common UI and why did Cadence develop it?
• How does someone invoke and use the Stylus Common UI?
• What are some of the important and useful features of the Stylus Common UI?
• What are key ways the Stylus Common UI is different from the Legacy UI?

If you want to learn more about Stylus UI in the context of Genus Synthesis Solution, refer to 45-minute recorded webinar on https://support.cadence.com (Cadence login required).

Video Title: Webinar: Genus Synthesis Solution—Introduction to the Stylus Common UI (Video)

Direct Link: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009MoGIUA0&pageName=ArticleContent

Related Resources

If interested in the full course, including lab content, please contact your Cadence representative or email a request to training_enroll@cadence.com. You can also enroll in the course on http://learning.cadence.com.​

Enhance the Genus Synthesis experience with videos: Genus Synthesis Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!!

But:

• How to do it?
• Is there any specific switch required?
• What is the flow/script when Joules is used from within Genus?
• Are all the Joules commands supported?

To answer to all these questions is just a click away in the form of video on “Genus-Joules Integration”; refer it on https://support.cadence.com (Cadence login required).

Video Title: Genus-Joules Integration (Video)

Direct Link: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V0000091CnXUAU&pageName=ArticleContent

Related Resources

Enhance the Genus Synthesis experience with videos: Genus Synthesis Solution: Video Library

Enhance the Joules experience with videos: Joules RTL Power Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?

• Is there any scope to improve power consumption of my design?
• What is the best-case power?
• Pin-point hot spots in my design?
• How to recover wasted power?

And here is the solution in form of Joules RTL Power Exploration. Joules’ framework for power exploration and power implementation/recovery is stimulus based, where analysis is done by Joules and is explored/implemented by user.

Power Exploration capabilities include:

• Efficiency metrics
• Pin point RTL location
• Cross probe to stim
• Centralize all power data

 Do you want to explore more? What is the flow? What commands can be used?

There is a ONE-STOP solution to all these queries in the form of videos on Joules Power Exploration features on https://support.cadence.com (Cadence login required).

Video Links:

How to Analyze Ideal Power Using Joules RTL Power Solution GUI? (Video)

What is Ideal Power Analysis Flow in Joules RTL Power Solution? (Video)

How to Apply Observability Don’t Care (ODC) Technique in Joules? (Video)

How to Debug Wasted Power Using Ideal Power Analyzer Window in Joules GUI? (Video)

Related Resources

Enhance the Joules experience with videos: Joules RTL Power Solution: Video Library

For any questions, general feedback, or future blog topic suggestions, please leave a comment. 

A recap of the blogs published in the Library Characterization Tidbits blog series.(read more)