b About using Liberate to create .lib for a cell with two separate outputs. By feedproxy.google.com Published On :: Wed, 18 Dec 2019 02:56:41 GMT Hello, my name is Hsukang. I want to use Liberate to create a .lib file for the following circuit. This is a scan FF with two separate outputs. The question is that no matter how I described its function, the synthesis tool said its a manformed scan FF. Has anyone ever encountered anything like this?How should I describe the function correctly?I found that almost standard flip-flop cells are with only one output Q or have Qn at the same time. Does Liberate support scan flip-flop cells with two separate outputs ? Thanks. Full Article
b What's the difference between Cadence PCB Editor and Cadence Allegro? By feedproxy.google.com Published On :: Thu, 02 Jan 2020 09:15:36 GMT Are they basically the same thing? I am trying to get as much experience with Allegro since a lot of jobs I am looking at right now are asking for Cadence Allegro experience (I wish they asked for Altium experience...). I currently have access to PCB Editor, but I don't want to commit to learning Editor if Allegro is completely different. Also walmart one, are the Cadence Allegro courses worth it? I won't be paying for it and if it's worth it, I figure I might as well use the opportunity to say I know how to use two complex CAD tools. Full Article
b Cadence SoC Encounter 8.1 - Keyboard is not working By feedproxy.google.com Published On :: Tue, 21 Jan 2020 21:45:03 GMT Hello, I am using Encounter 8.1. My mouse is working fine, but my keyboard is not working well in Encounter. I can type in some boxes, but in many boxes I cannot type. The binding key is also not responding. How do I fix this issue? Thanks. Full Article
b About modus design constraints By feedproxy.google.com Published On :: Fri, 13 Mar 2020 12:09:02 GMT Hi! In my design, there is an one hold violation on scan path, test data is corrupted during scan cycles (when i run verilog simulation of test vectors). I created constraint 'falsepath' to 'TI' input of violated flop and load it into Modus, but this does not have effect. Can enyone explain to me, does 'falsepath' constraint affects scan path (from Q to TI/SI input, i.e. during SCAN procedure) or this constraint is only for functional mode (ie affects TEST cycle only - to 'D' input)? I hope resolve this problem this by using some modus design constraints or any other method. Full Article
b Quantus Qrc Extraction of a block By feedproxy.google.com Published On :: Fri, 27 Mar 2020 11:36:28 GMT I have completed physical design of a block in innovus. I want to extract rc of that block using quantus . It will be very helpful if you give step by step procedure and command to run quantus to extract rc of that block. Full Article
b Interaction between Innovus and Virtuoso through OA database By feedproxy.google.com Published On :: Mon, 06 Apr 2020 14:32:45 GMT Hello,I created a floorplan view in Virtuoso ( it contains pins and blockages). I am trying to run PnR in Innovus for floorplan created in Virtuoso. I used set vars(oa_fp) "Library_name cell_name view_name" to read view from virtuoso. I am able to see pins in Innovus but not the blockages. Can i know how do i get the blockages created in virtuoso to Innovus. Regards,Amuu Full Article
b Mouse wheel and [i][o] button doesn't zoom By feedproxy.google.com Published On :: Tue, 16 Jul 2019 02:49:43 GMT Hi, I recently encountered a probelm where scrolling with the mouse wheel and [i][o] button does not zoom in or out both in "Allegro orcad capture CIS 17.2.2016 " . When I scroll the mouse wheel or [i][o] button, nothing is done. The thing is that it worked fine until yesterday. Anyone has an idea? Thanks, Dung. Full Article
b allegro 16.6 pcb export parameters error By feedproxy.google.com Published On :: Tue, 29 Oct 2019 12:11:35 GMT hi all, what wrong with the error "param_write.log does not exist" when i export parameters in allegro 16.6 pcb board. someone can provide suggestions, thanks. best regards. Full Article
b Force cell equivalence between same-footprint and same-functionality hard-macros in Conformal LEC By feedproxy.google.com Published On :: Thu, 14 Nov 2019 19:13:48 GMT For a netlist vs. netlist LEC flow we have to solve the following problem: - in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A - MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow) - at top-level (full-chip) we instantiate this array of all-identical macros - in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B - MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro - MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro - when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC - the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B . Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes . Is this flow supported ? Thanks in advance Luca Full Article
b How to dump waveform, fsdb in SimVision? By feedproxy.google.com Published On :: Thu, 09 Jan 2020 02:30:31 GMT As title, How to dump waveform, fsdb in SimVision? (Simulation Analysis Environment SimVision(64) 18.09-s001)Please help. Thanks. Full Article
b About SDF file after synthesis in Genus Tool By feedproxy.google.com Published On :: Thu, 20 Feb 2020 09:47:17 GMT hello sir this is Ganesh from NIT Hamirpur pursuing MTech in VLSI. I have doubt regarding SDF i'm using genus tool for synthesis & after synthesis when i'm generating SDF it is giving delays by default for maximum values but i want all the delays like minimum:Typical:Maximum how can i do this. Is there any provision to set PVT values manually for SDF generation so that i can get all the delay values. Full Article
b About SDF file By feedproxy.google.com Published On :: Thu, 27 Feb 2020 13:56:14 GMT How to get minimum: typical: maximum values in SDF I am using Genus synthesis tool there default setting is for max value. But I want all the values please guide me. Full Article
b About SDC file By feedproxy.google.com Published On :: Thu, 27 Feb 2020 13:58:58 GMT Which things we have to mention in SDC for combinational design? How to create virtual clock? Full Article
b SpectreRF Tutorials and Appnotes... Shhhh... We Have a NEW Best Kept Secret! By feedproxy.google.com Published On :: Tue, 17 Dec 2013 15:23:00 GMT It's been a while since you've heard from me...it has been a busy year for sure. One of the reasons I've been so quiet is that I was part of a team working diligently on our latest best kept secret: The MMSIM 12.1.1/MMSIM 13.1 Documentation has...(read more) Full Article RF Simulation wireless Wilsey tutorial spectreRF Appnote RF design transmission lines harmonic balance SpectreRF tutorials
b Have You Tried the New Transmission Line Library (rfTlineLib)? By feedproxy.google.com Published On :: Fri, 03 Jan 2014 13:36:00 GMT Happy New Year! Have you tried the new Transmission Line Library (rfTlineLib) yet? In case you missed it, rfTlineLib was introduced in IC 6.1.6 ISR1 plus MMSIM 12.1.1 -or- MMSIM13.1. You may wonder....Why should I use the new rfTlineLib ? Well...(read more) Full Article RF RF Simulation transmission line RFIC Wilsey Spectre RF rfTlineLib spectreRF SpectreRF tutorials
b New Memory Estimator Helps Determine Amount of Memory Required for Large Harmonic Balance Simulations By feedproxy.google.com Published On :: Thu, 24 Apr 2014 14:24:00 GMT Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an estimate before submitting jobs." The answer...(read more) Full Article HB Spectre RF MMSIM spectreRF harmonic balance memory estimator
b Broadband SPICE -- New Tool for S-Parameter Simulation in Spectre RF By feedproxy.google.com Published On :: Thu, 24 Apr 2014 15:18:00 GMT Hi All, Here's another great new feature that I've found very helpful... Broadband SPICE is a new tool for S-parameter simulation in Spectre RF. In the MMSIM13.1.1 ( MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...(read more) Full Article nport Spectre RF broadband SPICE nport settings Spectre s parameter simulation
b Distortion Summary in New CDNLive YouTube Video and at IEEE IMS2014 Next Week! By feedproxy.google.com Published On :: Fri, 30 May 2014 22:12:00 GMT Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC, discusses an aggressive...(read more) Full Article Wilsey Spectre RF spectreRF RF design harmonic balance Distortion
b Noise Simulation in Spectre RF Using Improved Pnoise/Hbnoise and Direct Plot Form Options By feedproxy.google.com Published On :: Wed, 19 Apr 2017 06:09:58 GMT Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form has also been enhanced and is much easy to use....(read more) Full Article HBnoise HB Spectre RF pnoise noise simulation Virtuoso RF design pss
b 7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters in a Time Domain Simulator By feedproxy.google.com Published On :: Tue, 16 May 2017 20:11:02 GMT Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic steady state) simulator has been and continues to be a challenge for many analog and RF designers. I'm often asked: What is required in order to achieve accurate...(read more) Full Article S-parameter Spectre RF Spectre International Microwave Symposium
b Link to: 7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters in a Time Domain Simulator By feedproxy.google.com Published On :: Thu, 06 Jul 2017 22:18:34 GMT Hi All, If you were unable to attend IMS 2017 in June 2017, the IMS MicroApp “7 Habits of Highly Successful S-Parameters” is on our Cadence website. On Cadence Online Support , the in-depth AppNote is here: 20466646 . Best regards, Tawna...(read more) Full Article nport analog/RF APS S-parameter Virtuoso Spectre Spectre RF broadband SPICE nport settings RF spectre spectreRF spectreRF s parameter simulation
b Triple Beat Analysis: What, Why & How? By feedproxy.google.com Published On :: Thu, 30 Nov 2017 09:04:00 GMT The Triple Beat analysis is similar to Rapid IP2/IP3 analysis except that it uses three tones instead of two. It is used in cases where two closely-spaced small-signal inputs from a transmitter leak in to the receiver along with an intended small-signal RF input signal. (read more) Full Article Virtuoso ADE Virtuoso Spectre RF design
b Multiple commands using ipcBeginProcess By feedproxy.google.com Published On :: Mon, 27 Apr 2020 14:37:17 GMT Hi, I am trying to use "sed -e 's " from SKILL code to edit unix file "FileA", to replace 3 words in the 2nd line. How to run below multiple commands using ipcBeginProcess, Should I use ipcWait or ipcCloseProcess ? Using && to combine , will that work as I have to work serially on each command. ? With below code only the first command gets executed. Please advise. FileA="/user/tmp/text1.txt" sprintf(Command1 "sed -e '2s/%s/%s/g' %s > %s" comment1 get(form concat("dComment" RDWn))->value FileA FileA) cid = ipcBeginProcess(Command1) sprintf(Command2 "sed -e '2s/%s/%s/g' %s > %s" Time getCurrentTime() FileA FileA) cid1 = ipcBeginProcess(Command2) sprintf(Command3 "sed -e '2s/%s/%s/g' %s > %s" comment2 get(form concat("Duser" RDWn))->value FileA FileA) cid2 = ipcBeginProcess(Command3) Thanks, Ajay Full Article
b Not able to close a form By feedproxy.google.com Published On :: Tue, 28 Apr 2020 11:13:08 GMT Hi, I am trying to write a skill code where it takes form inputs by default and just displays tree directly. i have written below code, procedure( create_tree() let(() leHiTree() leTreeForm->treeOption->value="Current to user level" leTreeForm->userLevel->value= 31 ipcSleep(1) hiFormDone(leTreeForm) )) the form takes in values but it is not closing. tried with regtimer in place of ipc sleep, didn't work. how to close form(should be same as pressing OK)? Thanks in advance, vishwas Full Article
b SKILL to Identify a LABEL over an Instance By feedproxy.google.com Published On :: Wed, 29 Apr 2020 18:32:44 GMT Hello, I am in a need of a skill program to find all instances of a specific cell (Including Mosaics), throughout the hierarchy. The program should print the instance's name, xy coordinates at the top level, and extract a label name that is dropped on top of it. In case there is no label on top of the found instance, the program should print "No Label Found" in the report text file. This program aims to map PADs cells within top level. I am using the below Cadence's solution to find instances and it works well. The missing feature is to identify LABELs that are on top of the found instances. I tried to use dbGetOverlap() function, within the below code, in few setups but it seems to fail to identify the existence of labels on top of the found instances. For example: overlapLabel=dbGetTrueOverlaps(cv cadr(instBox) list("M1" "text")) I am interested to add to the Cadence's solution below some code in order to identify labels on top of the found instances. Any tip would be greatly appreciated. Thanks, Danny -------------------------------------------------------- procedure(HilightCellByArea(lib cell level) let((cv instList rect instBox) ;; Deleting old highlights.To prevent uncomment the below line when(boundp('hset) hset->enable=nil) cv=geGetWindowCellView() rect=enterBox( ?prompts list("Enter the first corner of your box." "Enter the last corner of your box.") ) instList=dbGetOverlaps(cv rect nil level nil) ;; It uses hilite layer packet. You can change it to y0-y9 layer or any other hilite lpp ;;hset = geCreateHilightSet(cv list("y0" "drawing") nil) ;;hset = geCreateHilightSet(cv list("hilite" "drawing1") nil) hset = geCreateHilightSet(cv list("hilite" "drawing") nil) hset->enable = t foreach(instId instList if(listp(instId) then instBox=CCSTransformBBox(instId) instId=car(instBox) when(instId~>libName==lib && instId~>cellName==cell geAddHilightRectangle(hset cadr(instBox)) fprintf(myFileId, "Highlighted the %L instance %L of hierarchy at:%L " cell buildString(append1(caddr(instBox)~>name instId~>name) "/") cadr(instBox) foundFlag=t) ) else when(instId~>libName==lib && instId~>cellName==cell geAddHilightFig(hset instId) fprintf(myFileId, "Highlighted the %L instance %L of top cell at:%L " cell instId~>name instId~>bBox) foundFlag=t ) );if listp ) ;foreach t ) ;let ) ;procedure procedure(CCSTransformBBox(inst) let((flatList y location) while(listp(inst) y = car(inst) flatList = append(flatList list(y)) inst = cadr(inst) ; next inst );while location=dbTransformBBox(inst~>bBox dbGetHierPathTransform(list(flatList inst))) list(inst location flatList) );let );procedure Full Article
b How to get test name from test session object? By feedproxy.google.com Published On :: Thu, 30 Apr 2020 07:04:23 GMT Hi, I have a test session object that I am getting like this: maeTstSession=maeGetTestSession(test ?session session) Is it possible to get the test name from this object? I am asking because this object passed to several levels of functions and I don't want to pass an additional argument with the test name Full Article
b customizing status toolbar By feedproxy.google.com Published On :: Thu, 30 Apr 2020 07:14:35 GMT Hi, I would like to add items like length of selected metal or area also in status tool bar. I have tried below option but I am getting warning as shown below. Could you please give suggestions. envGetVal("layout" "statusToolbarFields") *WARNING* envGetVal: Could not find variable 'statusToolbarFields' in tool[.partition] 'layout' Regards, Varsha Full Article
b hiCreateAppForm with scrollbars and attachmentList By feedproxy.google.com Published On :: Thu, 30 Apr 2020 21:20:36 GMT Hello, I have created an appForm with the following attachmentList and size: ?attachmentList list(hicLeftPositionSet | hicRightPositionSet ; field 1 hicLeftPositionSet | hicRightPositionSet ; field 2etc. ?initialSize 800:800 ?minSize 800:800 ?maxSize 1600:800 If I reduce the minimum y-size (?minSize 800:200), scrollbars are not inserted, unless I remove the attachmentList constraints. Is it possible to have both scrollbars and "hicLeftPositionSet | hicRightPositionSet"? Thank you, Best regards, Aldo Full Article
b Get schematic to layout bound stdcells for array By feedproxy.google.com Published On :: Fri, 01 May 2020 00:29:26 GMT I can get the bound stdcells using bndGetBoundObjects, but not get what each individual stdcell corresponds in layout. Is there a way to get the layout bound stdcells of an array schematic symbol if the layout stdcell name do or do not match the symbol naming? Once the schematic array stdcells are bound to the layout stdcells, how to get the correct terminal term~>name and net~>name? Example of a schematic symbol and layout stdcell: Schematic INV<0:2> instTerms~>terms~>name = ("vss" "vdd" "A" "Y") instTerms~>net~>name = ("<*3>vss" "<*3>vdd" "in<0:2>" "nand2A,nand3B,nor2B") Layout ( I know it is bad practice, but it happens ) stdcell1 instTerms~>terms~>name = ("vss" "vdd" "A" "Y") instTerms~>net~>name = ("vss" "vdd" "in<0>" "nand2A") I23 instTerms~>terms~>name = ("vss" "vdd" "A" "Y") instTerms~>net~>name = ("vss" "vdd" "in<1>" "nand3B") INV(2) instTerms~>terms~>name = ("vss" "vdd" "A" "Y") instTerms~>net~>name = ("vss" "vdd" "in<2>" "nor2B") Paul Full Article
b Merge BBOX in hierarchical layout By feedproxy.google.com Published On :: Fri, 01 May 2020 05:01:07 GMT Hi Team, Problem Statement:In hierarchical layout, I want to get BBOX of particular layer without actually flattening the layout. Description:The layer can be at any hierarchical depth i.e both from PCELL or shapes but at top level if they are overlapping then I want the merged BBOX. Now, I am able to get BBOX of all the shapes present at different hierarchy.But i finding issue in merging BBOX. Please can help me on the same issue as I require efficient way to merge the BBOX because list containing the BBOX is huge. Thanks in advance. Regrads, Prasanna Full Article
b How can I make a SKILL procedure not callable? By feedproxy.google.com Published On :: Fri, 01 May 2020 19:57:35 GMT Inside the scope of isCallable there is code which I don't want to be executed. The procedure named in isCallable to-day is callable. I want to make that procedure so it cannot be called. How do I do that? I can't change the isCallable line or the scope. I want to change its behavior by making sure that the procedure does not exist (obviously this would be done before the code is executed). Full Article
b Select all members of a constraint with SKILL By feedproxy.google.com Published On :: Mon, 04 May 2020 08:54:21 GMT I want to select a constraint, and then run a SKILL command that returns a list with the members of that constraint. Is this possible? Thx, Full Article
b Displaying contents of a modeless dialog box during execution of a SKILL script By feedproxy.google.com Published On :: Tue, 05 May 2020 00:47:02 GMT I have a modeless informational dialog box defined at the beginning of a SKILL script, but its contents don't display until the script finishes. How do you get a modeless dialog box contents to display while a SKILL script is running? procedure(myproc() prog((myvars) hiDisplayAppDBox() ; opens blank dialog box - no dboxText contents show until script completes! ....rest of SKILL code in script...launches child processes );prog );proc Full Article
b Skill code to disable all callbacks By feedproxy.google.com Published On :: Wed, 06 May 2020 11:40:02 GMT Can anybody assist with a Skill code /function to disable all callbacks Full Article
b Choices in radio field to be displayed in two rows By feedproxy.google.com Published On :: Fri, 08 May 2020 16:28:25 GMT Hi, I am trying add multiple choices to my radio field in cdf parameters. when i see the select the instance and try editing the Instance properties I can not view them in a single window. Instead i get a vertical sliding bar. Is there a way to display them in multiple rows? -Haareeth Full Article
b ddDeleteObj() and its warnings By feedproxy.google.com Published On :: Sat, 09 May 2020 13:54:06 GMT Hello, After deleting cells using the following loop: foreach(cellId ddGetObj(libName)~>cells ddDeleteObj(cellId) ) the following warnings are printed in the CIW: *WARNING* (SCH-2162): "... symbol" has been updated since "... schematic" was last saved. Validate that the schematic is correct and run Check and Save to suppress this warning.*WARNING* (DB-270337): dbGetInstHeaderMaster: Failed to open cellview '...' from library '...' in read-only mode because the cellview does not exist. This cellview was instantiated in cellview '...' of library '...'. Ensure that the cellview exists in the library. Is it possible to turn them off? Thank you Best regards, Aldo Full Article
b When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC to Enable Machine Learning By feedproxy.google.com Published On :: Fri, 29 Sep 2017 19:59:59 GMT As the stakes for winning server segment market share grow ever higher an increasing number of companies are seeking to grasp the latest Holy Grail of multi-chip coherence. The approach promises to better enable applications such as machine learning...(read more) Full Article SoC verification perspec system verifier Accellera pss portable stimulus
b Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AMBA5 By feedproxy.google.com Published On :: Thu, 12 Oct 2017 22:05:00 GMT It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we...(read more) Full Article iwb interconnect amba5 Interconnect Workbench Palladium Performance Analysis AMBA CoreLink xcelium ARM
b Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey By feedproxy.google.com Published On :: Fri, 01 Dec 2017 22:48:00 GMT It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com. There were 33 user responses in favor of Perspec as the #1 tool, and dr...(read more) Full Article
b Portable Stimulus User Gives Perspec PSS Technology Nearly Perfect Review By feedproxy.google.com Published On :: Mon, 08 Jan 2018 09:01:00 GMT It’s always good to hear what real users think of products. Here is a very detailed review (~4000 words) by an Anonymous user, nick named Ant-Man (from the movie). Overall it’s a very strong endorsement of Perspec, and summarize...(read more) Full Article
b Cadence Collaborates with Test & Verification Solutions on Portable Stimulus By feedproxy.google.com Published On :: Thu, 18 Jan 2018 15:01:00 GMT The Cadence® Connections® Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. The program members help customer accelerate the adoption of new...(read more) Full Article CDNLive Test DVcon pss verification
b Preparing Accellera Portable Stimulus Standard for Ratification By feedproxy.google.com Published On :: Tue, 13 Mar 2018 15:35:00 GMT The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process forward towards ratification. While we can't predict exactly when it will be ratified, the goal is now more clearly in sight! Cadence booth was busy with a lo...(read more) Full Article pswg Perspec perspec system verifier pss portable stimulus
b What’s Hot in Verification at this Year’s CDNLive? It’s Portable Stimulus Again! By feedproxy.google.com Published On :: Tue, 27 Mar 2018 21:23:00 GMT CDNLive is a user conference, and verification is one of the largest categories of content with multiple tracks covering multiple days. Portable stimulus is one of the hottest new areas in verification, and continues to be popular in all venues. At l...(read more) Full Article CDNLive Perspec pss portable stimulus
b AMIQ and Cadence demonstrate Accellera PSS v1.0 interoperability By feedproxy.google.com Published On :: Thu, 12 Jul 2018 00:04:00 GMT There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced ...(read more) Full Article Perspec perspec system verifier AMIQ Accellera pss portable stimulus
b Perspec Portable Stimulus Hands-On Workshop at DAC 2018 By feedproxy.google.com Published On :: Fri, 20 Jul 2018 22:54:00 GMT Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...(read more) Full Article Perspec AMIQ pss portable stimulus
b Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application By feedproxy.google.com Published On :: Thu, 16 Aug 2018 22:17:00 GMT Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and...(read more) Full Article
b DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety, Security and More By feedproxy.google.com Published On :: Wed, 29 May 2019 23:45:00 GMT Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more) Full Article security 5G DAC DAC2019 prototyping palladium z1 Safety tortuga logic Protium Emulation ARM AI
b Generating IBIS models in cadence virtuoso By feedproxy.google.com Published On :: Wed, 04 Sep 2019 20:25:36 GMT I'm trying to generate IBIS models for the parts that I'm designing. I'm designing using CADENCE Virtuoso. I'm wondering if there is a tutorial for generating IBIS models in CADENCE Virtuoso. Please pardon me if my question is broad. Full Article
b Visibility to "component value" property in Edit/Properties dialog? By feedproxy.google.com Published On :: Thu, 12 Sep 2019 18:59:09 GMT Hi, I want to add values to components in my SiP design such as 1nF or 15nH. There is already in existence a COMP_VALUE property reserved for this as shown during BOM generation. This property is not visible under the Edit/Properties dialog for component or symbol find filters. We have already created user properties called COMP_MFG and COMP_MFG_PN that it editable at a component level. When we try to add COMP_VALUE it is reported as a reserved name in Cadence but this name is not listed in the properties dialog. Is there a way to turn on the visibility and editablility of this or other hidden reserved Cadence property names? How can I assign a string value to the COMP_VALUE property? Thanks Full Article
b About Degassing Hole By feedproxy.google.com Published On :: Thu, 05 Dec 2019 02:08:06 GMT I use "Degassing" function in APD. It provides the options "Even Layers" and "Odd Layers". My first question is that is there any additional setting to choose the specific layer? The second question is that is there any way to select a range to place degassing hoe? I don't want to place holes at the whole layer. Thanks! Full Article