A recap of the blogs published in the Library Characterization Tidbits blog series.(read more)

Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.(read more)

Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.

As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital teams that have rapidly evolved design and verification practices over the past decade. Well, I claim that is about to change. 2015 will be a watershed year for many more design teams because of the following factors:

• 85% of designs are mixed signal, and it is going to stay that way (there is no turning back)
• Advanced node drives new techniques, but they will be applied on all nodes
• Equilibrium of mixed-signal designs being challenged, complexity raises risk level
• Tipping point signs are evident and pervasive, things are going to change
• The convergence of “big A” and “big D” demands true mixed-signal practices

Reason 1: Mixed-signal is dominant

To begin the examination of what is going to change and why, let’s start with what is not changing. IBS reports that mixed signal accounts for over 85% of chip design starts in 2014, and that percentage will rise, and hold steady at 85% in the coming years. It is a mixed-signal world and there is no turning back!

Figure 1. IBS: Mixed-signal design starts as percent of total

The foundational nature of mixed-signal designs in the semiconductor industry is well established. The reason it is exciting is that a stable foundation provides a platform for driving change. (It’s hard to drive on crumbling infrastructure.  If you’re from California, you know what I mean, between the potholes on the highways and the earthquakes and everything.)

Reason 2: Innovation in many directions, mostly mixed-signal applications

While the challenges being felt at the advanced nodes, such as double patterning and adoption of FinFET devices, have slowed some from following onto to nodes past 28nm, innovation has just turned in different directions. Applications for Internet of Things, automotive, and medical all have strong mixed-signal elements in their semiconductor content value proposition. What is critical to recognize is that many of the design techniques that were initially driven by advanced-node programs have merit across the spectrum of active semiconductor process technologies. For example, digitally controlled, calibrated, and compensated analog IP, along with power-reducing mutli-supply domains, power shut-off, and state retention are being applied in many programs on “legacy” nodes.

Another graph from IBS shows that the design starts at 45nm and below will continue to grow at a healthy pace.  The data also shows that nodes from 65nm and larger will continue to comprise a strong majority of the overall starts. 

Figure 2.  IBS: Design starts per process node

TSMC made a comprehensive announcement in September related to “wearables” and the Internet of Things. From their press release:

TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.

Compared with their previous low-power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life—by 2X to 10X—when much smaller batteries are demanded in IoT/wearable applications.

The focus on power is quite evident and this means that all of the power management and reduction techniques used in advanced node designs will be coming to legacy nodes soon.

Integration and miniaturization are being pursued from the system-level in, as well as from the process side. Techniques for power reduction and system energy efficiency are central to innovations under way.  For mixed-signal program teams, this means there is an added dimension of complexity in the verification task. If this dimension is not methodologically addressed, the level of risk adds a new dimension as well.

Reason 3: Trends are pushing the limits of established design practices

Risk is the bane of every engineer, but without risk there is no progress. And, sometimes the amount of risk is not something that can be controlled. Figure 3 shows some of the forces at work that cause design teams to undertake more risk than they would ideally like. With price and form factor as primary value elements in many growing markets, integration of analog front-end (AFE) with digital processing is becoming commonplace.  

Figure 3.  Trends pushing mixed-signal out of equilibrium

The move to the sweet spot of manufacturing at 28nm enables more integration, while providing excellent power and performance parameters with the best cost per transistor. Variation becomes great and harder to control. For analog design, this means more digital assistance for calibration and compensation. For greatest flexibility and resiliency, many will opt for embedding a microcontroller to perform the analog control functions in software. Finally, the first wave of leaders have already crossed the methodology bridge into true mixed-signal design and verification; those who do not follow are destined to fall farther behind.

Reason 4: The tipping point accelerants are catching fire

The factors cited in Reason 3 all have a technical grounding that serves to create pain in the chip-development process. The more factors that are present, the harder it is to ignore the pain and get the treatment relief  afforded by adopting known best practices for truly mixed-signal design (versus divide and conquer along analog and digital lines design).

In the past design performance was measured in MHz with simple static timing and power analysis. Design flows were conveniently partitioned, literally and figuratively, along analog and digital boundaries. Today, however, there are gigahertz digital signals that interact at the package and board level in analog-like ways. New, dynamic power analysis methods enabled by advanced library characterization must be melded into new design flows. These flows comprehend the growing amount of feedback between analog and digital functions that are becoming so interlocked as to be inseparable. This interlock necessitates design flows that include metrics-driven and software-driven testbenches, cross fabric analysis, electrically aware design, and database interoperability across analog and digital design environments.

Figure 4.  Tipping point indicators

Energy efficiency is a universal driver at this point.  Be it cost of ownership in the data center or battery life in a cell phone or wearable device, using less power creates more value in end products. However, layering multiple energy management and optimization techniques on top of complex mixed-signal designs adds yet more complexity demanding adoption of “modern” mixed-signal design practices.

Reason 5: Convergence of analog and digital design

Divide and conquer is always a powerful tool for complexity management.  However, as the number of interactions across the divide increase, the sub-optimality of those frontiers becomes more evident. Convergence is the name of the game.  Just as analog and digital elements of chips are converging, so will the industry practices associated with dealing with the converged world.

Figure 5. Convergence drivers

Truly mixed-signal design is a discipline that unites the analog and digital domains. That means that there is a common/shared data set (versus forcing a single cockpit or user model on everyone). 

In verification the modern saying is “start with the end in mind”. That means creating a formal approach to the plan of what will be test, how it will be tested, and metrics for success of the tests. Organizing the mechanics of testbench development using the Unified Verification Methodology (UVM) has proven benefits. The mixed-signal elements of SoC verification are not exempted from those benefits.

Competition is growing more fierce in the world for semiconductor design teams. Not being equipped with the best-known practices creates a competitive deficit that is hard to overcome with just hard work. As the landscape of IC content drives to a more energy-efficient mixed-signal nature, the mounting risk posed by old methodologies may cause causalities in the coming year. Better to move forward with haste and create a position of strength from which differentiation and excellence in execution can be forged.

Summary

2015 is going to be a banner year for mixed-signal design and verification methodologies. Those that have forged ahead are in a position of execution advantage. Those that have not will be scrambling to catch up, but with the benefits of following a path that has been proven by many market leaders.

The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification methodology. An SoC, in these fast growing applications, incorporates a large number of analog and mixed-signal (AMS) blocks/IPs, some acquired from IP providers, some designed, often concurrently. AMS IP must be verified independently, but this is not sufficient to ensure an SoC will function properly and all scenarios of interaction among many different AMS IP blocks at full chip / SoC level must be verified thoroughly. To reduce an overall verification cycle, AMS IP and SoC verification teams must work in parallel from early stages of the design. Easier said than done! We will outline a methodology than can help.

AMS designers verify their IP meets required specifications by running a testbench they develop for standalone / out of-context verification. Typically, an AMS IP as analog-centric, hierarchal design in schematic, composed of blocks represented by transistor, HDL and behavioral description verified in Virtuoso® Analog Design Environment (ADE) using Spectre AMS Designer simulation. An SoC verification team typically uses UVM SystemVerilog testbech at full chip level where the AMS IP is represented with a simple digital or real number model running Xcelium /DMS simulation from the command line.

Ideally, AMS designers should also verify AMS IP function properly in the context of full-chip integration, but reproducing an often complex UVM SystemVerilog testbench and bringing over top-level design description to an analog-centric environment is not a simple task.

Last year, Cadence partnered with Infineon on a project with a goal to automate the reuse of a top-level testbench in AMS verification. The automation enabled AMS verification engineers to automatically configure setup for verification runs by assembling all necessary options and files from the AMS IP Virtuoso GUI and digital SoC top-level command line configurations. The benefits of this method were:

• AMS verification engineers did not need to re-create complex stimuli representing interaction of their IP at the top level
• Top-level verification stays external to the AMS IP verification environment and continues to be managed by the SoC verification team, but can be reused by the AMS IP team without manual overhead
• AMS IP is verified in-context and any inconsistencies are detected earlier in the verification process
• Improved productivity and overall verification time

For more details, please see Infineon’s CDNLlive presentation.

Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor, analog behavioral and real-number model (RNM) and RTL levels, and combination of these.

In recent years, RNM and simulation is being adopted for functional verification by many, due to advantages it offers including simpler modeling requirements and much faster simulation speed (compared to a traditional analog behavioral models like Verilog-A or VHDL-AMS). Verilog-AMS with its wreal continue to be popular choice. Standardization of real number extensions in SystemVerilog (SV) made SV-RNM an even more attractive choice for MS SoC verification.

Verilog-AMS/wreal is scalar real type. SV-RNM offers a powerful ability to define complex data types, providing a user-defined structure (record) to describe the net value. In a typical design, most analog nodes can be modeled using a single value for passing a voltage (or current) from one module to another. The ability to pass multiple values over a net can be very powerful when, for example, the impedance load impact on an analog signal needs to be modeled. Here is an example of a user-defined net (UDN) structure that holds voltage, current, and resistance values:

When there are multiple drives on a single net, the simulator will need a resolution function to determine the final net value. When the net is just defined as a single real value, common resolution functions such as min, max, average, and sum are built into the simulator.  But definition of more complex structures for the net also requires the user to provide appropriate resolution functions for them. Here is an example of a net with three drivers modeled using the above defined structural elements (a voltage source with series resistance, a resistive load, and a current source):

To properly solve for the resulting output voltage, the resolution function for this net needs to perform Norton conversion of the elements, sum their currents and conductances, and then calculate the resolved output voltage as the sum of currents divided by sum of conductances.

With some basic understanding of circuit theory, engineers can use SV-RNM UDN capability to model electrical behavior of many different circuits. While it is primarily defined to describe source/load impedance interactions, its use can be extended to include systems including capacitors, switching circuits, RC interconnect, charge pumps, power regulators, and others. Although this approach extends the scope of functional verification, it is not a replacement for transistor-level simulation when accuracy, performance verification, or silicon correlation are required:  It simply provides an efficient solution for discretely modeling small analog networks (one to several nodes).  Mixed-signal simulation with an analog solver is still the best solution when large nonlinear networks must be evaluated.

Cadence provides a tutorial on EEnet usage as well as the package (EEnet.pkg) with UDN definitions and resolution functions and modeling examples. To learn more, please login to your Cadence account to access the tutorial.

Cadence_SPB_17.4-2019 + Matlab R2019a

请参考本文档中的步骤进行操作

1，打开BJT_AMP.opj

2，设置Matlab路径

3，打开BJT_AMP_SLPS.slx

4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作

5，添加模块

6，相同

7，打开pspsim.slx

8，相同

9，打开C： Cadence Cadence_SPB_17.4-2019 tools bin

orCEFSimpleUI.exe和orCEFSimple.exe

10，相同

我想问一下如何解决，非常感谢！

Hello,

I'm reading the Design specification for IP6514E.

We will use the DAC mode.

It would seem to be very simple but I don't see any code sequence, i.e.

  1.Write 03(Basic Read) to this register

  2, Write start adress to this register

  3. Write "execute" to this register

  4. Read the data from this register

Thanks,

Stefan

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The IC6.1.8 ISR10 and ICADVM18.1 ISR10 production releases are now available for download.(read more)

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If you have one of those Die layouts, which doesn’t have bumps, but rather uses pad shapes and labels to identify I/O locations, then you might be feeling a bit left out of all of this jazz and tango. Hence, today, I am writing to tell you that, fear not, we have a solution for your Die as well.(read more)

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ڈونالڈ ٹرمپ کی صلاح کے بعد نیویارک مں جراثیم کو مارنے والی اشیا کے پینے کے 30 سے یادہ معاملے سامنے آئے ہیں۔ شہر کے ہیلتھ ڈپارٹمینٹ کے تحت آنے والے (Poison Control Center) کے پاس اس طرح کے معاملات کی گزشتہ 18گھنٹوں میں 30 سے زیادہ کالس آئی ہیں۔ حالانکہ ان میں سے کسی بھی نہ ےو موت ہوئی ہ ہی کسی کو اسپتال(hospital admit) میں داخل کرنے کی ضرورت پڑی ہے۔ ان میں سے زیادہ تر معاملے گھر کی صاف۔صفائی کیلئے استعمال کئے جانے کیلئے استعمال کئے جانے والا (lizol) کے استعمال سے جڑے ہیں۔

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