d

Broadband SPICE -- New Tool for S-Parameter Simulation in Spectre RF

Hi All, Here's another great new feature that I've found very helpful... Broadband SPICE is a new tool for S-parameter simulation in Spectre RF. In the MMSIM13.1.1 ( MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...(read more)




d

See Cadence RF Technologies at IEEE International Microwave Symposium 2014

RF Enthusiasts, Come connect with Cadence RF experts and discover the latest advances in Cadence RF technologies, including Spectre RF at the IEEE International Microwave Symposium (IMS) 2014. This year, IMS will be held in Tampa, Florida. Cadence...(read more)




d

Distortion Summary in New CDNLive YouTube Video and at IEEE IMS2014 Next Week!

Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC, discusses an aggressive...(read more)




d

Cadence Presenting Four Spectre RF MicroApp Papers at IMS2016, May 22-27

Hello Spectre RF Users, Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016 , May 22-27 in San Francisco, CA at the Moscone Center. If you're at the conference, please stop by the Cadence booth and...(read more)




d

Noise Simulation in Spectre RF Using Improved Pnoise/Hbnoise and Direct Plot Form Options

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form has also been enhanced and is much easy to use....(read more)




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7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters in a Time Domain Simulator

Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic steady state) simulator has been and continues to be a challenge for many analog and RF designers. I'm often asked: What is required in order to achieve accurate...(read more)




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Link to: 7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters in a Time Domain Simulator

Hi All, If you were unable to attend IMS 2017 in June 2017, the IMS MicroApp “7 Habits of Highly Successful S-Parameters” is on our Cadence website. On Cadence Online Support , the in-depth AppNote is here: 20466646 . Best regards, Tawna...(read more)




d

Measuring Rapid IP3

In the world of analog design, IP3—the third order intercept point, is a known parameter that is used to measure the linearity in the radio frequency (RF) components. The extracted IP3 values are very essential to determine the operating power ...(read more)




d

How to Set Up and Plot Large-Signal S Parameters?

Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and are defined as the ratio of reflected (or transmitted) waves to incident waves. (read more)




d

Multiple commands using ipcBeginProcess

Hi,

I am trying to use "sed -e 's " from SKILL code to edit unix file "FileA", to replace 3 words in the 2nd line.

How to run below multiple commands using  ipcBeginProcess, Should I use ipcWait or ipcCloseProcess ?

Using && to combine , will that work as I have to work serially on each command. ?

With below code only the first command gets executed. Please advise.

FileA="/user/tmp/text1.txt"

sprintf(Command1 "sed -e '2s/%s/%s/g' %s > %s" comment1 get(form concat("dComment" RDWn))->value FileA FileA)
cid = ipcBeginProcess(Command1)


sprintf(Command2 "sed -e '2s/%s/%s/g' %s > %s"  Time getCurrentTime() FileA FileA)
cid1 = ipcBeginProcess(Command2)


sprintf(Command3 "sed -e '2s/%s/%s/g' %s > %s"  comment2 get(form concat("Duser" RDWn))->value FileA FileA)
cid2 = ipcBeginProcess(Command3)

Thanks,

Ajay




d

SKILL to Identify a LABEL over an Instance

Hello,

I am in a need of a skill program to find all instances of a specific cell (Including Mosaics), throughout the hierarchy. The program should print the instance's name, xy coordinates at the top level, and extract a label name that is dropped on top of it. In case there is no label on top of the found instance, the program should print "No Label Found" in the report text file. This program aims to map PADs cells within top level.

I am using the below Cadence's solution to find instances and it works well. The missing feature is to identify LABELs that are on top of the found instances. 

I tried to use dbGetOverlap() function, within the below code, in few setups but it seems to fail to identify the existence of labels on top of the found instances.

For example: 


overlapLabel=dbGetTrueOverlaps(cv cadr(instBox) list("M1" "text"))

I am interested to add to the Cadence's solution below some code in order to identify labels on top of the found instances.

Any tip would be greatly appreciated.

Thanks,

Danny


--------------------------------------------------------

procedure(HilightCellByArea(lib cell level)
let((cv instList rect instBox)
;; Deleting old highlights.To prevent uncomment the below line
when(boundp('hset) hset->enable=nil)
cv=geGetWindowCellView()
rect=enterBox(
         ?prompts list("Enter the first corner of your box."
                        "Enter the last corner of your box.")
                )
     instList=dbGetOverlaps(cv rect nil level nil)
;; It uses hilite layer packet. You can change it to y0-y9 layer or any other hilite lpp
     ;;hset = geCreateHilightSet(cv list("y0" "drawing") nil)
     ;;hset = geCreateHilightSet(cv list("hilite" "drawing1") nil)
     hset = geCreateHilightSet(cv list("hilite" "drawing") nil)
        hset->enable = t
  foreach(instId instList
     if(listp(instId)
        then
        instBox=CCSTransformBBox(instId)
        instId=car(instBox)
        when(instId~>libName==lib && instId~>cellName==cell
                geAddHilightRectangle(hset cadr(instBox))
                fprintf(myFileId, "Highlighted the %L instance %L of hierarchy at:%L "
                        cell buildString(append1(caddr(instBox)~>name instId~>name) "/") cadr(instBox)
                     foundFlag=t)
                )
        else
        when(instId~>libName==lib && instId~>cellName==cell
                geAddHilightFig(hset instId)
                fprintf(myFileId, "Highlighted the %L instance %L of top cell at:%L "
                         cell instId~>name instId~>bBox)
                         foundFlag=t
                        )
                );if listp
        ) ;foreach
t
) ;let
) ;procedure
procedure(CCSTransformBBox(inst)
let((flatList y location)
while(listp(inst)
        y = car(inst)
        flatList = append(flatList list(y))
        inst = cadr(inst) ; next inst
       );while
location=dbTransformBBox(inst~>bBox dbGetHierPathTransform(list(flatList inst)))
list(inst location flatList)
);let
);procedure




d

convert ircx to ict or emDataFile for Voltus-fi

Hi,

I want to convert ircx file(which is from TSMC,inclued EM Information) to ict or emDataFile for Voltus-fi.

I tried many way, but I can not make it. Can anyone give me some advice?

and I  do not installed QRC.

below is some tools installed my server. 

IC617-64b.500.21 is used.




d

hiCreateAppForm with scrollbars and attachmentList

Hello,

I have created an appForm with  the following attachmentList and size:

?attachmentList list(hicLeftPositionSet | hicRightPositionSet ; field 1
                     hicLeftPositionSet | hicRightPositionSet ; field 2
etc.

?initialSize    800:800
?minSize        800:800
?maxSize       1600:800

If I reduce the minimum y-size (?minSize        800:200), scrollbars are not inserted, unless I remove the attachmentList constraints.

Is it possible to have both scrollbars and "hicLeftPositionSet | hicRightPositionSet"? 

Thank you,

Best regards,

Aldo




d

Get schematic to layout bound stdcells for array

I can get the bound stdcells using bndGetBoundObjects, but not get what each individual stdcell corresponds in layout.

Is there a way to get the layout bound stdcells of an array schematic symbol if the layout stdcell name do or do not match the symbol naming?

Once the schematic array stdcells are bound to the layout stdcells, how to get the correct terminal term~>name and net~>name?

Example of a schematic symbol and layout stdcell:

Schematic

INV<0:2>    instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

                   instTerms~>net~>name = ("<*3>vss" "<*3>vdd" "in<0:2>" "nand2A,nand3B,nor2B")

Layout ( I know it is bad practice, but it happens )

stdcell1 instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<0>" "nand2A")

I23        instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<1>" "nand3B")

INV(2) instTerms~>terms~>name = ("vss" "vdd" "A" "Y")

             instTerms~>net~>name = ("vss" "vdd" "in<2>" "nor2B")

Paul




d

How can I make a SKILL procedure not callable?

Inside the scope of isCallable there is code which I don't want to be executed.

The procedure named in isCallable to-day is callable.

I want to make that procedure so it cannot be called.  How do I do that?

I can't change the isCallable line or the scope.  I want to change its behavior by making sure that the procedure does not exist (obviously this would be done before the code is executed).




d

post-execution on an interrupted SKILL routine

I have a SKILL script that executes the callback of a menu item, and depends on first redefining an environment variable. 

When a user interrupts the script with ctrl-C, the script cannot finish to set the environment variable back to its default value.

How can I write the script in a way that handles a user interrupt to reset the changed environment variable after the interrupt?




d

VIVA Calculator function to get the all outputs and apply a procedure to all of them

Hi,

I am running simulation in ADEXL and need a custom function for VIVA to apply same procedure to all signals saved in output. For instance, I have clock nets and I want to get all of them and look at the duty-cycle, edge rate etc.

It is a little more involved than about part since I have some regex and setof to filter before processing but if I can get all signals for current history, I can postprocess them later.

In ocean, I am just doing outputs() and getting all saved signals but I was able to do this in VIVA calculator due to the difficulties in getting current history, test name and opening result directory

thanks

yayla

Version Info:

ICADV12.3 64b 500.21

spectre -W =>

Tool 'cadenceMMSIM' Current project version '16.10.479'
sub-version  16.1.0.479.isr9




d

Displaying contents of a modeless dialog box during execution of a SKILL script

I have a modeless informational dialog box defined at the beginning of a SKILL script, but its contents don't display until the script finishes.

How do you get a modeless dialog box contents to display while a SKILL script is running?

procedure(myproc()

   prog((myvars)

     hiDisplayAppDBox()    ; opens blank dialog box - no dboxText contents show until script completes!

     ....rest of SKILL code in script...launches child processes

   );prog

);proc




d

Default param values not saved in OA cell property.

When I place a pcell and do not change the W parameter (default is used) the value is not saved in the OA cell property.

When I change the default value of the super master now, the old pcell will get the new default value automatically because there is nothing saved inside the OA cell for this parameter.

Do you have any Idea, that how we can save the default values in the OA cell properties so that this value doesn't get updated if the default values are updated in the new PDKs




d

Skill code to disable all callbacks

Can anybody assist with a Skill code /function to disable all callbacks




d

Parasitic node coordinates

Howdy,

            In the netlist generated after parasitic extraction, nodes have been added at fracture points to add parasitic devices. For example, in the image below, I'm referring to the nodes IN#1 and IN#2. Is there a way to determine their co-ordinates relative to the layout co-ordinate system? I could not find them in the Skill command reference and when I query the parasitic elements in the extracted view, it gives the graphical pin locations of the elements rather than the physical.

Thanks

Audi




d

Choices in radio field to be displayed in two rows

Hi,

I am trying add multiple choices to my radio field in cdf parameters. when i see the select the instance and try editing the Instance properties I can not view them in a single window. Instead i get a vertical sliding bar. Is there a way to display them in multiple rows?

-Haareeth




d

ddDeleteObj() and its warnings

Hello,

After deleting cells using the following loop:

foreach(cellId ddGetObj(libName)~>cells
    ddDeleteObj(cellId)
)

the following warnings are printed in the CIW:

*WARNING* (SCH-2162): "... symbol" has been updated since "... schematic" was last saved. Validate that the schematic is correct and run Check and Save to suppress this warning.
*WARNING* (DB-270337): dbGetInstHeaderMaster: Failed to open cellview '...' from library '...' in read-only mode because the cellview does not exist. This cellview was instantiated in cellview '...' of library '...'. Ensure that the cellview exists in the library.

Is it possible to turn them off?

Thank you

Best regards,

Aldo




d

Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AMBA5

It’s been quite a long 5-year journey building and deploying Performance Analysis, Verification, and Debug capabilities for Arm-based SoCs. We worked with some of the smartest engineers on the planet. First with the engineers at Arm, with whom we...(read more)




d

Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3 of 3)

Here we conclude the blog series and highlight the results of Mediatek 's use of Cadence Perspec™ System Verifier for their SoC level verification. In case you missed it, Part 1 of the blog is here , and Part 2 of the blog is here . One of their key...(read more)




d

Cadence Collaborates with Test & Verification Solutions on Portable Stimulus

The Cadence® Connections® Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. The program members help customer accelerate the adoption of new...(read more)




d

Preparing Accellera Portable Stimulus Standard for Ratification

The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process forward towards ratification. While we can't predict exactly when it will be ratified, the goal is now more clearly in sight! Cadence booth was busy with a lo...(read more)




d

What’s Hot in Verification at this Year’s CDNLive? It’s Portable Stimulus Again!

CDNLive is a user conference, and verification is one of the largest categories of content with multiple tracks covering multiple days. Portable stimulus is one of the hottest new areas in verification, and continues to be popular in all venues. At l...(read more)




d

AMIQ and Cadence demonstrate Accellera PSS v1.0 interoperability

There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced ...(read more)




d

Perspec Portable Stimulus Hands-On Workshop at DAC 2018

Cadence pulled a fast one at DAC 2018, almost like a bait and switch. We advertised a hands-on workshop to learn about Accellera Portable Stimulus Specification (PSS) v1.0. But we made participants compete head to head, for prizes, and their pride! T...(read more)




d

Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application

Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and...(read more)




d

Willamette HDL and Cadence Develop the Industry's First PSS Training Course for Perspec System Verifier

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...(read more)




d

DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety, Security and More

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)




d

detecting duplicate shapes

Is there any way I can find duplicated shapes?

I would like to find two or more shapes are identical and they are placed in the same location.




d

Generating IBIS models in cadence virtuoso

I'm trying to generate IBIS models for the parts that I'm designing.  I'm designing using CADENCE Virtuoso.  

I'm wondering if there is a tutorial for generating IBIS models in CADENCE Virtuoso.   Please pardon me if my question is broad.      




d

Visibility to "component value" property in Edit/Properties dialog?

Hi, I want to add values to components in my SiP design such as 1nF or 15nH. There is already in existence a COMP_VALUE property reserved for this as shown during BOM generation. This property is not visible under the Edit/Properties dialog for component or symbol find filters. We have already created user properties called COMP_MFG and COMP_MFG_PN that it editable at a component level. When we try to add COMP_VALUE it is reported as a reserved name in Cadence but this name is not listed in the properties dialog. Is there a way to turn on the visibility and editablility of this or other hidden reserved Cadence property names? How can I assign a string value to the COMP_VALUE property?

Thanks




d

About Degassing Hole

I use "Degassing" function in APD. It provides the options "Even Layers" and "Odd Layers". 

My first question is that is there any additional setting to choose the specific layer? 

The second question is that  is there any way to select a range to place degassing hoe? I don't want to place holes at the whole layer.

Thanks!  




d

SIP to Allegro pcb designer 17.2 ver

Iam new to Package design SIP tool.

I had created the DIE package using SIP. Kindly give the direction how to map the created DIE package in Allegro pcb editor 17.2 ver.

In Allegro design capture CIS tool we had created the schematics file. The DIE which we are using is having 100pins, We had created the DIE in SIP tool. Out of 100 Die pins, only 90 pins is getting connected others are NC pins. We had mapped the Bond fingers only for 90 Die pins in the SIP package. But in the Schematics we had created the DIE logic symbol for 100 pins. Please advice whether we can able to import the DIE package in the allegro tool. In this scenario while importing the 100 pin DIE package in allegro pcb editor will the net connectivity will be shown from the DIE pad to Bond fingers and from Bond fingers to respective components? Please suggest whether we are going in the right path or please advice what we have to proceed with.

Thanks in Advance,

Rajesh




d

Unable to add wire bond finger from die pins

I have created a die and other components as symbols in sip and placed the symbols in sip through logic import capture netlist. It shows net connectivity but i couldn't add bond finger from the die pins. Please help on this. 




d

How to check a cluster of same net vias spacing, with have no shape or cline covered

 

Hi all,

I have a question regarding the manufacture : how to check a cluster of same net vias spacing, with have no shape or cline covered




d

BoardSurfers: Allegro In-Design Impedance Analysis: Screen your Routed Design Quickly

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

IC Packagers: Shape Connectivity in the Allegro Data Model

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

RAMAC Park and the Origin of the Disk Drive

Did you know that there is a park in San Jose named after a disk drive? Actually, technically it is named after the first computer that used disk drives. You couldn't just go and buy a disk drive...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

My Journey - From a Layout Designer to an Application Engineer

Today, we are living in the era where whatever we think of as an idea is not far from being implemented…thanks to machine learning (ML) and artificial intelligence (AI) entering into the...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis

In this week’s Whiteboard Wednesdays video, Dave Apte discusses how to create the lowest power design possible by using architectural exploration and Cadence’s Stratus HLS solution....

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

1G Mobile: AMPS, TOPS, C-450, Radiocom 2000, and All Those Japanese Ones

You can't read anything about technology these days without reading about 5G. But before there was 5G, there was 4G. And before that 3G, 2G, and 1G. A 0G even. For the next few Thursdays,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

Library Characterization Tidbits: Recharacterize What Matters - Save Time!

Recently, I read an article about how failure is the stepping stone to success in life. It instantly struck a chord and a thought came zinging from nowhere about what happens to the failed arcs of a...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

Start Your Engines: AMSD Flex – Your Instant Access to Latest Spectre Features!

Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




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2019 HF1 Release for Clarity, Celsius, and Sigrity Tools Now Available

The 2019 HF1 production release for Clarity, Celsius, and Sigrity Tools is now available for download at Cadence Downloads . SIGRITY2019 HF1 For information about supported platforms, compatibility...

[[ Click on the title to access the full blog on the Cadence Community site. ]]




d

Sunday Brunch Video for 3rd May 2020

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: EDA101 Video Tuesday: Weekend Update Wednesday: RAMAC Park and the Origin of the Disk Drive Thursday: 1G Mobile: AMPS, TOPS, C-450,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]