ca Replace Cache useing TCL command By community.cadence.com Published On :: Wed, 21 Mar 2018 09:30:10 GMT Hello, I'm using OrCad 17.2 and in the company I'm wokring at there was a change in the database folder (from driver F to G for example) and it effects the option of synchronise using the Part Manager. and changing manually each part in the Desgin Cahce can be a pain. Is there any way I can make a TCL script that will run and replace a part cahce with other? Better if I can call from a table to read, and write from other collum. I would really be happy for an example. Thanks for the help. Full Article
ca TensorFlow Optimization in DSVM: Azure and Cadence By community.cadence.com Published On :: Mon, 22 Oct 2018 12:41:39 GMT Hello Folks, Problem statement first: How does one properly setup tensorflow for running on a DSVM using a remote Docker environment? Can this be done in aml_config/*.runconfig? I receive the following message and I would like to be able to utilize the increased speeds of the extended FMA operations. tensorflow/core/platform/cpu_feature_guard.cc:140] Your CPU supports instructions that this TensorFlow binary was not compiled to use: AVX2 FMA Background: I utilize a local docker environment managed through Azure ML Workbench for initial testing and code validation so that I'm not running an expensive DSVM constantly. Once I assess that my code is to my liking, I then run it on a remote docker instance on an Azure DSVM. I want a consistent conda environment across my compute environments, so this works out extremely well. However, I cannot figure out how to control the tensorflow build to optimize for the hardware at hand (i.e. my local docker on macOS vs. remote docker on Ubuntu DSVM) Full Article
ca Matlab cannot open Pspice, to prompt orCEFSimpleUI.exe that it has stopped working! By community.cadence.com Published On :: Thu, 09 Apr 2020 12:08:58 GMT Cadence_SPB_17.4-2019 + Matlab R2019a 请参考本文档中的步骤进行操作 1,打开BJT_AMP.opj 2,设置Matlab路径 3,打开BJT_AMP_SLPS.slx 4,打开后,设置PSpiceBlock,出现或CEFSimpleUI.exe停止工作 5,添加模块 6,相同 7,打开pspsim.slx 8,相同 9,打开C: Cadence Cadence_SPB_17.4-2019 tools bin orCEFSimpleUI.exe和orCEFSimple.exe 10,相同 我想问一下如何解决,非常感谢! Full Article
ca How to remove incorrect nets error in cadence? By community.cadence.com Published On :: Tue, 03 Nov 2020 10:58:16 GMT While doing the lvs it's showing an error in gnd connection, I am not being able to understand exactly what is the error and what do I need to do to remove this error? Full Article
ca Formal Verification Approach for I2C Slave By community.cadence.com Published On :: Mon, 16 Nov 2020 15:31:30 GMT Hello, I am new in formal verification and I have a concept question about how to verify an I2C Slave block. I think the response should be valid for any serial interface which needs to receive information for several clocks before making an action. The the protocol description is the following: I have a serial clock (SCL), Serial Data Input (SDI) and Serial Data Output (SDO), all are ports of the I2C Slave block. The protocol looks like this: The first byte which is received by the slave consists in 7bits of sensor address and the 8th bit is the command 0/1 Write/Read. After the first 8 bits, the slave sends an ACK (SDO = 1 for 1 clock) if the sensor address is correct. Lets consider only this case, where I want to verify that the slave responds with an ACK if the sensor address is correct. The only solution I found so far was to use the internal buffer from the block which saves the received bits during 8 clocks. The signal is called shift_s. I also needed to use internal chip state (state_s) and an internal counter (shift_count_s). Instead of doing an direct check of the SDO(sdo_o) depending on SDI (sdi_d_i), I used the internal shift_s register. My question is if my approach is the correct one or there is a possibility to write the verification at a blackbox level. Below you have the 2 properties: first checks connection from SDI to internal buffer, the second checks the connection between internal buffer and output. property prop_i2c_sdi_store; @(posedge sclk_n_i) $past(i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR) |-> i2c_bl.shift_s == byte'({ $past(i2c_bl.shift_s), $past(sdi_d_i)}); endproperty APF_I2C_CHECK_SDI_STORE: assert property(prop_i2c_sdi_store); property prop_i2c_sensor_addr(sens_addr_sel, sens_addr); @(posedge sclk_n_i) (i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR) && (i2c_addr_i == sens_addr_sel) && (i2c_bl.shift_count_s == 7) ##1 (i2c_bl.shift_s inside {sens_addr, sens_addr+1}) |-> sdo_o; endproperty APF_I2C_CHECK_SENSOR_ADDR0: assert property(prop_i2c_sensor_addr(0, `I2C_SENSOR_ADDRESS_A0)); APF_I2C_CHECK_SENSOR_ADDR1: assert property(prop_i2c_sensor_addr(1, `I2C_SENSOR_ADDRESS_A1)); APF_I2C_CHECK_SENSOR_ADDR2: assert property(prop_i2c_sensor_addr(2, `I2C_SENSOR_ADDRESS_A2)); APF_I2C_CHECK_SENSOR_ADDR3: assert property(prop_i2c_sensor_addr(3, `I2C_SENSOR_ADDRESS_A3)); PS: i2c_addr_i is address selection for the slave (there are 4 configurable sensor addresses, but this is not important for the case). Thank you! Full Article
ca The code used to Replace Cache useing TCL command By community.cadence.com Published On :: Fri, 19 Apr 2024 10:16:17 GMT use the DBO function DboLib_RepalceCache to do the job of "Replace cache" in order to easy the job , type the code below . the code is a wrapper of the function metioned above set lStatus [DboState]set lSession $::DboSession_s_pDboSessionDboSession -this $lSessionset lDesignsIter [$lSession NewDesignsIter $lStatus]set lDesign [$lDesignsIter NextDesign $lStatus]set lNullObj NULL set oldLibName [DboTclHelper_sMakeCString "E:\PROJECT_WORKLIB.OLB"]set newLibName [DboTclHelper_sMakeCString "E:\MCU_PARTS_LIB.OLB"] #DboLib_ReplaceCache wrapperproc ReplaceCacheByName {partName} { global oldLibName global newLibName global lDesign set lPartStr [DboTclHelper_sMakeCString $partName] #set lNewStr [DboTclHelper_sMakeCString $newName] $lDesign ReplaceCache $lPartStr $oldLibName $lPartStr $newLibName 0 1} then use the tcl command like below to do the real job : ReplaceCacheByName "CL10B104KB8NNNC_C12" Full Article
ca How to design enhancement mode eGaN (EPC8002) switch in cadence By community.cadence.com Published On :: Tue, 06 Aug 2024 08:44:04 GMT Hi, I need to design EPC8002 eGaN switch in cadence. Can someone provide me step by step guide on hoe to add EPC8002 into my cadence. I am working on BCD180. Thank you Ihsan Full Article
ca Can't request Tensilica SDK - Error 500 By community.cadence.com Published On :: Tue, 22 Oct 2024 14:25:12 GMT Hi, I'm looking to download Tensilica SDK for evaluation, but I can't get past the registration form: Full Article
ca To Escalate or Not? This Is Modi’s Zugzwang Moment By indiauncut.com Published On :: 2019-03-03T03:19:05+00:00 This is the 17th installment of The Rationalist, my column for the Times of India. One of my favourite English words comes from chess. If it is your turn to move, but any move you make makes your position worse, you are in ‘Zugzwang’. Narendra Modi was in zugzwang after the Pulwama attacks a few days ago—as any Indian prime minister in his place would have been. An Indian PM, after an attack for which Pakistan is held responsible, has only unsavoury choices in front of him. He is pulled in two opposite directions. One, strategy dictates that he must not escalate. Two, politics dictates that he must. Let’s unpack that. First, consider the strategic imperatives. Ever since both India and Pakistan became nuclear powers, a conventional war has become next to impossible because of the threat of a nuclear war. If India escalates beyond a point, Pakistan might bring their nuclear weapons into play. Even a limited nuclear war could cause millions of casualties and devastate our economy. Thus, no matter what the provocation, India needs to calibrate its response so that the Pakistan doesn’t take it all the way. It’s impossible to predict what actions Pakistan might view as sufficient provocation, so India has tended to play it safe. Don’t capture territory, don’t attack military assets, don’t kill civilians. In other words, surgical strikes on alleged terrorist camps is the most we can do. Given that Pakistan knows that it is irrational for India to react, and our leaders tend to be rational, they can ‘bleed us with a thousand cuts’, as their doctrine states, with impunity. Both in 2001, when our parliament was attacked and the BJP’s Atal Bihari Vajpayee was PM, and in 2008, when Mumbai was attacked and the Congress’s Manmohan Singh was PM, our leaders considered all the options on the table—but were forced to do nothing. But is doing nothing an option in an election year? Leave strategy aside and turn to politics. India has been attacked. Forty soldiers have been killed, and the nation is traumatised and baying for blood. It is now politically impossible to not retaliate—especially for a PM who has criticized his predecessor for being weak, and portrayed himself as a 56-inch-chested man of action. I have no doubt that Modi is a rational man, and knows the possible consequences of escalation. But he also knows the possible consequences of not escalating—he could dilute his brand and lose the elections. Thus, he is forced to act. And after he acts, his Pakistan counterpart will face the same domestic pressure to retaliate, and will have to attack back. And so on till my home in Versova is swallowed up by a nuclear crater, right? Well, not exactly. There is a way to resolve this paradox. India and Pakistan can both escalate, not via military actions, but via optics. Modi and Imran Khan, who you’d expect to feel like the loneliest men on earth right now, can find sweet company in each other. Their incentives are aligned. Neither man wants this to turn into a full-fledged war. Both men want to appear macho in front of their domestic constituencies. Both men are masters at building narratives, and have a pliant media that will help them. Thus, India can carry out a surgical strike and claim it destroyed a camp, killed terrorists, and forced Pakistan to return a braveheart prisoner of war. Pakistan can say India merely destroyed two trees plus a rock, and claim the high moral ground by returning the prisoner after giving him good masala tea. A benign military equilibrium is maintained, and both men come out looking like strong leaders: a win-win game for the PMs that avoids a lose-lose game for their nations. They can give themselves a high-five in private when they meet next, and Imran can whisper to Modi, “You’re a good spinner, bro.” There is one problem here, though: what if the optics don’t work? If Modi feels that his public is too sceptical and he needs to do more, he might feel forced to resort to actual military escalation. The fog of politics might obscure the possible consequences. If the resultant Indian military action causes serious damage, Pakistan will have to respond in kind. In the chain of events that then begins, with body bags piling up, neither man may be able to back down. They could end up as prisoners of circumstance—and so could we. *** Also check out: Why Modi Must Learn to Play the Game of Chicken With Pakistan—Amit Varma The Two Pakistans—Episode 79 of The Seen and the Unseen India in the Nuclear Age—Episode 80 of The Seen and the Unseen The India Uncut Blog © 2010 Amit Varma. All rights reserved. Follow me on Twitter. Full Article
ca Can Amit Shah do for India what he did for the BJP? By indiauncut.com Published On :: 2019-06-02T02:07:40+00:00 This is the 20th installment of The Rationalist, my column for the Times of India. Amit Shah’s induction into the union cabinet is such an interesting moment. Even partisans who oppose the BJP, as I do, would admit that Shah is a political genius. Under his leadership, the BJP has become an electoral behemoth in the most complicated political landscape in the world. The big question that now arises is this: can Shah do for India what he did for the BJP? This raises a perplexing question: in the last five years, as the BJP has flourished, India has languished. And yet, the leadership of both the party and the nation are more or less the same. Then why hasn’t the ability to manage the party translated to governing the country? I would argue that there are two reasons for this. One, the skills required in those two tasks are different. Two, so are the incentives in play. Let’s look at the skills first. Managing a party like the BJP is, in some ways, like managing a large multinational company. Shah is a master at top-down planning and micro-management. How he went about winning the 2014 elections, described in detail in Prashant Jha’s book How the BJP Wins, should be a Harvard Business School case study. The book describes how he fixed the BJP’s ground game in Uttar Pradesh, picking teams for 147,000 booths in Uttar Pradesh, monitoring them, and keeping them accountable. Shah looked at the market segmentation in UP, and hit upon his now famous “60% formula”. He realised he could not deliver the votes of Muslims, Yadavs and Jatavs, who were 40% of the population. So he focussed on wooing the other 60%, including non-Yadav OBCs and non-Jatav Dalits. He carried out versions of these caste reconfigurations across states, and according to Jha, covered “over 5 lakh kilometres” between 2014 and 2017, consolidating market share in every state in this country. He nurtured “a pool of a thousand new OBC and Dalit leaders”, going well beyond the posturing of other parties. That so many Dalits and OBCs voted for the BJP in 2019 is astonishing. Shah went past Mandal politics, managing to subsume previously antagonistic castes and sub-castes into a broad Hindutva identity. And as the BJP increased its depth, it expanded its breadth as well. What it has done in West Bengal, wiping out the Left and weakening Mamata Banerjee, is jaw-dropping. With hindsight, it may one day seem inevitable, but only a madman could have conceived it, and only a genius could have executed it. Good man to be Home Minister then, eh? Not quite. A country is not like a large company or even a political party. It is much too complex to be managed from the top down, and a control freak is bound to flounder. The approach needed is very different. Some tasks of governance, it is true, are tailor-made for efficient managers. Building infrastructure, taking care of roads and power, building toilets (even without an underlying drainage system) and PR campaigns can all be executed by good managers. But the deeper tasks of making an economy flourish require a different approach. They need a light touch, not a heavy hand. The 20th century is full of cautionary tales that show that economies cannot be centrally planned from the top down. Examples of that ‘fatal conceit’, to use my hero Friedrich Hayek’s term, include the Soviet Union, Mao’s China, and even the lady Modi most reminds me of, Indira Gandhi. The task of the state, when it comes to the economy, is to administer a strong rule of law, and to make sure it is applied equally. No special favours to cronies or special interest groups. Just unleash the natural creativity of the people, and don’t try to micro-manage. Sadly, the BJP’s impulse, like that of most governments of the past, is a statist one. India should have a small state that does a few things well. Instead, we have a large state that does many things badly, and acts as a parasite on its people. As it happens, the few things that we should do well are all right up Shah’s managerial alley. For example, the rule of law is effectively absent in India today, especially for the poor. As Home Minister, Shah could fix this if he applied the same zeal to governing India as he did to growing the BJP. But will he? And here we come to the question of incentives. What drives Amit Shah: maximising power, or serving the nation? What is good for the country will often coincide with what is good for the party – but not always. When they diverge, which path will Shah choose? So much rests on that. The India Uncut Blog © 2010 Amit Varma. All rights reserved. Follow me on Twitter. Full Article
ca Start Your Engines: Create and Insert Connect Modules for Mixed-Signal Verification By community.cadence.com Published On :: Tue, 11 Jun 2024 16:17:00 GMT Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera. (read more) Full Article AMS AMS Designer Mixed-Signal AMS simulation mixed-signal design AMS Verification mixed-signal verification
ca Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Pt. 2 By community.cadence.com Published On :: Wed, 26 Jun 2024 20:00:00 GMT At a bustling Cadence event, we met Adrian, an intern at a startup who immerses himself in Cadence tools for his research and work. Adrian was enthusiastic about the innovative technologies at his disposal but faced a significant challenge: internet access was limited to a single machine for new joiners, forcing interns to wait in line for their turn to use online resources. Adrian's excitement soared when he discovered a game-changing solution: Doc Assistant. The cloud-based help viewer, Doc Assistant, ships with all Cadence tools, enabling Adrian to access help resources offline from any machine equipped with the software. This meant Adrian could continue his research and work seamlessly, irrespective of internet availability! Meeting Cadence users and customers at such events has given us the opportunity to showcase how they can benefit from the diverse features that Doc Assistant offers. With that note, welcome back to our Doc Assistant A-Z blog series! In Part 1, we explored key features and benefits that our innovative viewer brings to the table. Today, in Part 2, we'll dive deeper into the advanced functionalities and customization options that make Doc Assistant indispensable for its users. Whether you're looking to streamline your workflow or enhance your user experience, this blog will provide the insights you need to fully leverage the capabilities of our documentation viewer. Let’s get started! What Makes Doc Assistant Stand Out? Here are a few (more) cool features of Doc Assistant! History and Bookmarks: Want to refer to the topic you read last week? Of course, you can! Doc Assistant stores your browsing activity as History. You can also bookmark topics and revisit them later. Indexing Capabilities: Looking for seamless search capabilities? The advanced indexing capabilities of Doc Assistant enhance the accessibility and manageability of documents. Doc Assistant automatically creates a search index if it is missing or broken. Jump Links: Worried about scrolling through lengthy topics? Fret no more! Use the jump links in each topic to quickly navigate to different sections within the same topic or across topics. Jump links reduce the need for excessive scrolling and let you access relevant content swiftly. Just-in-Time Notifications: Looking for alerts and messages? That’s supported. Doc Assistant displays notifications about important events, including errors, warnings, information, and success messages. Keyword-Based Search Suggestions: You somewhat know your search keyword, but not quite sure? No worries. Just start typing what you know. Keyword and page suggestions are displayed dynamically as you type, providing a more sophisticated and intuitive search experience. Library-Switch Support: Want to view documents from other libraries? Doc Assistant, by default, displays documents for the currently active release in your machine. You can access documents from other releases by configuring the associated documentation libraries. Multimedia Support: Want to view product demos? Multimedia support in Doc Assistant lets you play videos, listen to audio, and view images without opening any external application. Navigation Made Easy: Worried that you’ll get lost in an infinite doc loop? Not at all. The intuitive navigation controls in Doc Assistant are designed to provide you with a fluid and efficient experience. The Doc Assistant user interface is clean and logically organized, with easy-to-access documentation links. That's not all. We have more coming your way. Until next time, take care and stay tuned for our next edition! Want to Know More? Here's a video about Doc Assistant Visit the Doc Assistant web page Read the Doc Assistant FAQ document For any questions or general feedback, write to docassistant.support@cadence.com. Subscribe to receive email notifications about our latest Custom IC Design blog posts. Happy reading! -Priya Sriram, on behalf of the Doc Assistant Team Full Article In-Tool Help user documentation in-built help Cloud-Based Help Doc Assistant
ca Knowledge Booster Training Bytes - Writing Physical Verification Language Rules By community.cadence.com Published On :: Wed, 03 Jul 2024 08:56:00 GMT Have you ever wanted to write a DRC rule deck to check for space or width constraints on polygons? Or have you wondered how the multiple lines of an LVS rule deck extract and conduct a comparison between the schematic and layout? Maybe you've been curious about the role of rule deck writers in creating high-quality designs ready for tape-out. If any of these questions interest you, there is good news: the latest version (v23.1) of the Physical Verification Rules Writer (PVLRW) course is designed to teach you rule deck writing. This free 16-hour online course includes audio and labs designed to make your learning experience comfortable and flexible. Whether you are new to the concept or an experienced CAD/PDK engineer, the course is structured to enhance your rule deck writing skills. The PVLRW course covers six core modules: Layer Processing, DRC Rules, Layout Extraction, ERC and LVS Rules, Schematic Netlisting, and Coloring Rules. There are also three optional appendix sections. Each module explains relevant rules with syntax, concepts, graphics, examples, and case studies. This course is based on tool versions PEGASUS231 and Virtuoso Studio IC231. Pegasus Input and Output Pegasus is a cloud-ready physical verification signoff solution that enables engineers to support faster delivery of advanced-node integrated circuits (ICs) to market. Pegasus requires input data in the form of layout geometry, schematic netlists, and rules that direct the tool operation. The rules fall into two categories: those that describe the fabrication process and those that control the job-specific operation. Pegasus provides log and report files, netlists, databases, and error databases as output. Overview of Pegasus Rule File The rule decks written in Physical Verification Language (PVL) work for the Cadence PV signoff tools Pegasus and PVS (Physical Verification System). The PVL rules are placed in a file that gets selected in a run from the GUI or the command line, as the user directs. PVL rules may be on separate lines within the file and can also be contained in named rule blocks. Each line of code starts with a PVL rule that uses prefix type notation. It consists of a keyword followed by options, input layer or variable names, and output layer or variable names. A rule block has the format of the keyword rule, followed by a rule name you wish to give it, followed by an opening curly brace. You enter the rules you wish to perform, followed by a closing curly brace on the last separate line. Sample Rule deck with individual lines of code and rule blocks. DRC Rules The first step in a typical Pegasus flow is a Design Rule Check (DRC), which verifies that layout geometries conform to the minimum width, spacing, and other fabrication process rules required by an IC foundry. Each foundry specifies its own process-dependent rules that must be met by the layout design. There are three types of DRC rules: layer definition rules, layer derivation rules, and DRC design check rules. Layer definition rules identify the layers contained in the input layout database, and layer derivation rules derive additional layers from the original input layers, allowing the tool to test the design against specific foundry requirements using the design check rules. A sample DRC Rule deck A layout view displaying the DRC violations LVS Rules The Pegasus Layout Versus Schematic (LVS) tool compares the layout netlist with the schematic netlist to check for discrepancies. There are two essential LVS rule sets: LVS extraction rules and comparison rules. LVS extraction rules help extract drawn devices and connectivity information from the input layout geometry data and outputs into a layout netlist. The LVS extraction rule set also includes the layer definition, derivation, extraction, connectivity, and net listing rules. LVS comparison rules are associated with comparing the extracted layout netlist to a schematic netlist. A sample LVS Rule deck. TCL, Macros, and Conditional commands Tcl is supported and used in various Pegasus functionalities, such as Pegasus rule files and Pegasus configurator. Macros are functional templates that are defined once and can be used multiple times in a rule file. Conditional Commands are used to process or skip specific commands in the rule file. Do You Have Access to the Cadence Support Portal? If not, follow the steps below to create your account. On the Cadence Support portal, select Register Now and provide the requested information on the Registration page. You will need an email address and host ID to sign up. If you need help with registration, contact support@cadence.com. To stay up to date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails. If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training. For any questions, general feedback, or future blog topic suggestions, please leave a comment. Related Resources Product Manuals Cadence Pegasus Developers Guide Rapid Adoption Kits Running Pegasus DRC/LVS/FILL in Batch Mode Training Byte Videos What Is the Run Command File? How to Run PVS-Pegasus Jobs in GUI and Batch modes? PVS DRC Run From - Setup Rules What Is PVS/Pegasus Layer Viewer? PVL Coloring Ruledecks with Docolor and Stitchcolor PLV Commands: dfm_property with Primary & Secondary Layer PVS Quantus QRC Overview Online Courses Pegasus Verification System PVS (Physical Verification System) Virtuoso Layout Design Basics About Knowledge Booster Training Bytes Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis. Subscribe to receive email notifications about our latest Custom IC Design blog posts. Full Article Virtuoso Studio Routing Layout Suite Cadence training training bytes Circuit Design Cadence Education Services Custom IC Design online training
ca Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer Part 3 By community.cadence.com Published On :: Tue, 01 Oct 2024 05:16:00 GMT Welcome back to the Doc Assistant A-Z blog series! Since the launch of Doc Assistant, we've been gathering feedback and input from our customers regarding their experiences with our latest documentation viewer. My interaction with Ralf was particularly useful and interesting. Ralf is a design engineer who works on complex schematics and intricate layouts. For each release, he is challenged with the task of verifying the tool and feature changes across multiple releases. He shared with me that he has been using Doc Assistant’s capabilities to help him achieve this. Ralf explained that he utilizes Doc Assistant to open and compare documents from different releases side-by-side, seamlessly tracking updates across multiple releases and verifying those updates in his Cadence tools. Additionally, in Doc Assistant’s online mode, he compares documents across previous tool versions, ensuring a thorough review of any changes. Finally, he was happy to share with me that Doc Assistant features have helped him significantly reduce the time he spends on identifying such changes. You, of course, can also achieve such productivity gains using several Doc Assistant features designed to help simplify such tasks! In previous editions of this blog series, we looked at some key features and benefits of Doc Assistant. If you've missed these editions, I would highly recommend that you read them: Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 1 Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer: Part 2 In this third installment, we're diving into some more of Doc Assistant's key capabilities. Open Multiple Documents Want to refer to multiple docs at the same time? That’s easy! Open each doc on a separate tab in Doc Assistant. Personalized Content Recommendations Is it a hassle to navigate through all docs each time? You don’t have to. You can tailor your Doc Assistant preferences to match your content requirements. PDF Support Do you prefer downloading and reading a PDF instead of an HTML? That’s also supported. Quick Access to Relevant Search Results Are you pressed for time, and yet want to run a comprehensive doc search? You’re covered. In online mode, search runs on all available product documentation, and the results are listed from multiple sources. Resource Links Looking for more information about a topic you’ve just read? That’s handy. Look out for content recommendations! Share Content Want to share a useful doc with the rest of your team? That’s easy. With a single click, Doc Assistant lets you share content with one or more readers. Submit Feedback Your feedback is important to us. Use the Submit Feedback feature to share your comments and inputs. To learn more about how to use the above features, check out the Doc Assistant User Guide. These are just a few of the productivity gain features in Doc Assistant. We’ll cover more in the next blog in the series. Want to Know More? Here's a video about Doc Assistant Visit the Doc Assistant web page Read the Doc Assistant FAQ document If you have any feedback on Doc Assistant or would like to request more information or a demo, please contact docassistant.support@cadence.com. Subscribe to receive email notifications about our latest Custom IC Design blog posts. Happy reading! - Priya Sriram, on behalf of the Doc Assistant Team Full Article In-Tool Help user documentation in-built help Cloud-Based Help Doc Assistant
ca How to transfer custom title block from Orcad Capture to PCB Editor By community.cadence.com Published On :: Thu, 09 Dec 2021 21:37:59 GMT Hi, So I was trying to update the title block of a schematic that I have. The title block that was on there was out of date . I clicked on place --> title block and was able to find the title block that I need. I also have a .OLB file that contains that title block. Then I created a Netlist with the old BRD file as the input file (To keep it as is but modify changes) but when I do that I still do not see / cannot place the title block that I need. Under Place --> format symbols in Allegro , I do see a title block that is coming from the database (But it's the old one). I don't know what to do at this point and would appreciate any tips. I did make sure that the path to where the library is , is defined in the user preferences. I also tried copying the title block under the library folder in capture before creating my Netlist and that did not work either. Thank you all. Full Article
ca Purging duplicate vias in pcb editor By community.cadence.com Published On :: Fri, 10 Dec 2021 07:07:15 GMT How do we purge/remove the duplicated vias in the same location of the PCB editor? These vias are not the one stacked and they are just blind vias running in internal layers 12-14. I find there is an additional copy of the blind via at the same location. Not sure what caused this issue. Full Article
ca Launch footprint editor from Capture or PCB Editor? By community.cadence.com Published On :: Fri, 10 Dec 2021 15:14:52 GMT I'd like to be able to edit a footprint for a part in my design without needing to find the footprint filepath and directly open that file in PCB Editor. I see that I can view footprints from Capture, and that doing so shows me the footprint path, but I can't find any way to launch the editor. Is there any way to go directly from a part in a Capture schematic or a placed part in a PCB Editor board design to editing that part's footprint? Full Article
ca Orcad PCB (allegro) not using GPU over USB By community.cadence.com Published On :: Mon, 13 Dec 2021 16:19:21 GMT Hi, I have a monitor plugged to my laptop using a HDMI to USB adapter. When using this adapter, Allegro runs very slowly. It seems that it is not using my video card. Is this a known issue with a workaround I can try? Thanks, Michael Full Article
ca Can I align pin numbers in edit part windows in Orcad Capture? By community.cadence.com Published On :: Tue, 14 Dec 2021 01:55:10 GMT Hello.. I'm updating part in part editor in orcad capture, and I wonder how to align pin numbers using menu or tcl/tk command. Please, let me know. Thank you. Full Article
ca datasheets for difference of Allegro PCB and OrCAD Professional By community.cadence.com Published On :: Tue, 14 Dec 2021 09:08:17 GMT Hi All I am looking for the functions which are different about OrCAD Professional and Allegro tier. is there any resource? regard Full Article
ca The default location of orCAD Capture library Pin Number is incorrect By community.cadence.com Published On :: Tue, 14 Dec 2021 21:38:21 GMT The default position of the pin number is incorrect. Full Article
ca Allegro part of DPI does not support scaling above 150% By community.cadence.com Published On :: Tue, 14 Dec 2021 21:49:57 GMT Allegro part of DPI does not support scaling above 150% Full Article
ca Migrating from files Orcad Layout 16.2 By community.cadence.com Published On :: Wed, 15 Dec 2021 02:55:48 GMT I have managed to convert our old schematic and PCD file to from Layout 16.2 to 17.4 I have exported the footprints and moved them to the correct lib directory. I get no DRC errors and I can build a new netlist file. The problem is I can't get the PCB editor to update using the new netlist and get the following error: I cannot figure out how to fix the Name is too long error. (---------------------------------------------------------------------) ( ) ( Allegro Netrev Import Logic ) ( ) ( Drawing : 70055R2.brd ) ( Software Version : 17.4S023 ) ( Date/Time : Tue Dec 14 18:54:25 2021 ) ( ) (---------------------------------------------------------------------) ------ Directives ------------ Ripup etch: Yes Ripup delete first segment: No Ripup retain bondwire: No Ripup symbols: IfSame Missing symbol has error: No DRC update: Yes Schematic directory: 'C:/AFS/70055 PCB Test 2' Design Directory: 'C:/AFS/70055 PCB Test 2' Old design name: 'C:/AFS/70055 PCB Test 2/70055R2.brd' New design name: 'C:/AFS/70055 PCB Test 2/70055R2.brd' CmdLine: netrev -$ -i C:/AFS/70055 PCB Test 2 -x -u -t -y 2 -h -z -q netrev_constraint_report.xml C:/AFS/70055 PCB Test 2/#Taaaaae57776.tmp ------ Preparing to read pst files ------ Starting to read C:/AFS/70055 PCB Test 2/pstchip.dat Finished reading C:/AFS/70055 PCB Test 2/pstchip.dat (00:00:00.02) Starting to read C:/AFS/70055 PCB Test 2/pstxprt.dat Finished reading C:/AFS/70055 PCB Test 2/pstxprt.dat (00:00:00.00) Starting to read C:/AFS/70055 PCB Test 2/pstxnet.dat Finished reading C:/AFS/70055 PCB Test 2/pstxnet.dat (00:00:00.00) ------ Oversights/Warnings/Errors ------ #1 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'. ERROR(SPMHNI-170): Device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro. #2 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'. ERROR(SPMHNI-170): Device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_S' has library errors. Unable to transfer to Allegro. #3 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'. ERROR(SPMHNI-170): Device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro. #4 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW DPDT': 'Name is too long.'. ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW' has library errors. Unable to transfer to Allegro. #5 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'. ERROR(SPMHNI-170): Device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW' has library errors. Unable to transfer to Allegro. #6 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_DPDT': 'Name is too long.'. ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_DP' has library errors. Unable to transfer to Allegro. #7 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB15_DSUBVPTM15_CONNECTOR DB15': 'Name is too long.'. ERROR(SPMHNI-170): Device 'CONNECTOR DB15_DSUBVPTM15_CONNE' has library errors. Unable to transfer to Allegro. #8 ERROR(SPMHNI-176): Device library error detected. ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB9_DSUBVPTM9_CONNECTOR DB9': 'Name is too long.'. ERROR(SPMHNI-170): Device 'CONNECTOR DB9_DSUBVPTM9_CONNECT' has library errors. Unable to transfer to Allegro. #9 ERROR(SPMHNI-175): Netrev error detected. ERROR(SPMHDB-195): Error processing 'M6': Text line is outside of the extents.. ------ Library Paths ------ MODULEPATH = . C:/Cadence/SPB_17.4/share/local/pcb/modules PSMPATH = . symbols .. ../symbols C:/Cadence/SPB_17.4/share/local/pcb/symbols C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols PADPATH = . symbols .. ../symbols C:/Cadence/SPB_17.4/share/local/pcb/padstacks C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols ------ Summary Statistics ------ #10 Run stopped because errors were detected netrev run on Dec 14 18:54:25 2021 DESIGN NAME : '70055R2' PACKAGING ON Nov 2 2021 14:32:04 COMPILE 'logic' CHECK_PIN_NAMES OFF CROSS_REFERENCE OFF FEEDBACK OFF INCREMENTAL OFF INTERFACE_TYPE PHYSICAL MAX_ERRORS 500 MERGE_MINIMUM 5 NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|' NET_NAME_LENGTH 24 OVERSIGHTS ON REPLACE_CHECK OFF SINGLE_NODE_NETS ON SPLIT_MINIMUM 0 SUPPRESS 20 WARNINGS ON 10 errors detected No oversight detected No warning detected cpu time 0:00:27 elapsed time 0:00:00 Full Article
ca No windows cascading in OrCAD Capture 17.4 By community.cadence.com Published On :: Tue, 21 Dec 2021 08:02:37 GMT Hello All, I'm a novice to this forum and probably this subject has been already discussed here. My company has purchased OrCAD Capture 17.4 tools that have a new GUI if compared to my earlier used OrCAD Capture 9.2. I have been using Capture 9.2 for ~18 years and its GUI is really convenient. The GUI of 17.4 looks to be a modern one with new icons and really has improved features and new capabilities. However, my main complain about GUI 17.4 is that the schematic windows cannot be cascaded. Although they can be set floating, this is even more annoying because all toolbars remain in the Capture window and when you select a tool, the Capture window pops over already open schematic window and you need a lot of useless extra clicks to return back to the currently edited schematic page. I always used cascading of schematic windows before because my complex designs includes many pages, not speaking about the library windows that are typically open simulatneously. My view is that the lack of CASCADING in Capture GUI 17.4 is critical and unacceptable for complex projects, and I would very highly appreciate if the Cadence guys will return back the CASCADING capability for schematic pages. In case this will be done, this will make the GUI really great and comfortable to use. Does anybody have opinion on this issue? Many thanks, Pavel Full Article
ca Version upgrade 17.2 to 17.4 - Cadance orcad capture By community.cadence.com Published On :: Tue, 21 Dec 2021 10:49:08 GMT hello, We have a number of workstations with version 17.2 that work on a floating license server We want to know if it can be upgraded to version 17.4 If so, should the floating license server be upgraded as well? In addition, how can you know where the license was purchased from? Thanks! Full Article
ca Sense line and decoupling capacitors By community.cadence.com Published On :: Thu, 23 Dec 2021 08:16:10 GMT Hello, A mybe silly question came to my mind: When routing sense lines, is it better to hav them as close as possible to DUT or afer the decoupling capacitors ? Force in red, sense in purple. Best way is 1 or 2 ? Thanks in advance and Merry Christmas to everybody ! Full Article
ca A problem with setup when Monte Carlo simulation starts By community.cadence.com Published On :: Thu, 24 Oct 2024 17:50:42 GMT Hi, When I try to run Monte Carlo it gives me a 3 items message for possible failure: 1. It says the machine selected in the current job setup policy isnot reachable 2. The Cadence hierarchy is not detected, not installed properly. or 3. Job start script (with a path and a name like swiftNetlistService#) is not found on the remote machines. Any recommendation on how to fix this? Full Article
ca New CDF creation and callback By community.cadence.com Published On :: Sun, 27 Oct 2024 11:35:08 GMT I need to add a new CDF parameter called "mag" to symbols in a given library using skill script in which the symbol size can be controlled and call back it each time this library is used so that all the symbols are updated. Full Article
ca Cannot access individual noise contributions using SpectreMDL By community.cadence.com Published On :: Tue, 29 Oct 2024 12:21:23 GMT I have tried replicating the setup described in a previous post (here), with the proposed solution. The MDL measurements return a value of 0 for all exported result but the first. Using Viva I can actually see the correct value for each contribution. I am using :- Spectre 23.1.0.538.isr10- Viva IC23.1-64b.ISR8.40 What should I do differently? Thanks! ***** test.scs ***** r1 (1 0) res_model l=10e-6 w=2e-6 r2 (2 1) res_model l=15e-6 w=2e-6 vr (2 0) vsource dc=1.0 mag=1 model res_model resistor rsh=100 kf=1e-20*exp(dkf) parameters dkf=0 statistics { process { vary dkf dist=gauss std=0.5 } } noi (1 0) noise freq=1 /***** test.mdl *****/ alias measurement noi_test { run noi; export real noi_total=noi_test:out; export real r1_total=r1:total; export real r1_flicker=r1:fn; export real r1_thermal=r1:rn; export real r2_total=r2:total; export real r2_flicker=r2:fn; export real r2_thermal=r2:rn; } run noi_test **** test.measure **** Measurement Name : noi_testAnalysis Type : noisenoi_total = 6.9282e-06 r1_flicker = 0 r1_thermal = 0 r1_total = 0 r2_flicker = 0 r2_thermal = 0 r2_total = 0 Full Article
ca How can I place stacked vias with the size exact same cut width without metals around? By community.cadence.com Published On :: Wed, 30 Oct 2024 12:40:16 GMT How can I place stacked vias with the size exact same cut width without metals around?As the red part only in the image below? Full Article
ca Verilog-A: Can I ignore WARNING (VACOMP-1047) By community.cadence.com Published On :: Thu, 31 Oct 2024 22:26:29 GMT I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics. Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va), mod2 (inside an external file mod2.va), and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module. At the bottom of the module I use "`include mod1.va", "`mod2.va", etc. When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning: Warning from spectre during AHDL compile. WARNING (VACOMP-1047): The Verilog-A file contains more than one module definition. ADE can process only one module per Verilog-A file. Put only one module in each Verilog-A file so that ADE can identify pin names, directions, and hierarchy within each separate module. Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored? Full Article
ca AMS simvision cannot load big psf.trn By community.cadence.com Published On :: Mon, 11 Nov 2024 18:27:49 GMT Hello all, I have run a simulation with a lot of instnaces extraction and the psf.trn is >= 200 Gb, I tried to load it with simvision and it just breaks. I would like to ask if there is a way to open this file, e.g. if I could read only some time window e.g. from 10us -> 15us. getVersion(t) "sub-version ICADVM20.1-64b.500.34 " XCELIUMMAIN23.03.001 thank you in advance Full Article
ca How to Set Up a Config View to Easily Switch Between Schematic and Calibre of DUT for Multiple Testbenches? By community.cadence.com Published On :: Tue, 12 Nov 2024 16:22:53 GMT Hello everyone, I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process. My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run. I would really appreciate it if you could guide me on the following: How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2. Where to specify view priorities or other settings to control which view is used during simulation. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches. Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views. Thank you so much for your time and assistance! Full Article
ca incorrect output of multiplication in jaspergold By community.cadence.com Published On :: Fri, 16 Feb 2024 10:02:22 GMT I want to use jaspergold to formally verify functionality of my custom multiplier. I am computing the expected result using A*B to check against output of my multiplier. Here, A and B are two logic signed operands. However, jaspergold is performing the operation A*B incorrectly. I have reproduced this issue using the attached example. JasperGold compiles and elaborates the module and subsequently runs a formal proof. The tool raises a counterexample to assertion whose screenshot is attached below: I simulated the same example using xrun and it was giving the correct product output in simvision waveform. Please help me resolve this issue. I am using 2023.03 version of Jasper Apps. Thanks and regards Anubhav Agarwal Full Article
ca Is it possible to automatically exclude registers or wires that are not used from toggle coverage? By community.cadence.com Published On :: Wed, 03 Jul 2024 12:04:29 GMT Hello, I have a question about toggle coverage. In my case, there are many unused registers or wires that are affecting the toggle coverage score negatively. Is it possible to automatically exclude registers or wires that are not used from toggle coverage? My RTL code is as follows, Is it possible to automatically disable tb.top1.b and tb.top1.c without using an exclude file? module top1; reg a; reg b; reg [31:0] c; initial begin #1 a=1'b0; #1 a=1'b1; #1 a=1'b0; end endmodule module tb; top1 top1(); endmodule Full Article
ca Issues related to cadence xrun command By community.cadence.com Published On :: Thu, 08 Aug 2024 06:47:05 GMT We are trying to run compilation, elab and sim with command xrun -r -u alu, where alu is one of the units to execute. we are getting the following errors.1) xmsim: *E,DLMKDF: Unable to add default DEFINE std /home/xxxx/Cad/xcelium/tools/inca/files/STD. xmsim: *E,DLMKDF: Unable to add default DEFINE synopsys /home/xxxx/Cad/xcelium/tools/inca/files/SYNOPSYS 2) xmsim: *W,DLNOHV: Unable to find an 'hdl.var' file to load in. What is the purpose of hdl.var3) xmsim: *F,NOSNAP: Snapshot 'alu' does not exist in the libraries. I cannot see in log files, which libraries is it referring to?? Any one request you to help on how to debug these. Full Article
ca Archive of Tools Classification Analysis (Xcelium) By community.cadence.com Published On :: Tue, 05 Nov 2024 16:19:01 GMT Hi, Current and valid TCAs for Functional Safety are readily available at the FuSa "one-stop shop". But I have not been able to find any archive repository for access to the obsoleted versions. I would need to have also v1.4 of Xcelum TCA to investigate exact changes wrt previous projects. Anyone knows how to find it? Best regards, Lars Full Article
ca help for $sscanf By community.cadence.com Published On :: Fri, 22 Apr 2016 04:03:22 GMT Can anyone tell me how i can supress few strings or integers while reading with $sscanf. I read a line from a file into a string. there are few strings and integers seperated by white spaces in the line. I am interested in one string which comes at postion 5 in the line. how can i suppress all other strings and integers with $scanf. i tried the following syntax but it dint work. $sscanf(line,"* * * * %s",string_arg); i am tring to supress first 4 integers/strings in the line. Full Article
ca X-FAB's Innovative Communication and Automotive Designs: Powered by Cadence EMX Planar 3D Solver By community.cadence.com Published On :: Sun, 31 Jul 2022 17:01:00 GMT Using the EMX solver, X-FAB design engineers can efficiently develop next-generation RF technology for the latest communication standards (including sub-6GHz 5G, mmWave, UWB, etc.), which are enabling technologies for communications and electric vehicle (EV) wireless applications. (read more) Full Article EM Analysis electromagnetics in-design analysis reference design Electromagnetic analysis PDK foundry
ca Cadence at IMS 2022 By community.cadence.com Published On :: Tue, 02 Aug 2022 01:49:00 GMT RF Design Solutions for Next-Generation Products The International Microwave Symposium (IMS2022), otherwise known as Microwave Week, was recently held (June 19-24) at the Denver Convention center, returning to its long-standing g...(read more) Full Article 5G RF IMS in-design analysis Electromagnetic analysis microwave design microwave office thermal
ca Japan Aviation Electronics is First to Support IP Protected Models for Cadence Clarity 3D Solver By community.cadence.com Published On :: Tue, 16 Aug 2022 04:08:00 GMT With the latest release (Sigrity and Systems Analysis 2022.1 HF2) of Clarity 3D Solver, support for encrypted component models is now available. With this functionality, vendors that supply 3D components, such as connectors, can now merge their...(read more) Full Article connector EM Clarity 3D Solver Systems Analysis JAE
ca BoardSurfers: Managing Silkscreen Data Using Allegro 3D Canvas By community.cadence.com Published On :: Wed, 24 Aug 2022 13:30:00 GMT The silkscreen layer plays a crucial role in the assembly, repair, and testing of a PCB. You can add a variety of information to this layer, such as the location of the components, polarity, component orientation, on-off switches, LEDs, and testpoint...(read more) Full Article 17.4 BoardSurfers 3D Canvas 17.4-2019 Allegro PCB Editor silkscreen Allegro
ca Quickchat Video Interview: Introducing Cadence Optimality and OnCloud for Systems Analysis and Signoff By community.cadence.com Published On :: Tue, 30 Aug 2022 15:05:00 GMT Microwaves & RF's David Maliniak interviews Sherry Hess of Cadence about recently announced products of Optimality and OnCloud.(read more) Full Article SaaS in-design analysis optimization multiphysics
ca EMX - Localised back etching By community.cadence.com Published On :: Wed, 07 Feb 2024 10:40:26 GMT Do you know if it is possible to define localized back etching (LBE) in EMX? It should be associated to a layer which defines the holes done in the substrate. I've not found any reference for this in the .proc syntax. --> Answer found. This is not possible because EMX considers the same dielectric in all x-y plane Full Article
ca HB: duplicated frequencies in 3-tone simulation By community.cadence.com Published On :: Fri, 09 Aug 2024 11:51:48 GMT I get multiple results at the same frequency in a 3-tone simulation. I try to determine the IP3 of a mixer. I have 3 large signal tones: 0.75 GHz, 1.25 GHz and 1.26 GHz. At the IM3 frequency of 490 MHz I observe 4 results, see also the screenshot of the table output. The frequencies are exactly the same (even when I subtract 490 MHz by using xval() ). Which of the values do I have to use to determine the correct IP3? Is there an option to merge these results? Full Article
ca Virtuoso ICADVM20.1 ISR26 and IC6.1.8 ISR26 Now Available By community.cadence.com Published On :: Fri, 08 Jul 2022 13:52:00 GMT The ICADVM20.1 ISR26 and IC6.1.8 ISR26 production releases are now available for download.(read more) Full Article Analog Design Environment Cadence blogs ICADVM18.1 ADE Explorer cadence Virtuoso RF Solution IC Release Announcement blog Virtuoso Visualization and Analysis XL Layout EXL Virtuoso Analog Design Environment IC Release Blog Custom IC Design Custom IC IC6.1.8 ADE Assembler Virtuoso Layout Suite XL
ca Virtuosity: Custom IC Design Flow/Methodology - Circuit Physical Verification & Parasitic Extraction By community.cadence.com Published On :: Fri, 29 Jul 2022 18:26:00 GMT Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve this.(read more) Full Article design rule violations Extraction Layout versus schematic Physical Verification System (PVS) Virtuoso Quantus Extraction Solution PVS Custom IC Design parasitics
ca Virtuoso ICADVM20.1 ISR27 and IC6.1.8 ISR27 Now Available By community.cadence.com Published On :: Wed, 24 Aug 2022 11:50:00 GMT The ICADVM20.1 ISR27 and IC6.1.8 ISR27 production releases are now available for download.(read more) Full Article Analog Design Environment Cadence blogs ICADVM18.1 ADE Explorer cadence Virtuoso RF Solution IC Release Announcement blog Virtuoso Visualization and Analysis XL Layout EXL Virtuoso Analog Design Environment ICADVM20.1 IC Release Blog Custom IC Design Custom IC IC6.1.8 ADE Assembler Virtuoso Layout Suite XL
ca Place replicate update default behaviour By community.cadence.com Published On :: Mon, 04 Nov 2024 07:39:41 GMT The default behaviour of Place replicate update is to select every new net item connected to the replicate module. This leads to an abundant number of clines, vias and shapes being selected, most of which I don't want to add to the replicate group. It is very tedious to unselect all these items and more often than not, I miss one or two items and then end up with a via or cline in a completely different place on the board or outside of the board. Is there a way to change this rather annoying behaviour? I haven't found any way to disable it or to batch deselect everything the tool has decided to add to the replicate group. The question has been asked before, but it didn't get any answers and the thread is now locked. /F Full Article
ca Update Package_Height_Max from Orcad Capture By community.cadence.com Published On :: Wed, 06 Nov 2024 16:05:50 GMT I am using OrCAD PCB Designer Standard version 17.4-2019. I want to force update the Package_Height_Max property on the place bound top shape. The footprint library that we've created has that property set in the dra file, but I'd like to override that from capture so I can be certain that the height is correct. This is coming from a place where we have created a very large footprint library over that past ++ years. Everyone who creates a new footprint is supposed to make sure that we add Package_Height_Max to the footprint, but of course footprints get reused for various parts, not all of which will have the same package height. What I want to do is export a list of package heights from our part database and then import the package heights into Capture and override the package height in the footprint. I have found a post here Using Height Property from Orcad Capture which says its not possible, but it also says its from 15 years ago, so maybe things have changed? Full Article