ca scaling a footprint By community.cadence.com Published On :: Thu, 07 Nov 2024 00:49:52 GMT hello is there a way to scale a footprint of a symbol? scaling a footprint means moving all the pad locations of the symbol by +x% or -x%. regards masa Full Article
ca how can load the Dll files and use it in Allegro 16.6 By community.cadence.com Published On :: Thu, 07 Nov 2024 05:52:05 GMT Hello everyone! Have you ever used the axlDllOpen function for Allegro 16.6? It doesn't work for me. Please give me your solution.Thank you. HoangKhoi Full Article
ca How to perform the reflection and crosstalk using the OrCAD X Professional By community.cadence.com Published On :: Sun, 10 Nov 2024 14:39:08 GMT Dear Community, I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other. I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1. I want to create a topology flow to the PCB layout and perform the reflection and crosstalk. Regards, Rohit Rohan Full Article
ca How to store the workspace designs and projects in local directory By community.cadence.com Published On :: Sun, 10 Nov 2024 14:54:48 GMT Dear Community, In OrCAD X Profession, the workspace feature enables the users to store the libraries (Schematic Symbol, Footprint and PSpice Models) and Designs (Schematic and PCB layout) in the cloud workspace. But storing these libraries and design are stored in servers in the USA, Europe, Asia and Japan Servers. I don't want to store my designs in any of these servers instead I want to create the workspace in my local PC and store all my libraries and designs in the local workspace. Is this possible, if possible then can anyone provide the steps/procedure or videos of how to do it? Regards, Rohit Rohan Full Article
ca How to resolve the impedance issue using the OrCAD X Professional By community.cadence.com Published On :: Sun, 10 Nov 2024 14:59:59 GMT Dear Community, I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional. Regards, Rohit Rohan Full Article
ca What is difference between the Cadence OrCAD / Allegro 24.1 with the Altium Designer 24 By community.cadence.com Published On :: Sun, 10 Nov 2024 15:07:37 GMT Hai Community, What are the differences between the Cadence OrCAD / Allegro 24.1 with the Altium Designer 24. Can I get the grid matrix difference between these two tools? Regards, Rohit Rohan Full Article
ca Socionext Accelerates SoC Design Breakthroughs with Cadence Signoff Tools By community.cadence.com Published On :: Thu, 27 Jun 2024 18:16:00 GMT Socionext, a leader in SoC design, recently made significant strides in enhancing its design efficiency for a complex billion-gate project. Faced with the initial challenges of lengthy eight-day iterations and a protracted two-month timing signoff process, the objective was to reduce the iteration cycle to just three days. By integrating Cadence's cutting-edge solutions—Certus Closure Solution, Tempus Timing Solution, and Quantus Extraction Solution—Socionext achieved remarkable improvements. Notably, the Tempus DSTA tool dramatically cut timing closure time by 73%, outperforming conventional single-machine STA methods. This achievement, combined with the synergistic use of Cadence's Certus Closure and Tempus Timing solutions, allowed Socionext to meet their ambitious three-day iteration target and double productivity. Additionally, integrating these solutions significantly decreased both human and machine resource needs, slashing memory and disk costs by up to 90% and halving engineering resources during the optimization and signoff phases. For more on this collaboration, check out the "Designed with Cadence" success story video on Cadence's website and YouTube channel. Also, don't miss the on-demand webinar "Fast, Accurate STA for Large-Scale Design Challenges," which provides a deeper dive into Socionext's breakthroughs and the innovative solutions that powered their success. Full Article digital design Tempus designed with cadence certus Quantus silicon signoff
ca Training Bytes: Explore Cadence DFT Synthesis Flow with Bytes By community.cadence.com Published On :: Wed, 24 Jul 2024 19:53:00 GMT Training Bytes are not just short technical videos; they are particularly designed to provide comprehensive support in understanding and learning various concepts and methodologies. These comprehensive yet small Training Bytes can be created to show various concepts and processes in a shorter pane of five to ten minutes, for example, running DFT synthesis, scanning insertion, inserting advanced testability features, test point insertion, debugging DFT violations, etc. In this blog, we will show you the DFT Synthesis Flow with Cadence's Genus Synthesis Solution using small Training Bytes available on the Cadence Learning and Support Portal. To explore these training bytes more, log on to support.cadence.com and select the learning section to choose the training videos, as shown below. DFT Synthesis Flow with Genus Synthesis Solution First, we will understand the Synthesis Flow with DFT in the Genus Synthesis Solution: Understanding a Script File that Used to Run the Synthesis Flow With DFT Here, we will show you "How to run the Test Synthesis Flow to Insert Scan Chains and Improve the Testability of a Design" in the Genus Synthesis Solution: Running Test Synthesis Flow to Insert Scan Chains And Improve the Testability of a Design in the Genus Synthesis Solution Let's check the flops marked with the dft_mapped attribute for scan mapping in Genus Synthesis Solution: How to Check Flops Marked With dft_mapped Attribute For Scan Mapping in Genus Synthesis Solution? How to Find Non-Scan Flops of a Design in Genus? (Video) Once the flops are mapped to scan flip flops and the scan chain inserted, we will see how to handle the flops marked with the dft_dont_scan attribute for scan mapping in Genus Synthesis Solution. How to Handle the Flops Marked With the dft_dont_scan Attribute For Scan Mapping in Genus Synthesis Solution? Here, we will see how to fix DFT Violations using the command fix_dft_violations: Fixing DFT Violations (Video) Once the design has been synthesized, let's explore the DFT design hierarchy in Genus Stylus CUI: Exploring DFT Design Hierarchy in Genus Stylus CUI (Video) Understand why sequential elements are not mapped to a scan flop: Why Are Sequential Elements Not Mapped to a Scan Flop? Explore hierarchical scan synthesis in Genus Stylus Common UI: Understanding Hierarchical Scan Synthesis in Genus Stylus Common UI. (Video) To understand how to resolve different warnings and errors (for example, DFT-415, DFT-512, DFT-304, etc.) in Genus Synthesis Solution, here are some videos you can refer to: How to Resolve Warning: DFT-415 (Video) How to Resolve Error: DFT-407 (Video) How to Resolve Error: DFT-404 (Video) DFT-510 Warning During Mapping (Video) How to Resolve Warning: DFT-512 (Video) How to Resolve Warning: DFT-511 (Video) How to Resolve Warning: DFT-304 (Video) How to Resolve Warning: DFT-302 (Video) How to Resolve Error: DFT-515 (Video) How to Resolve Error: DFT-500 (Video) Here, we will see how we can generate SDC constraints for DFT constructs for many scan insertion techniques, such as FULLSCAN, OPCG, Boundary Scan, PMBIST, XOR Compression, SmartScan Compression, LBIST, and IEEE 1500: How to Generate SDC Constraints for DFT Constructs in Genus Synthesis Solution? (Video) Explore advanced testability features that can be inserted in Genus Synthesis Solution, such as Boundary Scan, Programmable Memory built-in Self-Test Logic (PMBIST), Compression Logic, Masking, and On-Product Clock Generation Logic (OPCG): Advanced Testability Features (Video) To understand What the IEEE 1500 Wrapper and its Insertion Flow in Genus Synthesis Solution, follow the bytes: What Is IEEE 1500 Wrapper? (Video) IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution (Video) Understand the On-product Clock Generation (OPCG) insertion flow in Genus Synthesis Solution Stylus CUI with this byte: Understanding On Product Clock Generator (OPCG) Insertion in Genus Stylus CUI (Video) To debug DFT violations, you can use DFT Analyzer from Genus GUI and explore its features here: Debugging Using GUI: DFT Analyzer (Video) Exploring DFT Analyzer View of Genus Synthesis Solution GUI (Video) To understand What is Shadow Logic, How to Insert Test Points, How to do Testability Analysis Using LBIST, and How to Deterministic Fault Analysis in Genus, follow this article: What is Shadow Logic To insert the Boundary Scan Logic in and control Boundary Optimization in Genus Synthesis Solution, refer to these small bytes: How to Insert Boundary Scan Logic in Genus? Video) Controlling Boundary Optimization in Genus Synthesis Solution Stylus CUI (Video) Compression techniques are used during scan insertion to reduce the test data volume and test application time (TAT) while retaining the test coverage. To understand what compression and the compression techniques are, watch this article: What is Compression Technique During Scan Insertion? (Video) Interested to know what "Unified Compression" is? To get the concept, you can watch this small demo: What Is Unified Compression? (Video) To Explore More, Register for Online Training Log on to Cadence.com with your registered Cadence ID and password. Select Learning from the menu > Online Courses. Search for "Test Synthesis with Genus Stylus Common UI" using the search bar. Select the course and click "Enroll." Full Article DFT Modus DFT IEEE 1500 Genus Synthesis Solution
ca Technical Webinar: A Beginner’s Guide to RTL-to-GDSII Front-End Flow By community.cadence.com Published On :: Wed, 21 Aug 2024 06:23:00 GMT In this training webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. We will guide you through the essential steps in creating integrated circuits, the building blocks of modern electronics. We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore: Key concepts of specifying chip behavior and performance How to translate ideas into a digital blueprint and transform that into a design How to ensure your design is free of errors This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow. When Is the Webinar? Date and Time Wednesday, September 18, 202407:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing REGISTER To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System. Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details. If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help. For inquiries or issues with registration, reach out to eur_training@cadence.com.For inquiries or issues with registration, reach out to eur_training@cadence.com. To view our complete training offerings, visit the Cadence Training website. Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe. Want to Learn More? This link gives you more information about the related training course and a link to enroll: Cadence RTL-to-GDSII Flow Training The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training. The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training. Also, take this opportunity to register for the free Online Trainings related to this webinar topic. Cadence RTL-to-GDSII Flow Xcelium Simulator Verilog Language and Application Xcelium Integrated Coverage Related Training Bytes How to Run the Synthesis Without DFT? How to Run the Synthesis Flow with DFT? (Video) Related Blogs Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available! Training Insights – Why Is RTL Translated into Gate-Level Netlist? Training Bytes: They May Be Shorter, But the Impact Is Stronger! Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available! Full Article COS IMC IC DFT Integrated Metrics Center IP chip design webinars verification engineers Xcelium Logic Simulator training Mixed-Signal Logic Design coverage analysis RTL-to-GDSII FrontEnd training bytes system verilog Freshly Graduate Cadence RTL-to-GDSII Flow Technical webinar RTL2GDSII RTL design online training HLS VHDL vManager Verisuim
ca The Best Way to Learn – Cadence Cerebrus AI-Driven Design Implementation By community.cadence.com Published On :: Tue, 17 Sep 2024 04:49:00 GMT The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet the power, performance, and area (PPA) goals in a completely automated way. Use Cerebrus Apps to optimize some aspects of the design as well. Running a full RTL to GDSII flow, Cadence Cerebrus has a lot of possibilities and combinations of different tool settings to explore. Using the knowledge from previous runs, combined with on-the-fly analysis within the flow, Cadence Cerebrus can assess many settings combinations and fine-tune the flow accordingly in a very efficient manner. As technology advances, projects become bigger and way more complex than before. The ability of a single engineer to run simultaneously a large number of blocks in a traditional way is limited. Cadence Cerebrus allows a single engineer to work more efficiently and implement more blocks, while maintaining the same or even better PPA, using compute power. Being such a revolutionary tool, integrating Cerebrus into your existing flow is surprisingly simple as it can wrap around any existing flow scripts. Please join me in this course, to learn about the features and basics of Cadence Cerebrus Intelligent Chip Explorer. We’ll walk through the tool setting stage, explain what is a primitive and how it effects our run, talk about the cost function and the run goals. We’ll understand the concept of scenarios, learn how to analyze the results of the different runs, and compare them. In addition, we’ll talk about basic debug rules and methods to analyze failures. Sounds Interesting? Please join our “live” one-day Cadence Cerebrus Intelligent Chip Explorer Training @Cadence Feldkirchen planned for October 9th, 2024! For more details and registration, please contact Training Germany. If you would like to have an instructor-led training session in another region please contact your local training department. Become Cadence Certified Cadence Training Services offers a digital badge for this training course. This badge indicates proficiency in a certain technology or skill and gives you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding this digital badge to your email signature or any social media platform, such as Facebook or LinkedIn. Related Training Innovus Block Implementation with Stylus Common UI Related Training Bytes Cerebrus Primitives (Video) How to Reuse Cerebrus (Video) Cerebrus - Verifying Distribution Script (Video) How to distribute Cerebrus Scenarios (Video) Cerebrus Web Interface Monitor and Control (Video) How to Setup Cerebrus for a Successful Run (Video) Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have (Webinar) (Video) Cerebrus Cost Functions (Video) Related Blogs Training Insights: Cadence Cerebrus Webinar Recording Now Available! Keep Up with the Revolution—Cadence Cerebrus Training New to Equivalence Checking? Restart from the Basic Concepts Training Insights - Free Online Courses on Cadence Learning and Support Portal Training Insights – Important Facts You Should know About Our Cadence Learning and Support Portal Full Article digital badge live training cerebrus Cadence training cadence learning and support
ca Training Insights: Cadence Certus Closure Solution Badge Now Available! By community.cadence.com Published On :: Fri, 18 Oct 2024 17:22:00 GMT This blog informs about the new badge certification available for Cadence Certus Closure Solution, that grants credit to your proficiency.(read more) Full Article digital badge Cadence Certus Cadence Online Support Cadence training certus cadence learning and support
ca A Magical World - The Incredible Clock Tree Wizard to Augment Productivity and QoR! By community.cadence.com Published On :: Mon, 11 Nov 2024 13:00:00 GMT In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process. The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design. This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC) One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability. This incredible feature is part of the Joules RTL Design Studio. How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio? Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio. Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc. You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard. You can refer to the videos on Cadence Online Support (Cadence login required). Video Links: Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) Want to learn more? Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required). Related Resources Related Training Bytes: Understanding Prototype Design Flow in Joules RTL Design Studio (Video) Running Prototype Implementation Flow in Joules RTL Design Studio (Video) Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video) Related Courses: Joules Power Calculator Want to Enroll in this Course? We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. Please don't forget to obtain your Digital Badge after completing the training. Related Blogs: Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit! - Digital Design - Cadence Blogs - Cadence Community Joules RTL Design Studio: Accelerating Fully Optimized RTL - Digital Design - Cadence Blogs - Cadence Community Let's Replay the Process of Power Estimation with the Power of 'x'! - Digital Design - Cadence Blogs - Cadence Community Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community Full Article performance debug training congestion PPAC training bytes clock tree synthesis area RTL design power
ca American Cities of the Future 2019/20 - the winners By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Mon, 10 Jun 2019 08:24:30 +0100 New York continues to reign as leader of fDi’s American Cities of the Future 2019/20 ranking. San Francisco retains second place with Toronto rising to third. Naomi Davies reports. Full Article
ca American Cities of the Future 2019/20 – FDI strategy By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Mon, 10 Jun 2019 08:25:52 +0100 A more detailed look at fDi's judges’ top five American Cities of the Future 2019/20 for FDI strategy. Naomi Davies reports. Full Article
ca Fintech Locations of the Future 2019/20: London tops first ranking By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 15 Aug 2019 12:00:49 +0100 London has been named fDi’s inaugural Fintech Location of the Future for 2019/20, followed by Singapore and Belfast. Full Article
ca Tourism Locations of the Future 2019/20 – FDI Strategy By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Mon, 09 Dec 2019 08:33:03 +0000 Australia tops the FDI Strategy category of fDi's Tourism Locations of the Future 2019/20 rankings, followed by Costa Rica and Azerbaijan. Full Article
ca EBRD president looks to African expansion By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 12 Dec 2019 12:01:14 +0000 The EU is considering a broader mandate for the EBRD, and its president, Sir Suma Chakrabarti, believes its model would work in sub-Saharan Africa. Full Article
ca View from the Middle East & Africa: small steps can have a big impact on tourism By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 12 Dec 2019 12:01:06 +0000 Poor infrastructure and political instability deter tourism, but small and manageable steps to avoid chaos and promote hospitality can work wonders. Full Article
ca Will mobile phone penetration maintain African momentum? By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:20:18 +0000 Sub-Saharan Africa is the world’s fastest growing mobile phone market, but how can telecoms companies make the most of the huge opportunities the region provides? Full Article
ca View from Middle East and Africa: SDGs need rich to support the poor By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:24:27 +0000 The UN Sustainable Development Goals aim to end global poverty, but poorer countries are struggling to hit them. More help from richer countries is crucial, writes Mazdak Rafaty. Full Article
ca How the Suez Canal Economic Zone is aiding Egypt's economic resurgence By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:13:41 +0000 Combining a strategic location with an investor-friendly environment, Egypt is ensuring its Suez Canal Economic Zone is primed for foreign investment. Full Article
ca A green future for Cape Town’s Atlantis By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 16 Apr 2020 13:04:10 +0100 Atlantis in South Africa has a new SEZ focused on green manufacturing, which is hoping to turn around the area's fortunes. Annie Hessler reports. Full Article
ca UK strengthens ties to Africa By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 20 Feb 2020 11:25:25 +0000 London event hears how the UK export credit agency is increasing its focus on trade with African countries. Jason Mitchell reports. Full Article
ca Mara's Phones makes African manufacturing a priority By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 12 Dec 2019 12:01:24 +0000 Having opened new production facilities in Rwanda and South Africa, Mara Phones is looking to alter Africa's mindset from being a 'consumer' to being a 'manufacturer'. Full Article
ca Reforms could unlock African development, reports McKinsey By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Mon, 11 Nov 2019 10:34:15 +0000 Continued African development could hinge on public finance reforms. Full Article
ca Passion Capital partner puts faith in London fintech scene By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 12 Dec 2019 12:01:12 +0000 Passion Capital's Eileen Burbidge talks to fDi about what fintech companies should consider when expanding internationally, and why London will always be a key market in the sector. Full Article
ca Group effort helps The Fresh Market stay local By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 16 Apr 2020 13:04:20 +0100 Financial incentives from two different cities persuaded US grocery chain The Fresh Market to stay headquartered in its home state of North Carolina. Full Article
ca US-Iran feud casts new investment shadow over Middle East By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 09 Jan 2020 12:53:15 +0000 FDI levels have already fallen throughout Iran's main sphere of influence in the region. Full Article
ca Emerging markets predicted to spearhead GDP growth over next decade By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 14 Jan 2020 11:24:32 +0000 Lower fertility rates will boost economic growth, according to a demographic model developed by Renaissance Capital. Full Article
ca India invites foreign capital By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 20 Feb 2020 10:41:47 +0000 India’s 2020 budget continues the process of opening up to overseas investment. Full Article
ca fDi Index: investors carried weak sentiment into January as coronavirus threat emerged By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 12 Mar 2020 10:56:11 +0000 Announced greenfield projects into China plummeted in early 2020 with the US and Europe taking the lion's share of global foreign investment. Full Article
ca AstraZeneca expands further into China’s biotech sector By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Mon, 18 Nov 2019 10:44:42 +0000 AstraZeneca will set up a R&D centre and an AI innovation centre in Shanghai, as well as create a $1bn fund that would invest in healthcare start-ups. Full Article
ca Zonamerica looks beyond Latin America for expansion opportunities By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Mon, 16 Dec 2019 10:05:06 +0000 Uruguay-based Zonamerica has successfully expanded into Colombia and China, and is now looking to export its model to other parts of Asia and Africa. Full Article
ca View from the Americas: the evolving political economy of FDI By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 12 Dec 2019 12:00:59 +0000 We are currently in a state of heightened business and economic disruption and sociopolitical activism, which only looks set to intensify. Full Article
ca Jamaican tourism minister seeks to explode myths By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 12 Dec 2019 16:15:01 +0000 Edmund Bartlett, Jamaica’s minister of tourism, talks about key investment opportunities and the need for better international reporting when natural disasters strike. Full Article
ca The winners and losers of the USMCA By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:24:48 +0000 Early reports on the new trade agreement between the US, Mexico and Canada – known as the USMCA – suggest that the US is getting the better end of the deal. But what are the implications of the new rules of origin? Full Article
ca Microsoft makes a crossborder connection in North America By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:24:36 +0000 While governments grow more protectionist over trade and physical borders, companies such as Microsoft are bridging the gap by funding international collaborative enterprises. Full Article
ca View from the Americas: time for action on SDGs By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:24:16 +0000 Giant investment firm BlackRock throwing its weight behind sustainability issues is sending a signal to the corporate world to respond urgently to global calls for action, writes Gregg Wassmansdorf. Full Article
ca How venture capital helps start-ups expand globally By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:23:25 +0000 Venture capital funding has reached record levels in recent years, enabling start-ups to expand across borders – but their ability to do this depends on their type of business, and where they are founded. Full Article
ca Latin America embraces China's Belt and Road with enthusiasm By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 25 Feb 2020 13:20:49 +0000 Up to 18 countries across Latin America have joined China’s new Belt and Road Initiative, hoping to boost their infrastructure development and investment. Full Article
ca View from Europe: will European investment go local? By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 16 Apr 2020 13:04:13 +0100 Long-dominant global supply chains look less tenable in the light of pressures ranging from pandemics to disasters, trade tensions and protectionism. Full Article
ca Dublin tops European HQ location rankings By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 16 Apr 2020 13:04:08 +0100 The UK is the top country, but Dublin is leading city, for foreign companies setting up headquarters in Europe, according to fDi’s ranking. Full Article
ca Global pharmaceutical FDI on an upward trend By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Tue, 31 Mar 2020 17:24:03 +0100 The global pharmaceutical sector has seen consistent growth since 2014, with western Europe a major beneficiary. Full Article
ca UK firm targets booming medicinal cannabis market By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 16 Apr 2020 13:04:02 +0100 Eco Equity is one of only a few Europe-based investors in medicinal cannabis from Africa and the Caribbean, an area in which the UK is missing an opportunity, according to CEO Jon-Paul Doran. Full Article
ca View from Middle East and Africa: UAE moves fast to combat Covid-19 By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 16 Apr 2020 13:04:01 +0100 The UAE followed Singapore’s swift reaction to combat Covid-19, to preserve the health of its citizens. Now moves are in place to tackle the country’s economic wellbeing. Full Article
ca View from the Americas: new perspectives in a time of pandemic By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 16 Apr 2020 13:03:51 +0100 The coronavirus pandemic could change human behaviour more permanently in future. Full Article
ca Latin America prepares for sharp drop in FDI amid coronavirus pandemic By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Wed, 08 Apr 2020 13:03:41 +0100 The fallout from the pandemic looks set to stall trade and investment to Latin America. Full Article
ca Can the largest fossil fuel financiers change? By master-7rqtwti-2nwxk3tn3ebiq.eu-2.platformsh.site Published On :: Thu, 29 Oct 2020 16:13:03 +0000 JPMorgan has pledged to push clients towards aligning with the Paris Agreement Full Article
ca The death list: These cars have been discontinued for 2025 By www.thecarconnection.com Published On :: Fri, 08 Nov 2024 11:50:00 -0500 We're already deeply into the discovery phase of the 2025 model year. With it, as usual, have come a stellar crop of new vehicles—everything from the high and mighty Chevy Corvette ZR1 to the cheeky, efficient Honda Civic Hybrid. But on the sadder end of the spectrum, we're tallying the list of vehicles that didn't make the cut—the... Full Article
ca Cadillac discontinues XT4 crossover SUV By www.thecarconnection.com Published On :: Fri, 08 Nov 2024 11:59:00 -0500 The XT4 compact crossover ends production in January after one generation The Cadillac Optiq electric crossover will take the place as the entry point into the Cadillac brand Production of the XT4 ends not longer after it ended on the Chevy Malibu as GM retools its Fairfax Assembly for the next Bolt EV A year after an interior glow-up, Cadillac... Full Article