A previous article shows a simulation of two different models of a foraging animal. The first model is a random walk, which assumes that the animal chooses a random direction, then takes a step that is distributed according to a Gaussian random variable. In the second model, the animal again [...]

The post Levy flight and vectorizing a simulation in SAS appeared first on The DO Loop.

Fight back against sophisticated money launderers with these 3 techniques.

The post 3 techniques to improve AML transaction monitoring strategies appeared first on The Data Roundtable.

With containers, you can build once, run anywhere – no worries about underlying dependencies.

The post How containers have moved us to next-gen virtualization appeared first on The Data Roundtable.

Having the right data analytics platform can help law enforcement solve crimes faster.

The post 5 technology considerations for law enforcement appeared first on The Data Roundtable.

The explosion occurred in Telangana Spice Kitchen on Road Number One Jubilee Hills. According to police, the explosion damaged the boundary wall of the hotel.

A Delhi government report has attributed nearly 24 per cent of the total about 89,000 deaths registered in the national capital in 2023 to infectious and parasitic diseases like cholera, diarrhoea, tuberculosis and hepatitis B, among others.

Power discoms have provided electricity connections to 6,791 of the 10,802 applicants living in Delhi's unauthorised colonies following Lieutenant Governor V K Saxena's intervention, the Raj Niwas said on Tuesday.

The results for the Delhi University Students' Union elections will be declared on November 21, almost two months after the polls were held, according to university officials.

Born in a poor village, Algerian boxer Imane Khelif has overcome numerous obstacles throughout her life to win a controversial Paris Olympics gold on Friday.

Abdul Ghafoor Noorani, eminent constitutional expert, lawyer and author, died today at the age of 93. A noted scholar on Jammu and Kashmir, his absence is being felt in the Union Territory, where many are mourning him.

Liam Payne, who rose to fame as a member of the boy band One Direction has died at the age of 31. The British singer fell to his death from the third-floor balcony of Hotel CasaSur Palermo in Buenos Aires, Argentina.

US President-elect Donald Trump has named Mike Waltz, a Congressman from Florida and co-chair of the India Caucus, as the new National Security Adviser.

1. South Africa vs India Match Prediction - Who will win today’s 3rd T20I match between SA vs IND?  CricTracker
2. SA look to break spin stranglehold while India worry about depth  ESPNcricinfo
3. South Africa vs India 3rd T20 Playing 11, live match time (IST), streaming  Business Standard
4. Time running out for Abhishek, Avesh as Ramandeep-Vyshak waiting in wings: India vs South Africa 3rd T20I Probable XIs  Hindustan Times
5. India, SA eye series lead in Centurion before decisive T20I in Johannesburg  Cricbuzz

1. Pakistan Government's Firm Stance On Champions Trophy, Report Says PCB Told To...  NDTV Sports
2. ICC in a catch-22 situation amid PCB's steadfast stance on hosting Champions Trophy  Cricbuzz
3. Champions Trophy: PCB wants an explanation in writing from India for refusal to travel  ESPNcricinfo
4. 'Duniya bewakoof hai': Basit Ali gives unique solution to India-Pakistan Champions Trophy stand-off  The Times of India
5. Champions Trophy : Rizwan's welcome message for KL Rahul and Suryakumar  India Today

1. Google Chrome on iPhones gets new features with Drive, Maps integration  Business Standard
2. Stop Using Chrome On Your iPhone, Warns Apple—Millions Of Users Must Now Decide  Forbes
3. 4 new Chrome improvements for iOS  The Keyword
4. Chrome on iOS now lets you search using images and text at the same time  TechCrunch
5. Google rolls out new features in Chrome for iPhone users  Moneycontrol

1. Inflation in nearly half of major states outgrows India's Oct CPI; price pressure steepest in Chhattisgarh  Moneycontrol
2. Retail inflation surges to a 14-month high of 6.2% in October  The Times of India
3. If we exclude vegetable prices, CPI inflation remains in RBI's range: UBI research  The Economic Times
4. Rising food prices are likely to push back beginning of rate cutting cycle  The Indian Express
5. India confident of reaching USD 100 billion trade volume with Russia ahead of 2030 timeline: S Jaishankar  Telegraph India

1. Has AIMIM’s Owaisi, the dark horse in Maharashtra elections, played a winning move?  Hindustan Times
2. Video | Maharashtra Election Will Throw Up Fractured Mandate: A Owaisi's Party Leader  NDTV
3. Owaisi backs Maratha reservation ahead of Maharashtra Assembly polls  India Today
4. Need to fight unitedly by Muslims, Maratha and Dalits: Barrister Owaisi.  Etemaad
5. No one can say Uddhav Thackrey won't go back to BJP: AIMIM  The Times of India

1. Delhi: India's capital chokes as air pollution turns 'severe'  BBC.com
2. Several flights diverted due to low visibility conditions at Delhi airport  The Times of India
3. Delhi's toxic air: Why you should not take your cough lightly  India Today
4. Delhi air pollution: Visibility near-zero amid thick smog; CPCB says AQI 'very poor', IQAir shows 'hazardous' | Details  Hindustan Times
5. Delhi's IGI airport sees flight diversions as season's first dense fog hits national capital  Moneycontrol

If you're an iPhone user, then you might want to check the Chrome app for new updates.

The post Google Adds Some Nifty Features for Chrome on iOS Devices appeared first on Phandroid.

A Bengaluru-based entrepreneur recently took to social media to jokingly explain how his daily commute on bike taxes in the city doubles as an unexpected fitness routine.

The post has sparked a heated debate about Bengaluru's rising rental prices and the need for a cap on deposits.

US-based comedian Austin Nasso is going viral online for his hilarious impersonation of US-President-elect Donald Trump during a fictional visit to India.

IFTTT (If This Than That), a web-based software that automates and connects over 600 online services/software raised a $24M Series C led by Salesforce. Other investors include IBM and the Chamberlain Group and Fenox Venture Capital.

The latest round brings IFTTT’s funding to $63M and it will use the funding proceeds to provide integration for enterprise and IoT services and hiring. In IFTTT’s platform, applets are code/script users need to deploy to integrate two or more services (such Google Drive’s integration with Twitter/Facebook).

Investment in IFTTT reveals that Salesforce is consolidating its presence in enterprise IoT space. It also acquired Mulesoft, an integration platform that rivals Microsoft’s BizTalk.

IBM’s investment in IFTTT is also noteworthy as the former is pushing its IBM Watson IoT platform. The following statement also shows its keen interest in IFTTT.

Other recent investments in IoT companies include $30M Series B of Armis and Myriota's $15M for its IoT satellite-based connectivity platform.

For latest IoT funding and product news, please visit our IoT news section.

Amber Solutions, an IoT product company that sells smart outlets, switches and circuit breakers closed Series A Preferred Stock round of financing that equals $3.3M in gross proceeds. Amber will use the funds to support the commercial development of Amber's core technologies.

One of Amber’s product is solid-state circuit interrupter (GFCI) that basically stops harmful levels of electricity from passing through a person. It operates as a safety device alerting the homeowner of electrocution incidents in real time.

Amber Solutions’ core markets are builders that prepare smart home/smart building ready infrastructure, certified electrical contractors or remodelers, and electrical manufacturers.

Other latest funding news include Owlet’s $24M Series B, Axonize’s $6M Series A round and addition of Deutsche Telekom as its strategic investor, and $30M Series B raised by Palo Alto-based Armis.

Microsoft announced it has acquired Semantic Machines, a conversational AI startup providing chatbots and AI chat apps founded in 2014 having $20.9 million in funding from investors. The acquisition will help Microsoft catch up with Amazon Alexa, though the latter is more focused on enabling consumer applications of conversational AI.

Microsoft will use Semantic Machine’s acquisition to establish a conversational AI center of excellence in Berkeley to help it innovate in natural language interfaces.

Microsoft has been stepping up its products in conversational AI. It launched the digital assistant Cortana in 2015, as well as social chatbots like XiaoIce. The latest acquisition can help Microsoft beef up its ‘enterprise AI’ offerings.

As the use of NLP (natural language processing) increases in IoT products and services, more startups are getting traction from investors and established players. In June last year, Josh.ai, avoice-controlled home automation software has raised $8M.

Followed by it was SparkCognition that raised $32.5M Series B for its NLP-based threat intelligence platform.

It appears Microsoft’s acquisition of Semantic Machines was motivated by the latter’s strong AI team. The team includes technology entrepreneur Daniel Roth who sold his previous startups Voice Signal Technologies and Shaser BioScience for $300M and $100M respectively. Other team members include Stanford AI Professor Percy Liang, developer of Google Assistant Core AI technology and former Apple chief speech scientist Larry Gillick.

[SAPS] - A former company Director (57) is expected to appear in the Thabamoopo Magistrates Court in Lebowakgomo on 11 November 2024 for allegedly defrauding a pensioner an amount of R378 000.00 in the name of business.

[SAPS] - Polokwane based Hawks Serious Commercial Crime Investigation in collaboration with National Traffic Anti-corruption Unit arrested 11 suspects between the ages of 27 and 57 for alleged fraud at various Provinces during operation "SISFIKILE".

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[SAPS] One hundred and seventy one (171) murder suspects, 261 attempted murder suspects and 250 suspected rapists were among 12 593 suspects who were arrested during various operations by police in KwaZulu-Natal in the month of October. During such operations police also managed to recover 345 firearms and 2 998 rounds of ammunition of various calibre of firearms. Among the recovered firearms were 23 rifles and 17 homemade illegal guns.

[SAPS] SAPS members' continued efforts to prevent and detect crime yielded the following successes within the Joe Gqabi District as part of Operation Shanela during the week and start of the weekend .

[DA] Note to editors: Please find attached soundbite by Ian Cameron MP.

[Daily Maverick] Office of the Chief Justice reveals Constitutional Court has been unable to sit because of unreliable water supply. This article is free to read.Sign up for free or sign in to continue reading.Unlike our competitors, we don't force you to pay to read the news but we do need your email address to make your experience better.Create your free account or sign in FAQ | Contact Us Nearly there! Create a password to finish signing up with us: You want to receive First Thing, our flagship daily newsletter. Opt

[allAfrica]

[DA] It is a national embarrassment that the inability of the City of Johannesburg to supply water to its residents, business and public sector offices, has now led to the shutdown of operations at the Constitutional Court, on Constitution Hill in Braamfontein.

PCI-SIG DevCon 2024 – 32^nd Anniversary

For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32^nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.

Why Are Standards Like PCIe So Important?

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.

HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.

Figure 1. Evolution of PCIe Data Rates (source PCI-SIG)

What’s New This Year at DevCon?

At DevCon ’24, the PCIe 7.0 standard will take center stage, and Cadence is showing off a full suite of IP subsystem solutions for PCIe 7.0 this year.

What Sets Cadence Apart?

At Cadence, we believe in building a full subsystem for our testchips with eight lanes of PHY along with a full 8-lane controller. Adding a controller to our testchip significantly increases the efficiency and granularity in characterization and stress testing and enables us to demonstrate interoperability with real-world systems. We are also able to test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice. This approach significantly reduces the risks in our customers’ SoC designs.

Figure 2: Piper - Cadence PHY IP for PCIe 7.0

Figure 3: Industry’s first IP subsystem for PCIe 7.0

Which Market Is This For?

At a time when accelerated computing has gone mainstream, PCIe links are going to take on a role of higher importance in systems. Direct GPU-to-GPU communication is crucial for scaling out complex computational tasks across multiple graphics processing units (GPUs) or accelerators within servers or computing pods. There is a growing recognition within the industry of a need for scalable, open architecture in high-performance computing. As AI and data-intensive applications evolve, the demand for such technologies will likely increase, positioning PCIe 7.0 as a critical component in the next generation of interface IP.

Here's a recent article describing a potential use case for PCIe 7.0.

Figure 4: Example use case for PCIe 7.0

Why Are Optical Links Important?

It takes multiple buildings of data centers to train AI/ML models today. These buildings are increasingly being distributed across geographies, requiring optical fiber networks that are great at handling the increased bandwidth over long distances. However, these optical modules soon hit a power wall where all the budgeted power is used to drive the signal from point A to point B, and there is not enough power left to run the actual CPUs and GPUs. Such scenarios create a need for non-retimed, linear topologies. Linear Pluggable Optics (LPO) links can significantly reduce module power consumption and latency when compared to traditional Digital Signal Processing (DSP) based retimed optical solutions, which is critical for accelerating AI performance. Swapping from DSP-based solutions to LPO results in significant cost savings that help drive down expenditure due to lower power and cooling requirements, but this requires a robust high-performance ASIC to drive the optics rather than retimers/DSP.

To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare.

Figure 5: Example of ASIC driving linear optics

Compliance Is Key

For PCIe 6.0, the official compliance program has not started yet; this is typical for the SIG where the official compliance follows a few years after the spec is ratified to give enough time for the ecosystem to have initial products ready, and for test and equipment vendors to get their hardware/software up and running. At this time, PCIe Gen6 implementations can only be officially certified up to PCIe 5.0 level (the highest official compliance test suite that the SIG supports). We have taken our PCIe 6.0 IP subsystem solution to the SIG for multiple process nodes, and they are all listed as compliant. You can run this query on the pcisig.com website under the Developers->Integrators list by making the following selections:

Due to space limitations, not all combinations could be tested at the May workshop (e.g., N3 root port) – this will be tested in the next workshop.

Also, the SIG just held an “FYI” compliance event this week to bring together the ecosystem for confidential testing (no results were reported, and data cannot be shared outside without violating the PCI-SIG NDA). We participated in the event with multiple systems and can report that our systems have done quite well. The test ecosystem is not mature yet, and a few more FYI workshops will be conducted before the official compliance for 6.0 is launched. We have collaborated with all the key test vendors for electrical and protocol testing throughout the year. As early as the middle of last year, we were able to provide test cards to all these vendors to demo PCIe 6.0 capabilities in their booths at various events. Many of them recorded these videos, and they can be found online.

• Cadence Subsystem IP for PCIe 6.0: Protocol and Electrical Testing
• Cadence Subsystem IP for CXL Protocol Test Demo
• Cadence Subsystem IP for CXL2.0/3.0 Protocol Test Demo
• Cadence Subsystem IP for PCIe 6.0: Protocol Stack Demo

More at the PCI-SIG Developers Conference

Check us out at the PCI-SIG Developer’s conference on June 12 and 13 to see the following demonstrations:

• Robust performance of Cadence IP for PCIe 7.0 transmitting and receiving 128GT/s signals over non-retimed optics
• Capabilities of Cadence IP for PCIe 7.0 measured using oscilloscope instrumentation detailing its stable electrical performance and margin
• The reliability of Cadence IP for PCIe 6.0 interface using Test Equipment to characterize the PHY receiver quality
• A PCI-SIG-compliant Cadence IP subsystem for PCIe 6.0 optimized for both power and performance

As a leader in PCI Express, Anish Mathew of Cadence will share his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Figure 6: Cadence UIO Implementation Summary

Summary

Cadence showcased PCIe 7.0-ready IP at PCI-SIG Developers Conference 2023 and continues to lead in PCIe IP development, offering complete solutions in advanced nodes for PCIe 7.0 that will be generally available early next year. With a full suite of solutions encompassing PHYs, Controllers, Software, and Verification IP, Cadence is proud to be a member of the PCI-SIG community and is heavily invested in PCIe. Cadence was the first IP provider to bring complete subsystem solutions for PCIe 3.0, 4.0, 5.0, and 6.0 with industry-leading PPA and we are proud to continue this trend with our latest IP subsystem solution for PCIe 7.0, which sets new benchmarks for power, performance, area, and time to market.

The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence.  However, designing and signing off chiplets and packages individually is time-...(read more)

The automotive industry is currently on the cusp of a radical evolution, steering towards a future where cars are not just vehicles but sophisticated, software-defined vehicles (SDV). This shift is marked by an increased reliance on automation and a significant increase in the use of sensors to improve safety and reliability. However, the increasing number of sensors has led to higher compute demands and poses challenges in managing a wide variety of data. The traditional method of using separate processors to manage each sensor's data is becoming obsolete. The current trends necessitate a unified processing system that can deal with multimodal sensor data, utilizing traditional Digital Signal Processing (DSP) and AI-driven algorithms. This approach allows for more efficient and reliable sensor fusion, significantly enhancing vehicle perception. Developers often face difficulties adhering to stringent power, performance, area, and cost (PPAC) and timing constraints while designing automotive SoCs.

Cadence, with its groundbreaking products and AI-powered processors, is enabling designers and automotive manufacturers to meet the future sensor fusion demands within the automotive sector. At the recent CadenceLive Silicon Valley 2024, Amol Borkar, product marketing director at Cadence, showcased the company's dedication and forward-thinking solutions in a captivating presentation titled "Addressing Tomorrow’s Sensor Fusion Needs in Automotive Computing with Cadence." This blog aims to encapsulate the pivotal takeaways from the presentation. If you missed the chance to watch this presentation live, please click here to watch it.

Significant Trends in the Automotive Market – Industry Landscape

We are witnessing a revolution in automotive technology. Innovations like occupant and driver monitoring systems (OMS, DMS), 4D radar imaging, LiDAR technology, and 360-degree view are pushing the boundaries of what's possible, leading us into an era of remarkable autonomy levels—ranging from no feet or hands required to eventually no eyes needed on the road.

Sensor Fusion and Increasing Processing Demands—Sensor fusion effectively integrates data from different sensors to help vehicles understand their surroundings better. Its main benefit is in overcoming the limitations of individual sensors. For example, cameras provide detailed visual information but struggle in low-light or lousy weather. On the other hand, radar is excellent at detecting objects in these conditions but lacks the detail that cameras provide. By combining the data from multiple sensors, automotive computing can take advantage of their strengths while compensating for their weaknesses, resulting in a more reliable and robust system overall.

One thing to note is that the increased number of sensors produces various data types, leading to more pre-processing.

On-Device Processing—As the industry moves towards autonomy, there is an increasing need for on-device data processing instead of cloud computing to enable vehicles to make informed decisions. Embracing on-device processing is a significant advancement for facilitating real-time decisions and avoiding round-trip latency.

AI Adoption—AI has become integral to automotive applications, driving safety, efficiency, and user experience advancements. AI models offer superior performance and adaptability, making future-proofing a crucial consideration for automotive manufacturers. AI significantly enhances sensor fusion algorithms, offering scalability and adaptability beyond traditional rule-based approaches. Neural networks enable various fusion techniques, such as early fusion, late fusion, and mid-fusion, to optimize the integration and processing of sensor data.

Future Sensor Fusion Needs

Automotive architectures are continually evolving. With current trends and AI integration into radar and sensor fusion applications, SoCs should be modular, flexible, and programmable to meet market demands.

Heterogeneous Architecture- Today's vehicles are loaded with various sensors, each with a unique processing requirement. Running the application on the most suitable processor is essential to achieve the best PPA. To meet such requirements, modern automotive solutions require a heterogeneous compute approach, integrating domain-specific digital signal processors (DSPs), neural processing units (NPUs), central processing unit (CPU) clusters, graphics processing unit (GPU) clusters, and hardware accelerator blocks. A balanced heterogeneous architecture gives the best PPA solution.

Flexibility and Programmability- The industry has come a long way from using computer vision algorithms such as HOG (Histogram Oriented Gradient) to detect people and objects, HAR classifier to detect faces, etc., to CNN and LSTM-based AI to Transformer models and graphical neural networks (GNN). AI has evolved tremendously over the last ten years and continues to evolve. To keep up with the evolving rate of AI, SoC design must be flexible and programmable for updates if needed in the future.

Addressing the Sensor Fusion Needs with Cadence

Cadence offers a complete suite of hardware and software products to address the increasing compute requirements in automotive. The comprehensive portfolio of Tensilica products built on the robust 32-bit RISC architecture caters to various automotive CPU and AI needs. What makes them particularly appealing is their scalability, flexibility, and configurability, offering many options to meet diverse needs.

The Xtensa family of products offers high-quality, power-efficient CPUs. Tensilica family also includes AI processors like Neo NPUs for the best power, performance, and area (PPA) for AI inference on devices or more extensive applications. Cadence also offers domain-specific products for DSPs such as HIFI DSPs, specialized DSPs and accelerators for radar and vision-based processing, and a general-purpose family of products for floating point applications.

The ConnX family offers a wide range of DSPs, from compact and low-power to high-performance, optimized for radar, lidar, and communications applications in ADAS, autonomous driving, V2X, 5G/LTE/4G, wireless communications, drones, and robotics. Tensilica's ISO26262 certification ensures compliance with automotive safety standards, making it a trusted partner for advanced automotive solutions. The Cadence NeuroWeave Software Development Kit (SDK) provides customers with a uniform, scalable, and configurable ML interface and tooling that significantly improves time to market and better prepares them for a continuously evolving AI market. Cadence Tensilica offers an entire ecosystem of software frameworks and compilers for all programming styles.

Tensilica's comprehensive software stack supports programming for DSPs, NPUs, and accelerators using C++, OpenCL, Halide, and various neural network approaches. Middleware libraries facilitate applications such as SLAM, radar processing, and Eigen libraries, providing robust support for automotive software development.

Conclusion

Cadence’s Tensilica products offer a development toolchain and various IPs tailored for the automotive industry, covering audio, vision, radar, unified DSPs, and NPUs. With ISO certification and a robust partner ecosystem, Tensilica solutions are designed to meet the future needs of automotive computing, ensuring safety, efficiency, and innovation.

Learn More

• Cadence Automotive Solutions
• Cadence Automotive IP
• Sensor Fusion and ADAS in TSMC Automotive Processes
• Revolution on the Road: How Cadence is Driving the Future of Automotive Design!
• Taming Design Complexity in Chiplet-Based Automotive Electronics
• UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

The generative AI market is experiencing rapid growth, driven by the increasing parameter size of Large Language Models (LLMs). This growth is pushing the boundaries of performance requirements for training hardware within data centers. For an in-depth look at this, consider the insights provided in "HBM3E: All About Bandwidth". Once trained, these models are deployed across a diverse range of applications. They are transforming sectors such as finance, meteorology, image and voice recognition, healthcare, augmented reality, high-speed trading, and industrial, to name just a few.

The critical process that utilizes these trained models is called AI inference. Inference is the capability of processing real-time data through a trained model to swiftly and effectively generate predictions that yield actionable outcomes. While the AI market has primarily focused on the requirements of training infrastructure, there is an anticipated shift towards prioritizing inference as these models are deployed.

The computational power and memory bandwidth required for inference are significantly lower than those needed for training. Inference engines typically need between 300-700GB/s of memory bandwidth, compared to 1-3TB/s for training. Additionally, the cost of inference needs to be lower, as these systems will be widely deployed not only in data centers but also at the network's edge (e.g., 5G) and in end-user equipment like security cameras, cell phones, and automobiles.

When designing an AI inference engine, there are several memory options to consider, including DDR, LPDDR, GDDR, and HBM. The choice depends on the specific application, bandwidth, and cost requirements. DDR and LPDDR offer good memory density, HBM provides the highest bandwidth but requires 2.5D packaging, and GDDR offers high bandwidth using standard packaging and PCB technology.

The GDDR7 standard, announced by JEDEC in March of this year, features a data rate of up to 192GB/s per device, a chip density of 32Gb, and the latest data integrity features. The high data rate is achieved by using PAM3 (Pulse Amplitude Modulation) with 3 levels (+1, 0, -1) to transmit 3 bits over 2 cycles, whereas the current GDDR6 generation uses NRZ (non-return-to-zero) to transmit 2 bits over 2 cycles.

GDDR7 offers many advantages for AI Inference having the best balance of bandwidth and cost. For example, an AI Inference system requiring 500GB/s memory bandwidth will need only 4 GDDR7 DRAM running at 32Gbp/s (32 data bits x 32Gbp/s per pin = 1024Gb/s per DRAM). The same system would use 13 LPDDR5X PHYs running at 9.6Gbp/s, which is currently the highest data rate available (32 data bits x 9.6Gb/s = 307Gb/s per DRAM).

Cadence stands at the forefront of AI inference hardware support, being the first IP company to roll out GDDR7 PHYs capable of impressive speeds up to 36Gb/s across various process nodes. This milestone builds on Cadence's established leadership in GDDR6 PHY IP, which has been available since 2019. The company caters to a diverse client base spanning AI inference, graphics, automotive, and networking equipment.

While GDDR7 continues to utilize standard PCB board technology, the increased signal speeds seen in GDDR6 (20Gbp/s) and now GDDR7 (36Gb/s) calls for careful attention with the physical design to ensure optimized system performance. In addition to providing the PHY, Cadence also offers comprehensive PCB and package reference design, which are essential in helping customers achieve optimal signal and power integrity (SI/PI) for their systems.

Cadence is dedicated to ensuring customer success beyond just providing hardware. They provide expert support in SI/PI, collaborating closely with customers throughout the design process. This approach ensures that customers can benefit from Cadence's expertise in navigating the complexities of high-speed design and achieving optimal performance in their AI inference systems.

As the AI market continues to advance, Cadence remains at the forefront by offering a comprehensive memory IP portfolio tailored for every segment of this dynamic market. From DDR5 and HBM3E, which cater to the intensive demands of training in servers and high-performance computing (HPC), to LPDDR5X designed for low-end inference at the network edge and in consumer devices, Cadence's offerings cover a wide range of applications.

Looking to the future, Cadence is dedicated to innovating at the forefront of memory system performance, ensuring that the evolving needs of AI training and inference are met with the highest standards of excellence. Whether it's pushing the boundaries with GDDR7 or exploring new technologies, Cadence is dedicated to driving the AI revolution forward, one breakthrough at a time.

Learn more about Cadence GDDR7 PHY

Learn more about Cadence Simulation VIP for GDDR7.

Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet designs and demonstrate high data rate performance in TSMC's 3nm technology(read more)

Staying ahead of the curve is essential to meeting customer needs. Cadence has consistently demonstrated its commitment to innovation, and its latest IP portfolio available on TSMC's 3nm (N3) process is no exception. Today, rapid advancements in AI/ML, hyperscale computing (HPC), and the automotive industry are driving significant changes in technology. Let's explore the impressive array of IP that Cadence offers on this advanced node.

Memory Solutions: High-Speed and Power-Efficient

Cadence's DDR5 12.8G MRDIMM IP supports the highest speed grade Gen2 MRDIMMs and features a fully hardened PHY optimized to the customer's floorplan. The LPDDR5X IP is silicon-proven at 9.6Gbps and is ideal for power-sensitive applications, offering a fully integrated memory subsystem.

GDDR7: Leading the Way in Graphics Memory

Cadence has achieved a significant milestone with the world's first silicon-proven GDDR7 IP, supporting data rates up to 32Gbps. This IP offers the best price/performance ratio for AI interfaces, making it a game-changer in the graphics memory domain.

PCIe and CXL Solutions: Robust and Reliable

Cadence's PCIe 3.0 IP is a mature and production-proven solution available across a wide range of process nodes from 28nm to 3nm. It offers a versatile multi-link architecture for optimum SoC configurability and flexible use cases. The PCIe 6.0 and CXL 3.x solutions are silicon-proven, power-optimized, and highly robust, with jitter-tolerant capabilities. These IP are the only subsystem proven with eight lanes of controller and PHY in silicon, ensuring interoperability with leading test vendors and OEMs.

UCIe PHY: Setting New Standards

The UCIe PHY IP from Cadence are set to be generally available after successful silicon characterization in both standard and advanced package options on the TSMC N3 (3nm) process. These IP demonstrate significantly better power, performance, and area (PPA) metrics than the specifications, with a bit error rate (BER) better than 1E-27 compared to the spec of 1E-15. The power consumption is also notably lower than the spec limit, ensuring a simpler integration with a best-in-class power profile.

112G PHY IP: Pushing the Boundaries of Performance

Cadence's 112G PHY IP are designed to meet the demands of high-speed data transmission. The 112G-ULR PHY IP, characterized in the 3nm process, showcases exceptional performance with support for insertion loss over 45dB at data rates ranging from 1.25Gbps to 112.5Gbps. This IP is optimized for both power and area, making it a versatile choice for various applications. The 112G-VSR/MR PHY IP also stands out with its excellent power and performance metrics, making it ideal for short-reach applications and optical interconnects. Additionally, the 112G PAM4 PHY solutions cater to hyperscale, AI, HPC, and optics applications, featuring a mature DSP-based SerDes architecture with advanced techniques such as reflection cancellation.

Cadence's IP portfolio on TSMC N3 shows innovation and expertise to solve today's design challenges. From high-speed PHY IP to robust PCIe and CXL solutions and advanced memory IP, Cadence continues to lead the way in semiconductor IP development. These solutions not only meet but exceed industry standards, ensuring that customers can confidently achieve their design goals. Stay tuned for more updates on Cadence's groundbreaking advancements in semiconductor technology.

Learn more about Cadence IP and other silicon solutions.

anyone know what is "cell with Zero maximum clock transition time"  ?

not zero transition, not maximum transtion, it is zero maximum clock transition time.

it means X0 cell? (drive-strength)

can you explain? 

thanks :-)

Hi all,

I have off grid violations on M2 layer. I have tried ecoRoute -fix_drc and deleting violations and rerouting. But the tool is still placing these routes off grid. The on grid option in nanoroute is turned on. Since there is a fat metal closer to these routes, the tool is honouring the drc and not placing the metals on track. How do I ignore drc while routing? Also if there is any other way I can fix it, please let me know 

I am getting the cut_spacing violation in the power plan, my design has two power rails, and the via is not formed for two rails, only one rail getting via, I used edit power via and modified the cut_space violation.

how to solve this problem.