A vapor purge valve in an engine is provided. The vapor purge valve includes a purge valve inlet, a purge valve outlet, and a muffler including a housing at least partially enclosing a diffuser in fluidic communication with the purge valve inlet and the purge valve outlet.

A method of controlling fuel injection in a dual fuel engine system includes determining, with a first controller, a diesel injection pulse indicative of a first amount of diesel fuel to be injected into a combustion chamber of the engine and a first timing at which the first amount of diesel fuel is to be injected. The method also includes determining, with a second controller, a combined injection pulse based on the diesel injection pulse. The method further includes injecting the second amount of diesel fuel and the third amount of natural gas into the combustion chamber in accordance with the combined injection pulse. In such a method, injection in accordance with the combined injection pulse results in a combustion event characterized by a second combustion characteristic substantially equal to a first combustion characteristic associated with the diesel injection pulse.

An air cooler line is provided. The air cooler lines includes a first air cooler having a plurality of air flow conduits, each of the air flow conduits including an inlet, and a first air flow deflector extending across peripheral portions of the inlets and fixedly coupled to the air flow conduits and a second air cooler having a plurality of air flow conduits, each of the air flow conduits including an inlet, and a second air flow deflector extending across peripheral portions of the inlets and fixedly coupled to the air flow conduits, the second air flow deflector differing in at least one of size and geometry than the first air flow deflector.

Embodiments for an engine system are provided. One example internal combustion engine having at least one cylinder head and at least two cylinders, in which each cylinder has at least one inlet opening for the supply of combustion air into the cylinder, comprises an intake line leading to each inlet opening, an overall intake line where the intake lines of at least two cylinders merge, such that a distributor junction point is formed, and a heating device arranged in the overall intake line which has at least one strip-like heating element, a first narrow side of a cross section of which faces toward intake combustion air flow, wherein the heating device is arranged adjacent to the distributor junction point at which the intake lines merge to form the overall intake line, a spacing between the heating device and the distributor junction point being smaller than the diameter of a cylinder.

An air intake manifold for an engine includes an air inlet to receive a flow of compressed charge air, and multiple runners to deliver cooled compressed charge air to corresponding combustion cylinders of the engine. A charge air cooler is arranged within the intake manifold between the air inlet and the runners, and includes a first core section and a second core section. The first and second core sections are arranged fluidly in parallel with respect to the flow of compressed charge air, so that the charge air is divided into a first portion that is substantially directed through the first core section to a first subset of the runners, and a second portion that is substantially directed through the second core section to a second subset of the runners.

A charge air cooler includes a housing and a heat exchanger core positioned within the housing. The heat exchanger core includes a first core section, a second core section, and a centrally located section positioned between the first core section and the second core section. The charge air cooler also includes a plurality of coolant circuits. Each coolant circuit extends through at least one of the first and second core sections. The charge air cooler further includes a coolant inlet extending from the centrally located section to deliver coolant to the plurality of coolant circuits, and a coolant outlet extending from the centrally located section to receive coolant from the plurality of coolant circuits. The charge air cooler also includes a fastener extending through the centrally located section of the core to secure the core to the housing.

A method for controlling combustion in an engine is provided. The method comprises under a first condition, adjusting an EGR amount of a total cylinder charge in response to engine out NOx levels being below a first threshold. In this way, NOx levels may be used as feedback to control combustion stability.

An exhaust gas recirculation device is provided. The device recirculates, from an exhaust system to an intake system, a part of exhaust gas from a plurality of cylinders of a multi-cylinder engine as EGR gas. The device includes a single EGR pipe extending from the exhaust system toward the intake system, an EGR manifold branching from a downstream end portion of the EGR pipe toward each cylinder, and an EGR valve for adjusting an EGR gas amount. The EGR manifold has one or more common EGR passages having a single pipe portion and branched pipe portions, and one or more independent EGR passages. Each shape of the common and independent EGR passages is set so that a communicating path in the EGR manifold communicating an arbitrary cylinder with a cylinder where combustion is performed subsequently thereto has the same volume for any cylinder combination having the adjacent combustion order.

As one example, a fuel rail assembly for supplying pressurized fuel to a plurality of cylinders of an engine is provided. The fuel rail assembly includes a fuel rail housing defining an internal fuel rail volume having at least a first region and a second region; a fuel separation membrane element disposed within the fuel rail housing that segregates the first region from the second region. The membrane element can be configured to pass a first component of a fuel mixture such as an alcohol through the membrane element from the first region to the second region at a higher rate than a second component of the fuel mixture such as a hydrocarbon. The separated alcohol and hydrocarbon components can be provided to the engine in varying relative amounts based on operating conditions.

Embodiments of systems and methods for tuning a turbine are provided. In one embodiment, a method may include receiving at least one of a measured operating parameter or a modeled operating parameter of a turbine during operation; and tuning the turbine during operation. The turbine may be tuned during operation by applying the measured operating parameter or modeled operating parameter or parameters to at least one operational boundary model, applying the measured operating parameter or modeled operating parameter or parameters to at least one scheduling algorithm, comparing the output of the operational boundary model or models to the output of the scheduling algorithm or algorithms to determine at least one error term, and closing loop on the one error term or terms by adjusting at least one turbine control effector during operation of the turbine.

In an engine having a plurality of cylinders in which a plurality of fuel injection valves are provided respectively, fuel is injected at a predetermined injection ratio, and an abnormality of air-fuel ratio variation is detected. If a fuel injection amount of at least one of the plurality of the fuel injection valves is smaller than a predetermined reference value, the fuel injection amount is increased so as to become equal to or larger than the reference value.

Methods and systems are provided for reducing late burn induced cylinder pre-ignition events. Forced entry of residuals from a late burning cylinder into a neighboring cylinder may be detected based on engine block vibrations sensed in a window during an open exhaust valve of the late burning cylinder. In response to the entry of residuals, a pre-ignition mitigating action, such as fuel enrichment or deactivation, is performed in the neighboring cylinder.

Provided is a timing adjustment system having improved control for achieving a target rotational phase. The valve timing adjustment system includes a displacement mechanism unit that displaces a rotational phase of a camshaft relative to a crankshaft of an internal combustion engine; a locking mechanism unit that locks the rotational phase at an intermediate locked phase positioned within a displacement range of the rotational phase; a hydraulic pathway that hydraulically drives the displacement mechanism unit and the locking mechanism unit; and a control unit including a control system that controls operations of the hydraulic control valve. The control unit changes a temporal responsiveness of the control system based on a displacement force that displaces the rotational phase.

Method and system for operating a compression engine on ether containing fuel obtained by conversion of a primary fuel based on alcohol comprising the steps and means for: (a) continuously withdrawing the primary fuel based on alcohol from a fuel tank and pressurising the primary fuel based on alcohol in its liquid form to a final engine injection pressure; (b) continuously introducing the pressurized primary fuel based on alcohol into a fuel accumulation chamber; (c) continuously distributing the pressurized primary fuel based on alcohol into pipes connecting the accumulation chamber with fuel injectors of the engine; (d) prior to the fuel injectors continuously converting the pressurised primary fuel based on alcohol to an ether containing fuel by contact with an alcohol dehydration catalyst being arranged in each of the pipes upstream the fuel injectors; (e) continuously injecting the ether containing fuel at injection pressure into the engine; and (f) continuously withdrawing a part of the introduced primary fuel based on alcohol from the accumulation chamber; and (g) depressurising and recycling the withdrawn primary fuel based on alcohol to the fuel tank.

A valve timing adjusting device for and engine includes a sprocket configured to rotate by receiving drive power from a driving shaft, a vane rotor fixed to a driven shaft so as to be rotatable relative to the sprocket, a housing that includes an oil chamber housing the vane rotor and is fixed to one end in a thickness direction of the sprocket, a bolt fixing the sprocket to the housing, and a knock pin inserted into a sprocket hole formed in the sprocket at one end thereof and into a housing hole formed in the housing at the other end thereof to restrict relative relation between the sprocket and the housing. The knock pin abuts against an inner wall of the sprocket hole at one end thereof, and abuts against an inner wall of the housing hole at the other end thereof.

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Various systems and methods for implementing fuse-based integrity protection are described herein. A system for validating a read-only memory (ROM), the system comprising a ROM reader logic, implemented at least partly in hardware, to: access a read-only memory (ROM) having a plurality of permanently programmable electric couplings (PPECs), the PPECs having been programmed; survey a number of permanently altered PPECs in the set of PPECs to produce a counter value; read a binary representation of the counter value from PPEC values stored as a PPEC signature; and read a binary representation of the binary complement of the counter value from PPEC values in the PPEC signature; and a ROM validation logic, implemented at least partly, in hardware, to verify the integrity of the ROM using a combination of at least two of: the counter value, the binary representation of the counter value, and the binary representation of the binary complement of the counter value.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. Firstly, a selected memory cell of the memory array is determined, wherein one of the plural bit lines connected with the selected memory cell is a selected bit line and the other bit lines are unselected bit lines. Then, the unselected bit lines are precharged to a precharge voltage. Then, the selected bit line is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to at least one result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

To provide a magnetic element capable of performing skyrmion transfer, a skyrmion memory to which this magnetic element is applied, and a shift register, for example, a magnetic element capable of performing skyrmion transfer is provided, the magnetic element providing a transverse transfer arrangement in which the skyrmion is transferred substantially perpendicular to a current between an upstream electrode and a downstream electrode, and including a plurality of stable positions in which the skyrmion exists more stably than in other regions of a magnet, and a skyrmion sensor that detects a position of the skyrmion.

To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a β-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter λ being generated, is such that 2λ>Wm>λ/2 and 2λ>hm>λ/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that λ≧W>λ/4 and 2λ>h>λ/2.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

An SRAM includes an SRAM array comprising a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising:first and second conduction electrodes (201, 202);a channel zone (203) arranged between the first and second conduction electrodes;a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222);an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·λ>Wm≧λ, where λ denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·λ>Hm≧λ, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

A dual inline memory module can include a module card having first and second opposed surfaces and a plurality of microelectronic elements each having a surface facing a surface of the module card. The module card can have a plurality of parallel edge contacts, the edge contacts including first and second contacts, the first and second contacts configured to carry command and address information and data signals corresponding to first and second memory channels, respectively, the first memory channel being independent from the second memory channel. Each microelectronic element can have memory storage array function being of type LPDDRx and being configured to sample the command and address information at least twice per clock cycle. The plurality of microelectronic elements can be configured to implement the first and second memory channels. The first and second microelectronic elements can be configured for communication via the first and second contacts, respectively.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

An electronic device includes a semiconductor memory that includes: a memory cell coupled between a first line and a second line; a first selection block configured to select the first line; a second selection block configured to select the second line; an alternate current supply block configured to supply, during a read operation, an alternate current corresponding to a resistance state of the memory cell; and a sensing block configured to sense, during the read operation, at least one of a cell current flowing through the memory cell and the alternate current.

Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.